Fix assembly code for atomic operations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49869 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td
index 1ac0519e798c24ee32a64ef2241d8af4abacd05d..7c97e9207d0068280123fb26f98e6f1afb8cee23 100644 (file)
--- a/lib/Target/X86/X86InstrInfo.td
+++ b/lib/Target/X86/X86InstrInfo.td
@@ -2548,9 +2548,9 @@ def EH_RETURN   : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
 
 let Defs = [EAX, EFLAGS], Uses = [EAX] in {
 def CMPXCHG32 : I<0xB1, Pseudo, (outs), (ins i32mem:$ptr, GR32:$swap),
-               "cmpxchgl $swap,$ptr", []>, TB;
+               "cmpxchg{l} $swap,$ptr", []>, TB;
 def LCMPXCHG32 : I<0xB1, Pseudo, (outs), (ins i32mem:$ptr, GR32:$swap),
-               "lock cmpxchgl $swap,$ptr",
+               "lock cmpxchg{l} $swap,$ptr",
                [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
 }
 let Defs = [EAX, EBX, ECX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
@@ -2563,55 +2563,55 @@ def LCMPXCHG8B : I<0xC7, Pseudo, (outs), (ins i32mem:$ptr),
 
 let Defs = [AX, EFLAGS], Uses = [AX] in {
 def CMPXCHG16 : I<0xB1, Pseudo, (outs), (ins i16mem:$ptr, GR16:$swap),
-               "cmpxchgw $swap,($ptr)", []>, TB, OpSize;
+               "cmpxchg{w} $swap,($ptr)", []>, TB, OpSize;
 def LCMPXCHG16 : I<0xB1, Pseudo, (outs), (ins i16mem:$ptr, GR16:$swap),
-               "lock cmpxchgw $swap,$ptr",
+               "lock cmpxchg{w} $swap,$ptr",
                [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
 }
 let Defs = [AL, EFLAGS], Uses = [AL] in {
 def CMPXCHG8 : I<0xB0, Pseudo, (outs), (ins i8mem:$ptr, GR8:$swap),
-               "cmpxchgb $swap,($ptr)", []>, TB;
+               "cmpxchg{b} $swap,($ptr)", []>, TB;
 def LCMPXCHG8 : I<0xB0, Pseudo, (outs), (ins i8mem:$ptr, GR8:$swap),
-               "lock cmpxchgb $swap,$ptr",
+               "lock cmpxchg{b} $swap,$ptr",
                [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
 }
 
 let Constraints = "$val = $dst", Defs = [EFLAGS] in {
 def LXADD32 : I<0xC1, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
-               "lock xadd $val, $ptr", 
+               "lock xadd{l} $val, $ptr", 
                [(set GR32:$dst, (atomic_las_32 addr:$ptr, GR32:$val))]>,
                 TB, LOCK;
 def LXADD16 : I<0xC1, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
-               "lock xadd $val, $ptr", 
+               "lock xadd{w} $val, $ptr", 
                [(set GR16:$dst, (atomic_las_16 addr:$ptr, GR16:$val))]>,
                 TB, OpSize, LOCK;
 def LXADD8  : I<0xC0, Pseudo, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
-               "lock xadd $val, $ptr", 
+               "lock xadd{b} $val, $ptr", 
                [(set GR8:$dst, (atomic_las_8 addr:$ptr, GR8:$val))]>,
                 TB, LOCK;
 def XADD32 : I<0xC1, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
-               "xadd $val, $ptr", []>, TB;
+               "xadd{l} $val, $ptr", []>, TB;
 def XADD16 : I<0xC1, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
-               "xadd $val, $ptr", []>, TB, OpSize;
+               "xadd{w} $val, $ptr", []>, TB, OpSize;
 def XADD8  : I<0xC0, Pseudo, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
-               "xadd $val, $ptr", []>, TB;
+               "xadd{b} $val, $ptr", []>, TB;
 
 def LXCHG32 : I<0x87, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
-               "lock xchg $val, $ptr", 
+               "lock xchg{l} $val, $ptr", 
                [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>, LOCK;
 def LXCHG16 : I<0x87, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
-               "lock xchg $val, $ptr", 
+               "lock xchg{w} $val, $ptr", 
                [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>, 
                 OpSize, LOCK;
 def LXCHG8  : I<0x86, Pseudo, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
-               "lock xchg $val, $ptr", 
+               "lock xchg{b} $val, $ptr", 
                [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>, LOCK;
 def XCHG32 : I<0x87, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
-               "xchg $val, $ptr", []>;
+               "xchg{l} $val, $ptr", []>;
 def XCHG16 : I<0x87, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
-               "xchg $val, $ptr", []>, OpSize;
+               "xchg{w} $val, $ptr", []>, OpSize;
 def XCHG8  : I<0x86, Pseudo, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
-               "xchg $val, $ptr", []>;
+               "xchg{b} $val, $ptr", []>;
 }
 
 //===----------------------------------------------------------------------===//