{.frequency = 1608 * 1000, .cpu_volt = 1350 * 1000, .logic_volt = 1200 * 1000},//1.325V/1.175V
{.frequency = CPUFREQ_TABLE_END},
};
+static struct cpufreq_frequency_table dvfs_gpu_table[] = {
+ {.frequency = 266 * 1000, .index = 1000 * 1000},
+ {.frequency = 400 * 1000, .index = 1350 * 1000},
+ {.frequency = CPUFREQ_TABLE_END},
+};
+
+static struct cpufreq_frequency_table dvfs_ddr_table[] = {
+ {.frequency = 300 * 1000, .index = 1000 * 1000},
+ {.frequency = 400 * 1000, .index = 1100 * 1000},
+ {.frequency = CPUFREQ_TABLE_END},
+};
#define DVFS_CPU_TABLE_SIZE (ARRAY_SIZE(dvfs_cpu_logic_table))
static struct cpufreq_frequency_table cpu_dvfs_table[DVFS_CPU_TABLE_SIZE];
{
rk30_clock_data_init(periph_pll_default, codec_pll_default, RK30_CLOCKS_DEFAULT_FLAGS);
dvfs_set_arm_logic_volt(dvfs_cpu_logic_table, cpu_dvfs_table, dep_cpu2core_table);
+ dvfs_set_freq_volt_table(clk_get(NULL, "gpu"), dvfs_gpu_table);
+ dvfs_set_freq_volt_table(clk_get(NULL, "ddr"), dvfs_ddr_table);
}
MACHINE_START(RK30, "RK30board")
\r
static LIST_HEAD(rk_dvfs_tree);\r
static DEFINE_MUTEX(mutex);\r
+static DEFINE_MUTEX(rk_dvfs_mutex);\r
\r
extern int rk30_clk_notifier_register(struct clk *clk, struct notifier_block *nb);\r
extern int rk30_clk_notifier_unregister(struct clk *clk, struct notifier_block *nb);\r
ret = -1;\r
} else {\r
vd = clk->dvfs_info->vd;\r
- mutex_lock(&vd->dvfs_mutex);\r
+ // mutex_lock(&vd->dvfs_mutex);\r
+ mutex_lock(&rk_dvfs_mutex);\r
ret = vd->vd_dvfs_target(clk, rate);\r
- mutex_unlock(&vd->dvfs_mutex);\r
+ mutex_unlock(&rk_dvfs_mutex);\r
+ // mutex_unlock(&vd->dvfs_mutex);\r
}\r
DVFS_DBG("%s(%s(%lu)),is end\n", __func__, clk->name, rate);\r
return ret;\r
if (!vd)\r
return -1;\r
mutex_lock(&mutex);\r
- mutex_init(&vd->dvfs_mutex);\r
+ //mutex_init(&vd->dvfs_mutex);\r
list_add(&vd->node, &rk_dvfs_tree);\r
INIT_LIST_HEAD(&vd->pd_list);\r
INIT_LIST_HEAD(&vd->req_volt_list);\r
DVFS_ERR("%s can't get dvfs regulater\n", clk->name);\r
return -1;\r
}\r
-\r
- // clk_round_rate_nolock(clk, rate_hz);\r
+ \r
rate_new = rate_hz;\r
rate_old = clk_get_rate(clk);\r
+ if(!is_suport_round_rate(clk))\r
+ {\r
+ rate_new=clk_round_rate_nolock(clk, rate_hz);\r
+ }\r
+ if(rate_new==rate_old)\r
+ return 0;\r
+\r
\r
// DVFS_DBG("dvfs(%s) round rate(%lu)(rount %lu)\n",dvfs_clk->name,rate_hz,rate_new);\r
\r
return -1;\r
}\r
volt_old = dvfs_clk->vd->cur_volt;\r
-\r
volt_clk_old = dvfs_clk->set_volt;\r
-\r
dvfs_clk->set_volt = clk_fv.index;\r
-\r
volt_new = dvfs_vd_get_newvolt_byclk(dvfs_clk);\r
\r
DVFS_DBG("dvfs--(%s),volt=%d(was %dmV),rate=%lu(was %lu),vd%u=(was%u)\n",\r
\r
if (flag_core_set_volt_err) {\r
/* It means the last time set voltage error */ \r
+ if (!IS_ERR(dvfs_clk->vd->regulator))\r
+ flag_set_volt_correct = dvfs_regulator_get_voltage(dvfs_clk->vd->regulator);\r
+ else {\r
+ DVFS_ERR("dvfs regulator is ERROR\n");\r
+ }\r
+\r
flag_set_volt_correct = dvfs_regulator_get_voltage(dvfs_clk->vd->regulator);\r
if (flag_set_volt_correct <= 0) {\r
DVFS_ERR("%s (clk:%s),volt=%d(was %dmV),rate=%lu(was %lu), try to reload core_volt error %d!!! stop scaling\n", \r
};\r
\r
static struct cpufreq_frequency_table gpu_dvfs_table[] = {\r
- {.frequency = 100 * DVFS_KHZ, .index = 1000 * DVFS_MV},\r
- {.frequency = 200 * DVFS_KHZ, .index = 1050 * DVFS_MV},\r
+ {.frequency = 90 * DVFS_KHZ, .index = 1100 * DVFS_MV},\r
+ {.frequency = 180 * DVFS_KHZ, .index = 1150 * DVFS_MV},\r
{.frequency = 300 * DVFS_KHZ, .index = 1100 * DVFS_MV},\r
{.frequency = 400 * DVFS_KHZ, .index = 1150 * DVFS_MV},\r
{.frequency = 500 * DVFS_KHZ, .index = 1200 * DVFS_MV},\r