arm64: dts: add more nodes for Rockchip rk3368 core dtsi

Add these nodes for Rockchip rk3368 core dtsi:
- AMBA(DMAC_PERH/DMAC_BUS)
- I2S/PCM(2CH/8CH)
- ddrpctl
- pmu

Change-Id: I7d281e820732dca468728482e8e4dc63d89ec85a
Signed-off-by: Jianqun xu <jay.xu@rock-chips.com>

diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index 343f3fd9017bd1d87b8c3813a4d214e81def2f24..39f98b578aac01eeec78a025bf021412f1e50682 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -197,6 +197,33 @@
                                     <&cpu_b2>, <&cpu_b3>;
        };
 
+       amba {
+               compatible = "arm,amba-bus";
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               dmac_peri: dma-controller@ff250000 {
+                       compatible = "arm,pl330", "arm,primecell";
+                       reg = <0x0 0xff250000 0x0 0x4000>;
+                       interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+                       #dma-cells = <1>;
+                       clocks = <&cru ACLK_DMAC_PERI>;
+                       clock-names = "apb_pclk";
+               };
+
+               dmac_bus: dma-controller@ff600000 {
+                       compatible = "arm,pl330", "arm,primecell";
+                       reg = <0x0 0xff600000 0x0 0x4000>;
+                       interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+                       #dma-cells = <1>;
+                       clocks = <&cru ACLK_DMAC_BUS>;
+                       clock-names = "apb_pclk";
+               };
+       };
+
        psci {
                compatible = "arm,psci-0.2";
                method = "smc";
@@ -445,6 +472,11 @@
                status = "disabled";
        };
 
+       ddrpctl: syscon@ff610000 {
+               compatible = "rockchip,rk3368-ddrpctl", "syscon";
+               reg = <0x0 0xff610000 0x0 0x400>;
+       };
+
        i2c0: i2c@ff650000 {
                compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
                reg = <0x0 0xff650000 0x0 0x1000>;
@@ -526,6 +558,11 @@
                status = "disabled";
        };
 
+       pmu: power-management@ff730000 {
+               compatible = "rockchip,rk3368-pmu", "syscon";
+               reg = <0x0 0xff730000 0x0 0x1000>;
+       };
+
        pmugrf: syscon@ff738000 {
                compatible = "rockchip,rk3368-pmugrf", "syscon";
                reg = <0x0 0xff738000 0x0 0x1000>;
@@ -566,6 +603,34 @@
                      (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
        };
 
+       i2s_2ch: i2s-2ch@ff890000 {
+               compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
+               reg = <0x0 0xff898000 0x0 0x1000>;
+               interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <2>;
+               #size-cells = <0>;
+               dmas = <&dmac_bus 6>, <&dmac_bus 7>;
+               dma-names = "tx", "rx";
+               clock-names = "i2s_hclk", "i2s_clk";
+               clocks = <&cru HCLK_I2S_2CH>, <&cru SCLK_I2S_2CH>;
+               status = "disabled";
+       };
+
+       i2s_8ch: i2s-8ch@ff898000 {
+               compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
+               reg = <0x0 0xff898000 0x0 0x1000>;
+               interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               dmas = <&dmac_bus 0>, <&dmac_bus 1>;
+               dma-names = "tx", "rx";
+               clock-names = "i2s_hclk", "i2s_clk";
+               clocks = <&cru HCLK_I2S_8CH>, <&cru SCLK_I2S_8CH>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&i2s_8ch_bus>;
+               status = "disabled";
+       };
+
        pinctrl: pinctrl {
                compatible = "rockchip,rk3368-pinctrl";
                rockchip,grf = <&grf>;
@@ -754,6 +819,20 @@
                        };
                };
 
+               i2s {
+                       i2s_8ch_bus: i2s-8ch-bus {
+                               rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_none>,
+                                               <2 13 RK_FUNC_1 &pcfg_pull_none>,
+                                               <2 14 RK_FUNC_1 &pcfg_pull_none>,
+                                               <2 15 RK_FUNC_1 &pcfg_pull_none>,
+                                               <2 16 RK_FUNC_1 &pcfg_pull_none>,
+                                               <2 17 RK_FUNC_1 &pcfg_pull_none>,
+                                               <2 18 RK_FUNC_1 &pcfg_pull_none>,
+                                               <2 19 RK_FUNC_1 &pcfg_pull_none>,
+                                               <2 20 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+               };
+
                sdio0 {
                        sdio0_bus1: sdio0-bus1 {
                                rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;