dts: vt8500: Add ARM, AHB, APB and DDR clock nodes to SoC files
authorTony Prisk <linux@prisktech.co.nz>
Fri, 10 May 2013 05:44:58 +0000 (17:44 +1200)
committerTony Prisk <linux@prisktech.co.nz>
Sun, 12 May 2013 08:31:15 +0000 (20:31 +1200)
Add support for the ARM, AHB, APB and DDR clocks found on the
WM8505, WM8650, WM8750 and WM8850 SoCs.

These clocks are gateable, but the enable part of the clock definition
is left out as there are no users for these clocks, and we don't want
them being disabled at boot, but it does provide users the ability to
check the current rate of these clocks.

Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
arch/arm/boot/dts/wm8505.dtsi
arch/arm/boot/dts/wm8650.dtsi
arch/arm/boot/dts/wm8750.dtsi
arch/arm/boot/dts/wm8850.dtsi

index 702d866b6f57dbba2aac76f34537a176587176a7..a1a854b8a4547c1d47d8707c262335f7cdf66acd 100644 (file)
                                        reg = <0x20c>;
                                };
 
+                               clkarm: arm {
+                                       #clock-cells = <0>;
+                                       compatible = "via,vt8500-device-clock";
+                                       clocks = <&plla>;
+                                       divisor-reg = <0x300>;
+                               };
+
+                               clkahb: ahb {
+                                       #clock-cells = <0>;
+                                       compatible = "via,vt8500-device-clock";
+                                       clocks = <&pllb>;
+                                       divisor-reg = <0x304>;
+                               };
+
+                               clkapb: apb {
+                                       #clock-cells = <0>;
+                                       compatible = "via,vt8500-device-clock";
+                                       clocks = <&pllb>;
+                                       divisor-reg = <0x350>;
+                               };
+
+                               clkddr: ddr {
+                                       #clock-cells = <0>;
+                                       compatible = "via,vt8500-device-clock";
+                                       clocks = <&plld>;
+                                       divisor-reg = <0x310>;
+                               };
+
                                clkuart0: uart0 {
                                        #clock-cells = <0>;
                                        compatible = "via,vt8500-device-clock";
index 46a4603c9c539610884bfbeeb3d3897fbf0ba9bd..7525982262ac9896285031462e45b23b4020d9c7 100644 (file)
                                        reg = <0x210>;
                                };
 
+                               clkarm: arm {
+                                       #clock-cells = <0>;
+                                       compatible = "via,vt8500-device-clock";
+                                       clocks = <&plla>;
+                                       divisor-reg = <0x300>;
+                               };
+
+                               clkahb: ahb {
+                                       #clock-cells = <0>;
+                                       compatible = "via,vt8500-device-clock";
+                                       clocks = <&pllb>;
+                                       divisor-reg = <0x304>;
+                               };
+
+                               clkapb: apb {
+                                       #clock-cells = <0>;
+                                       compatible = "via,vt8500-device-clock";
+                                       clocks = <&pllb>;
+                                       divisor-reg = <0x320>;
+                               };
+
+                               clkddr: ddr {
+                                       #clock-cells = <0>;
+                                       compatible = "via,vt8500-device-clock";
+                                       clocks = <&plld>;
+                                       divisor-reg = <0x310>;
+                               };
+
                                clkuart0: uart0 {
                                        #clock-cells = <0>;
                                        compatible = "via,vt8500-device-clock";
                                        enable-bit = <2>;
                                };
 
-                               arm: arm {
-                                       #clock-cells = <0>;
-                                       compatible = "via,vt8500-device-clock";
-                                       clocks = <&plla>;
-                                       divisor-reg = <0x300>;
-                               };
-
-                               sdhc: sdhc {
+                               clksdhc: sdhc {
                                        #clock-cells = <0>;
                                        compatible = "via,vt8500-device-clock";
                                        clocks = <&pllb>;
index e4a1e8553e30df4f704e80f141ae6b6ac0a39b0f..557a9c2ace49faadac1f0698b4f32d8361a1f1eb 100644 (file)
                                        divisor-reg = <0x304>;
                                };
 
+                               clkapb: apb {
+                                       #clock-cells = <0>;
+                                       compatible = "via,vt8500-device-clock";
+                                       clocks = <&pllb>;
+                                       divisor-reg = <0x320>;
+                               };
+
                                clkddr: ddr {
                                        #clock-cells = <0>;
                                        compatible = "via,vt8500-device-clock";
index 59aaad98f5441732e643519c932747838f5c6128..1f49f54c38d2ca0c6b39799a16ba4b137e91fec1 100644 (file)
                                        reg = <0x218>;
                                };
 
+                               clkarm: arm {
+                                       #clock-cells = <0>;
+                                       compatible = "via,vt8500-device-clock";
+                                       clocks = <&plla>;
+                                       divisor-reg = <0x300>;
+                               };
+
+                               clkahb: ahb {
+                                       #clock-cells = <0>;
+                                       compatible = "via,vt8500-device-clock";
+                                       clocks = <&pllb>;
+                                       divisor-reg = <0x304>;
+                               };
+
+                               clkapb: apb {
+                                       #clock-cells = <0>;
+                                       compatible = "via,vt8500-device-clock";
+                                       clocks = <&pllb>;
+                                       divisor-reg = <0x320>;
+                               };
+
+                               clkddr: ddr {
+                                       #clock-cells = <0>;
+                                       compatible = "via,vt8500-device-clock";
+                                       clocks = <&plld>;
+                                       divisor-reg = <0x310>;
+                               };
+
                                clkuart0: uart0 {
                                        #clock-cells = <0>;
                                        compatible = "via,vt8500-device-clock";