[Hexagon] Adding round reg/imm and bitsplit instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225188 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Hexagon/HexagonInstrInfo.td b/lib/Target/Hexagon/HexagonInstrInfo.td
index d73adc66b5cf3a61bf127dbf6504afc63a6234da..7ce65f345cabaf6e36a1b29aad831874aa518866 100644 (file)
--- a/lib/Target/Hexagon/HexagonInstrInfo.td
+++ b/lib/Target/Hexagon/HexagonInstrInfo.td
@@ -3220,6 +3220,13 @@ class T_S2op_2 <string mnemonic, bits<4> RegTyBits, RegisterClass RCOut,
     let Inst{7-5} = MinOp;
     let Inst{4-0} = dst;
   }
+
+class T_S2op_2_di <string mnemonic, bits<3> MajOp, bits<3> MinOp>
+  : T_S2op_2 <mnemonic, 0b1000, DoubleRegs, IntRegs, MajOp, MinOp, 0, 0>;
+
+let hasNewValue = 1 in
+class T_S2op_2_id <string mnemonic, bits<3> MajOp, bits<3> MinOp>
+  : T_S2op_2 <mnemonic, 0b1000, IntRegs, DoubleRegs, MajOp, MinOp, 0, 0>;
   
 let hasNewValue = 1 in
 class T_S2op_2_ii <string mnemonic, bits<3> MajOp, bits<3> MinOp,

diff --git a/lib/Target/Hexagon/HexagonInstrInfoV4.td b/lib/Target/Hexagon/HexagonInstrInfoV4.td
index 07892edc3eafe9e73de27f878de03ebc1e8a2705..6892b5c9bf892d50272714e650f347e31177c502 100644 (file)
--- a/lib/Target/Hexagon/HexagonInstrInfoV4.td
+++ b/lib/Target/Hexagon/HexagonInstrInfoV4.td
@@ -1747,6 +1747,20 @@ def M4_xor_xacc
     let Inst{12-8}  = Rtt;
     let Inst{4-0}   = Rxx;
   }
+  
+// Split bitfield
+let isCodeGenOnly = 0 in
+def A4_bitspliti : T_S2op_2_di <"bitsplit", 0b110, 0b100>;
+
+// Arithmetic/Convergent round
+let isCodeGenOnly = 0 in
+def A4_cround_ri : T_S2op_2_ii <"cround", 0b111, 0b000>;
+
+let isCodeGenOnly = 0 in
+def A4_round_ri  : T_S2op_2_ii <"round", 0b111, 0b100>;
+
+let Defs = [USR_OVF], isCodeGenOnly = 0 in
+def A4_round_ri_sat : T_S2op_2_ii <"round", 0b111, 0b110, 1>;
 
 //  Add and accumulate.
 //  Rd=add(Rs,add(Ru,#s6))

diff --git a/test/MC/Disassembler/Hexagon/xtype_alu.txt b/test/MC/Disassembler/Hexagon/xtype_alu.txt
index ec9944bd9263be82dd604ed9d98e6eaad91fcf9e..d614e9ca83b72a5e8bf004e9c132c49e0e2675da 100644 (file)
--- a/test/MC/Disassembler/Hexagon/xtype_alu.txt
+++ b/test/MC/Disassembler/Hexagon/xtype_alu.txt
@@ -86,6 +86,12 @@
 # CHECK: r17:16 = neg(r21:20)
 0xd1 0xc0 0x95 0x8c
 # CHECK: r17 = neg(r21):sat
+0x11 0xdf 0xf5 0x8c
+# CHECK: r17 = cround(r21, #31)
+0x91 0xdf 0xf5 0x8c
+# CHECK: r17 = round(r21, #31)
+0xd1 0xdf 0xf5 0x8c
+# CHECK: r17 = round(r21, #31):sat
 0x71 0xd5 0x1f 0xef
 # CHECK: r17 += sub(r21, r31)
 0x11 0xd5 0x3f 0xd5

diff --git a/test/MC/Disassembler/Hexagon/xtype_bit.txt b/test/MC/Disassembler/Hexagon/xtype_bit.txt
index 601b3e199632f81f2dda1c44628e17345e001c7e..ac670c02bb0b586c9d3a7fb0aa9db1044bb51414 100644 (file)
--- a/test/MC/Disassembler/Hexagon/xtype_bit.txt
+++ b/test/MC/Disassembler/Hexagon/xtype_bit.txt
@@ -64,6 +64,8 @@
 # CHECK: r17 = clrbit(r21, r31)
 0x91 0xdf 0x95 0xc6
 # CHECK: r17 = togglebit(r21, r31)
+0x90 0xdf 0xd5 0x88
+# CHECK: r17:16 = bitsplit(r21, #31)
 0xf1 0xcd 0x15 0x87
 # CHECK: r17 = tableidxb(r21, #7, #13):raw
 0xf1 0xcd 0x55 0x87