inline Interval::succ_iterator succ_end(Interval *I) {
return I->Successors.end();
}
-
+
/// pred_begin/pred_end - define methods so that Intervals may be used
/// just like BasicBlocks can with the pred_* functions, and *::pred_iterator.
///
static NodeType *getEntryNode(Interval *I) { return I; }
/// nodes_iterator/begin/end - Allow iteration over all nodes in the graph
- static inline ChildIteratorType child_begin(NodeType *N) {
+ static inline ChildIteratorType child_begin(NodeType *N) {
return succ_begin(N);
}
static inline ChildIteratorType child_end(NodeType *N) {
/// splitBasicBlock - This splits a basic block into two at the specified
/// instruction. Note that all instructions BEFORE the specified iterator
/// stay as part of the original basic block, an unconditional branch is added
- /// to the original BB, and the rest of the instructions in the BB are moved
+ /// to the original BB, and the rest of the instructions in the BB are moved
/// to the new BB, including the old terminator. The newly formed BasicBlock
/// is returned. This function invalidates the specified iterator.
///
public:
MachineRelocation(unsigned Offset, unsigned RelocationType, GlobalValue *GV,
- intptr_t cst = 0, bool DoesntNeedFunctionStub = 0,
+ intptr_t cst = 0, bool DoesntNeedFunctionStub = 0,
bool GOTrelative = 0)
: OffsetTypeExternal(Offset + (RelocationType << 26)), ConstantVal(cst),
GOTRelative(GOTrelative), isConstPool(0) {
}
/// getGOTIndex - Once this has been resolved to an entry in the GOT,
- /// this returns that index. The index is from the lowest address entry
+ /// this returns that index. The index is from the lowest address entry
/// in the GOT.
unsigned getGOTIndex() const {
return Target.GOTIndex;
assert(ResNo < Values.size() && "Illegal result number!");
return Values[ResNo];
}
-
+
typedef std::vector<MVT::ValueType>::const_iterator value_iterator;
value_iterator value_begin() const { return Values.begin(); }
value_iterator value_end() const { return Values.end(); }
/// setAdjCallChain - This method should only be used by the legalizer.
void setAdjCallChain(SDOperand N);
-
+
protected:
friend class SelectionDAG;
/* If using the C implementation of alloca, define if you know the
direction of stack growth for your system; otherwise it will be
automatically deduced at run-time.
- STACK_DIRECTION > 0 => grows toward higher addresses
- STACK_DIRECTION < 0 => grows toward lower addresses
- STACK_DIRECTION = 0 => direction of growth unknown */
+ STACK_DIRECTION > 0 => grows toward higher addresses
+ STACK_DIRECTION < 0 => grows toward lower addresses
+ STACK_DIRECTION = 0 => direction of growth unknown */
#undef STACK_DIRECTION
/* Define to 1 if the `S_IS*' macros in <sys/stat.h> do not work properly. */
//===----------------------------------------------------------------------===//
//
// Annotable - This class is used as a base class for all objects that would
-// like to have annotation capability.
+// like to have annotation capability.
//
// Annotable objects keep their annotation list sorted as annotations are
// inserted and deleted. This is used to ensure that annotations with identical
virtual bool handleOccurrence(unsigned pos, const char *ArgName,
const std::string &Arg) {
- typename ParserClass::parser_data_type Val =
+ typename ParserClass::parser_data_type Val =
typename ParserClass::parser_data_type();
if (Parser.parse(*this, ArgName, Arg, Val))
return true; // Parse error!
//===-- include/Support/DataTypes.h - Define fixed size types ---*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file contains definitions to figure out the size of _HOST_ data types.
//===-- Support/MutexGuard.h - Acquire/Release Mutex In Scope ---*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file defines a guard for a block of code that ensures a Mutex is locked
#include <llvm/System/Mutex.h>
namespace llvm {
- /// Instances of this class acquire a given Mutex Lock when constructed and
+ /// Instances of this class acquire a given Mutex Lock when constructed and
/// hold that lock until destruction. The intention is to instantiate one of
/// these on the stack at the top of some scope to be assured that C++
/// destruction of the object will always release the Mutex and thus avoid
/// holds - Returns true if this locker instance holds the specified lock.
/// This is mostly used in assertions to validate that the correct mutex
/// is held.
- bool holds(const sys::Mutex& lock) const { return &M == &lock; }
+ bool holds(const sys::Mutex& lock) const { return &M == &lock; }
};
}
/// Attempts to release the lock. If the lock is held by the current
/// thread, the lock is released allowing other threads to acquire the
- /// lock.
+ /// lock.
/// @returns false if any kind of error occurs, true otherwise.
/// @brief Unconditionally release the lock.
bool release(void);
/// available, true otherwise.
/// @brief Try to acquire the lock.
bool tryacquire();
-
+
//@}
/// @name Platform Dependent Data
/// @{
/// @}
/// @name Do Not Implement
/// @{
- private:
+ private:
Mutex(const Mutex & original);
void operator=(const Mutex &);
/// @}
/// in the operating system's filesystem and provides various basic operations
/// on it. Note that this class only represents the name of a path to a file
/// or directory which may or may not be valid for a given machine's file
- /// system. The class is patterned after the java.io.File class with various
- /// extensions and several omissions (not relevant to LLVM). A Path object
- /// ensures that the path it encapsulates is syntactically valid for the
- /// operating system it is running on but does not ensure correctness for
- /// any particular file system. That is, a syntactically valid path might
+ /// system. The class is patterned after the java.io.File class with various
+ /// extensions and several omissions (not relevant to LLVM). A Path object
+ /// ensures that the path it encapsulates is syntactically valid for the
+ /// operating system it is running on but does not ensure correctness for
+ /// any particular file system. That is, a syntactically valid path might
/// specify path components that do not exist in the file system and using
/// such a Path to act on the file system could produce errors. There is one
- /// invalid Path value which is permitted: the empty path. The class should
- /// never allow a syntactically invalid non-empty path name to be assigned.
+ /// invalid Path value which is permitted: the empty path. The class should
+ /// never allow a syntactically invalid non-empty path name to be assigned.
/// Empty paths are required in order to indicate an error result in some
- /// situations. If the path is empty, the isValid operation will return
- /// false. All operations will fail if isValid is false. Operations that
+ /// situations. If the path is empty, the isValid operation will return
+ /// false. All operations will fail if isValid is false. Operations that
/// change the path will either return false if it would cause a syntactically
- /// invalid path name (in which case the Path object is left unchanged) or
+ /// invalid path name (in which case the Path object is left unchanged) or
/// throw an std::string exception indicating the error. The methods are
/// grouped into four basic categories: Path Accessors (provide information
/// about the path without accessing disk), Disk Accessors (provide
bool isDynamicLibrary() const;
/// This function determines if the path name references an existing file
- /// or directory in the file system.
- /// @returns true if the pathname references an existing file or
+ /// or directory in the file system.
+ /// @returns true if the pathname references an existing file or
/// directory.
/// @brief Determines if the path is a file or directory in
/// the file system.
bool exists() const;
/// This function determines if the path name references a readable file
- /// or directory in the file system. This function checks for
- /// the existence and readability (by the current program) of the file
+ /// or directory in the file system. This function checks for
+ /// the existence and readability (by the current program) of the file
/// or directory.
/// @returns true if the pathname references a readable file.
/// @brief Determines if the path is a readable file or directory
bool canRead() const;
/// This function determines if the path name references a writable file
- /// or directory in the file system. This function checks for the
- /// existence and writability (by the current program) of the file or
+ /// or directory in the file system. This function checks for the
+ /// existence and writability (by the current program) of the file or
/// directory.
/// @returns true if the pathname references a writable file.
/// @brief Determines if the path is a writable file or directory
bool canWrite() const;
/// This function determines if the path name references an executable
- /// file in the file system. This function checks for the existence and
+ /// file in the file system. This function checks for the existence and
/// executability (by the current program) of the file.
/// @returns true if the pathname references an executable file.
/// @brief Determines if the path is an executable file in the file
/// This method sets the Path object to \p unverified_path. This can fail
/// if the \p unverified_path does not pass the syntactic checks of the
- /// isValid() method. If verification fails, the Path object remains
+ /// isValid() method. If verification fails, the Path object remains
/// unchanged and false is returned. Otherwise true is returned and the
/// Path object takes on the path value of \p unverified_path
/// @returns true if the path was set, false otherwise.
/// The \p component is added to the end of the Path if it is a legal
/// name for the operating system. A directory separator will be added if
- /// needed.
+ /// needed.
/// @returns false if the path component could not be added.
/// @brief Appends one path component to the Path.
bool appendComponent( const std::string& component );
/// @brief Make the file readable;
void makeExecutableOnDisk();
- /// This method allows the last modified time stamp and permission bits
+ /// This method allows the last modified time stamp and permission bits
/// to be set on the disk object referenced by the Path.
/// @throws std::string if an error occurs.
/// @returns true
/// same name as the Path object. The \p create_parents parameter controls
/// whether intermediate directories are created or not. if \p
/// create_parents is true, then an attempt will be made to create all
- /// intermediate directories, as needed. If \p create_parents is false,
- /// then only the final directory component of the Path name will be
+ /// intermediate directories, as needed. If \p create_parents is false,
+ /// then only the final directory component of the Path name will be
/// created. The created directory will have no entries.
/// @returns false if the Path does not reference a directory, true
/// otherwise.
/// file is created. Note that this will both change the Path object
/// *and* create the corresponding file. This function will ensure that
/// the newly generated temporary file name is unique in the file system.
- /// @param reuse_current When set to true, this parameter indicates that
+ /// @param reuse_current When set to true, this parameter indicates that
/// if the current file name does not exist then it will be used without
/// modification.
/// @returns true if successful, false if the file couldn't be created.
bool createTemporaryFileOnDisk(bool reuse_current = false);
/// This method renames the file referenced by \p this as \p newName. The
- /// file referenced by \p this must exist. The file referenced by
+ /// file referenced by \p this must exist. The file referenced by
/// \p newName does not need to exist.
/// @returns true
/// @throws std::string if there is an file system error.
/// @brief Rename one file as another.
bool renamePathOnDisk(const Path& newName);
- /// This method attempts to destroy the file or directory named by the
+ /// This method attempts to destroy the file or directory named by the
/// last component of the Path. If the Path refers to a directory and the
- /// \p destroy_contents is false, an attempt will be made to remove just
- /// the directory (the final Path component). If \p destroy_contents is
- /// true, an attempt will be made to remove the entire contents of the
+ /// \p destroy_contents is false, an attempt will be made to remove just
+ /// the directory (the final Path component). If \p destroy_contents is
+ /// true, an attempt will be made to remove the entire contents of the
/// directory, recursively. If the Path refers to a file, the
/// \p destroy_contents parameter is ignored.
/// @param destroy_contents Indicates whether the contents of a destroyed
/// Not all operating systems support this feature. Where it is not
/// supported, the function should return 65536 as the value.
static int GetCurrentUserId();
-
+
/// This static function will return the process' current group id number.
/// Not all operating systems support this feature. Where it is not
/// supported, the function should return 65536 as the value.
/// This function returns true if the target allows unaligned stores. This is
/// used in situations where an array copy/move/set is converted to a sequence
- /// of store operations. It ensures that such replacements don't generate
- /// code that causes an alignment error (trap) on the target machine.
+ /// of store operations. It ensures that such replacements don't generate
+ /// code that causes an alignment error (trap) on the target machine.
/// @brief Determine if the target supports unaligned stores.
bool allowsUnalignedStores() const { return allowUnalignedStores; }
/// should assume that the memset will be done using as many of the largest
/// store operations first, followed by smaller ones, if necessary, per
/// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
- /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
+ /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
/// store. This only applies to setting a constant array of a constant size.
/// @brief Specify maximum number of store instructions per memset call.
unsigned maxStoresPerMemSet;
/// must set this value based on the cost threshold for that target. Targets
/// should assume that the memmove will be done using as many of the largest
/// store operations first, followed by smaller ones, if necessary, per
- /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
- /// with 8-bit alignment would result in nine 1-byte stores. This only
+ /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
+ /// with 8-bit alignment would result in nine 1-byte stores. This only
/// applies to copying a constant array of constant size.
/// @brief Specify maximum bytes of store instructions per memmove call.
unsigned maxStoresPerMemMove;
/// This field specifies whether the target machine permits unaligned stores.
- /// This is used to determine the size of store operations for copying
+ /// This is used to determine the size of store operations for copying
/// small arrays and other similar tasks.
/// @brief Indicate whether the target machine permits unaligned stores.
bool allowUnalignedStores;
virtual const TargetFrameInfo *getFrameInfo() const { return 0; }
const TargetData &getTargetData() const { return DataLayout; }
- /// getSubtarget - This method returns a pointer to the specified type of
+ /// getSubtarget - This method returns a pointer to the specified type of
/// TargetSubtarget. In debug builds, it verifies that the object being
/// returned is of the correct type.
template<typename STC> STC *getSubtarget() const {
#ifndef LTDL_H
#define LTDL_H 1
-#include <sys/types.h> /* for size_t declaration */
+#include <sys/types.h> /* for size_t declaration */
\f
/* --- MACROS FOR PORTABILITY --- */
/* Saves on those hard to debug '\0' typos.... */
-#define LT_EOS_CHAR '\0'
+#define LT_EOS_CHAR '\0'
/* LTDL_BEGIN_C_DECLS should be used at the beginning of your declarations,
so that C++ compilers don't mangle their names. Use LTDL_END_C_DECLS at
the end of C declarations. */
#ifdef __cplusplus
-# define LT_BEGIN_C_DECLS extern "C" {
-# define LT_END_C_DECLS }
+# define LT_BEGIN_C_DECLS extern "C" {
+# define LT_END_C_DECLS }
#else
-# define LT_BEGIN_C_DECLS /* empty */
-# define LT_END_C_DECLS /* empty */
+# define LT_BEGIN_C_DECLS /* empty */
+# define LT_END_C_DECLS /* empty */
#endif
LT_BEGIN_C_DECLS
that don't understand ANSI C prototypes still work, and ANSI C
compilers can issue warnings about type mismatches. */
#if defined (__STDC__) || defined (_AIX) || (defined (__mips) && defined (_SYSTYPE_SVR4)) || defined(WIN32) || defined(__cplusplus)
-# define LT_PARAMS(protos) protos
-# define lt_ptr void*
+# define LT_PARAMS(protos) protos
+# define lt_ptr void*
#else
-# define LT_PARAMS(protos) ()
-# define lt_ptr char*
+# define LT_PARAMS(protos) ()
+# define lt_ptr char*
#endif
/* LT_STMT_START/END are used to create macros which expand to a
/* LT_CONC creates a new concatenated symbol for the compiler
in a portable way. */
#if defined(__STDC__) || defined(__cplusplus) || defined(_MSC_VER)
-# define LT_CONC(s,t) s##t
+# define LT_CONC(s,t) s##t
#else
-# define LT_CONC(s,t) s/**/t
+# define LT_CONC(s,t) s/**/t
#endif
/* LT_STRLEN can be used safely on NULL pointers. */
-#define LT_STRLEN(s) (((s) && (s)[0]) ? strlen (s) : 0)
+#define LT_STRLEN(s) (((s) && (s)[0]) ? strlen (s) : 0)
\f
# ifndef __CYGWIN__
/* LT_DIRSEP_CHAR is accepted *in addition* to '/' as a directory
separator when it is set. */
-# define LT_DIRSEP_CHAR '\\'
-# define LT_PATHSEP_CHAR ';'
+# define LT_DIRSEP_CHAR '\\'
+# define LT_PATHSEP_CHAR ';'
# endif
#endif
#ifndef LT_PATHSEP_CHAR
-# define LT_PATHSEP_CHAR ':'
+# define LT_PATHSEP_CHAR ':'
#endif
/* DLL building support on win32 hosts; mostly to workaround their
ridiculous implementation of data symbol exporting. */
#ifndef LT_SCOPE
# ifdef __WINDOWS__
-# ifdef DLL_EXPORT /* defined by libtool (if required) */
-# define LT_SCOPE __declspec(dllexport)
+# ifdef DLL_EXPORT /* defined by libtool (if required) */
+# define LT_SCOPE __declspec(dllexport)
# endif
-# ifdef LIBLTDL_DLL_IMPORT /* define if linking with this dll */
-# define LT_SCOPE extern __declspec(dllimport)
+# ifdef LIBLTDL_DLL_IMPORT /* define if linking with this dll */
+# define LT_SCOPE extern __declspec(dllimport)
# endif
# endif
-# ifndef LT_SCOPE /* static linking or !__WINDOWS__ */
-# define LT_SCOPE extern
+# ifndef LT_SCOPE /* static linking or !__WINDOWS__ */
+# define LT_SCOPE extern
# endif
#endif
/* --- DYNAMIC MODULE LOADING API --- */
-typedef struct lt_dlhandle_struct *lt_dlhandle; /* A loaded module. */
+typedef struct lt_dlhandle_struct *lt_dlhandle; /* A loaded module. */
/* Initialisation and finalisation functions for libltdl. */
-LT_SCOPE int lt_dlinit LT_PARAMS((void));
-LT_SCOPE int lt_dlexit LT_PARAMS((void));
+LT_SCOPE int lt_dlinit LT_PARAMS((void));
+LT_SCOPE int lt_dlexit LT_PARAMS((void));
/* Module search path manipulation. */
-LT_SCOPE int lt_dladdsearchdir LT_PARAMS((const char *search_dir));
-LT_SCOPE int lt_dlinsertsearchdir LT_PARAMS((const char *before,
- const char *search_dir));
-LT_SCOPE int lt_dlsetsearchpath LT_PARAMS((const char *search_path));
-LT_SCOPE const char *lt_dlgetsearchpath LT_PARAMS((void));
-LT_SCOPE int lt_dlforeachfile LT_PARAMS((
- const char *search_path,
- int (*func) (const char *filename, lt_ptr data),
- lt_ptr data));
+LT_SCOPE int lt_dladdsearchdir LT_PARAMS((const char *search_dir));
+LT_SCOPE int lt_dlinsertsearchdir LT_PARAMS((const char *before,
+ const char *search_dir));
+LT_SCOPE int lt_dlsetsearchpath LT_PARAMS((const char *search_path));
+LT_SCOPE const char *lt_dlgetsearchpath LT_PARAMS((void));
+LT_SCOPE int lt_dlforeachfile LT_PARAMS((
+ const char *search_path,
+ int (*func) (const char *filename, lt_ptr data),
+ lt_ptr data));
/* Portable libltdl versions of the system dlopen() API. */
-LT_SCOPE lt_dlhandle lt_dlopen LT_PARAMS((const char *filename));
-LT_SCOPE lt_dlhandle lt_dlopenext LT_PARAMS((const char *filename));
-LT_SCOPE lt_ptr lt_dlsym LT_PARAMS((lt_dlhandle handle,
- const char *name));
-LT_SCOPE const char *lt_dlerror LT_PARAMS((void));
-LT_SCOPE int lt_dlclose LT_PARAMS((lt_dlhandle handle));
+LT_SCOPE lt_dlhandle lt_dlopen LT_PARAMS((const char *filename));
+LT_SCOPE lt_dlhandle lt_dlopenext LT_PARAMS((const char *filename));
+LT_SCOPE lt_ptr lt_dlsym LT_PARAMS((lt_dlhandle handle,
+ const char *name));
+LT_SCOPE const char *lt_dlerror LT_PARAMS((void));
+LT_SCOPE int lt_dlclose LT_PARAMS((lt_dlhandle handle));
/* Module residency management. */
-LT_SCOPE int lt_dlmakeresident LT_PARAMS((lt_dlhandle handle));
-LT_SCOPE int lt_dlisresident LT_PARAMS((lt_dlhandle handle));
+LT_SCOPE int lt_dlmakeresident LT_PARAMS((lt_dlhandle handle));
+LT_SCOPE int lt_dlisresident LT_PARAMS((lt_dlhandle handle));
/* --- MUTEX LOCKING --- */
-typedef void lt_dlmutex_lock LT_PARAMS((void));
-typedef void lt_dlmutex_unlock LT_PARAMS((void));
-typedef void lt_dlmutex_seterror LT_PARAMS((const char *errmsg));
-typedef const char *lt_dlmutex_geterror LT_PARAMS((void));
+typedef void lt_dlmutex_lock LT_PARAMS((void));
+typedef void lt_dlmutex_unlock LT_PARAMS((void));
+typedef void lt_dlmutex_seterror LT_PARAMS((const char *errmsg));
+typedef const char *lt_dlmutex_geterror LT_PARAMS((void));
-LT_SCOPE int lt_dlmutex_register LT_PARAMS((lt_dlmutex_lock *lock,
- lt_dlmutex_unlock *unlock,
- lt_dlmutex_seterror *seterror,
- lt_dlmutex_geterror *geterror));
+LT_SCOPE int lt_dlmutex_register LT_PARAMS((lt_dlmutex_lock *lock,
+ lt_dlmutex_unlock *unlock,
+ lt_dlmutex_seterror *seterror,
+ lt_dlmutex_geterror *geterror));
libltdl relies on a featureful realloc, but if you are sure yours
has the right semantics then you can assign it directly. Generally,
it is safe to assign just a malloc() and a free() function. */
-LT_SCOPE lt_ptr (*lt_dlmalloc) LT_PARAMS((size_t size));
-LT_SCOPE lt_ptr (*lt_dlrealloc) LT_PARAMS((lt_ptr ptr, size_t size));
-LT_SCOPE void (*lt_dlfree) LT_PARAMS((lt_ptr ptr));
+LT_SCOPE lt_ptr (*lt_dlmalloc) LT_PARAMS((size_t size));
+LT_SCOPE lt_ptr (*lt_dlrealloc) LT_PARAMS((lt_ptr ptr, size_t size));
+LT_SCOPE void (*lt_dlfree) LT_PARAMS((lt_ptr ptr));
lt_ptr address;
} lt_dlsymlist;
-LT_SCOPE int lt_dlpreload LT_PARAMS((const lt_dlsymlist *preloaded));
-LT_SCOPE int lt_dlpreload_default
- LT_PARAMS((const lt_dlsymlist *preloaded));
+LT_SCOPE int lt_dlpreload LT_PARAMS((const lt_dlsymlist *preloaded));
+LT_SCOPE int lt_dlpreload_default
+ LT_PARAMS((const lt_dlsymlist *preloaded));
-#define LTDL_SET_PRELOADED_SYMBOLS() LT_STMT_START{ \
- extern const lt_dlsymlist lt_preloaded_symbols[]; \
- lt_dlpreload_default(lt_preloaded_symbols); \
- }LT_STMT_END
+#define LTDL_SET_PRELOADED_SYMBOLS() LT_STMT_START{ \
+ extern const lt_dlsymlist lt_preloaded_symbols[]; \
+ lt_dlpreload_default(lt_preloaded_symbols); \
+ }LT_STMT_END
/* Read only information pertaining to a loaded module. */
-typedef struct {
- char *filename; /* file name */
- char *name; /* module name */
- int ref_count; /* number of times lt_dlopened minus
- number of times lt_dlclosed. */
+typedef struct {
+ char *filename; /* file name */
+ char *name; /* module name */
+ int ref_count; /* number of times lt_dlopened minus
+ number of times lt_dlclosed. */
} lt_dlinfo;
-LT_SCOPE const lt_dlinfo *lt_dlgetinfo LT_PARAMS((lt_dlhandle handle));
-LT_SCOPE lt_dlhandle lt_dlhandle_next LT_PARAMS((lt_dlhandle place));
-LT_SCOPE int lt_dlforeach LT_PARAMS((
- int (*func) (lt_dlhandle handle, lt_ptr data),
- lt_ptr data));
+LT_SCOPE const lt_dlinfo *lt_dlgetinfo LT_PARAMS((lt_dlhandle handle));
+LT_SCOPE lt_dlhandle lt_dlhandle_next LT_PARAMS((lt_dlhandle place));
+LT_SCOPE int lt_dlforeach LT_PARAMS((
+ int (*func) (lt_dlhandle handle, lt_ptr data),
+ lt_ptr data));
/* Associating user data with loaded modules. */
typedef unsigned lt_dlcaller_id;
-LT_SCOPE lt_dlcaller_id lt_dlcaller_register LT_PARAMS((void));
-LT_SCOPE lt_ptr lt_dlcaller_set_data LT_PARAMS((lt_dlcaller_id key,
- lt_dlhandle handle,
- lt_ptr data));
-LT_SCOPE lt_ptr lt_dlcaller_get_data LT_PARAMS((lt_dlcaller_id key,
- lt_dlhandle handle));
+LT_SCOPE lt_dlcaller_id lt_dlcaller_register LT_PARAMS((void));
+LT_SCOPE lt_ptr lt_dlcaller_set_data LT_PARAMS((lt_dlcaller_id key,
+ lt_dlhandle handle,
+ lt_ptr data));
+LT_SCOPE lt_ptr lt_dlcaller_get_data LT_PARAMS((lt_dlcaller_id key,
+ lt_dlhandle handle));
\f
/* --- USER MODULE LOADER API --- */
-typedef struct lt_dlloader lt_dlloader;
-typedef lt_ptr lt_user_data;
-typedef lt_ptr lt_module;
+typedef struct lt_dlloader lt_dlloader;
+typedef lt_ptr lt_user_data;
+typedef lt_ptr lt_module;
/* Function pointer types for creating user defined module loaders. */
-typedef lt_module lt_module_open LT_PARAMS((lt_user_data loader_data,
- const char *filename));
-typedef int lt_module_close LT_PARAMS((lt_user_data loader_data,
- lt_module handle));
-typedef lt_ptr lt_find_sym LT_PARAMS((lt_user_data loader_data,
- lt_module handle,
- const char *symbol));
-typedef int lt_dlloader_exit LT_PARAMS((lt_user_data loader_data));
+typedef lt_module lt_module_open LT_PARAMS((lt_user_data loader_data,
+ const char *filename));
+typedef int lt_module_close LT_PARAMS((lt_user_data loader_data,
+ lt_module handle));
+typedef lt_ptr lt_find_sym LT_PARAMS((lt_user_data loader_data,
+ lt_module handle,
+ const char *symbol));
+typedef int lt_dlloader_exit LT_PARAMS((lt_user_data loader_data));
struct lt_user_dlloader {
- const char *sym_prefix;
+ const char *sym_prefix;
lt_module_open *module_open;
lt_module_close *module_close;
- lt_find_sym *find_sym;
+ lt_find_sym *find_sym;
lt_dlloader_exit *dlloader_exit;
- lt_user_data dlloader_data;
+ lt_user_data dlloader_data;
};
-LT_SCOPE lt_dlloader *lt_dlloader_next LT_PARAMS((lt_dlloader *place));
-LT_SCOPE lt_dlloader *lt_dlloader_find LT_PARAMS((
- const char *loader_name));
-LT_SCOPE const char *lt_dlloader_name LT_PARAMS((lt_dlloader *place));
-LT_SCOPE lt_user_data *lt_dlloader_data LT_PARAMS((lt_dlloader *place));
-LT_SCOPE int lt_dlloader_add LT_PARAMS((lt_dlloader *place,
- const struct lt_user_dlloader *dlloader,
- const char *loader_name));
-LT_SCOPE int lt_dlloader_remove LT_PARAMS((
- const char *loader_name));
+LT_SCOPE lt_dlloader *lt_dlloader_next LT_PARAMS((lt_dlloader *place));
+LT_SCOPE lt_dlloader *lt_dlloader_find LT_PARAMS((
+ const char *loader_name));
+LT_SCOPE const char *lt_dlloader_name LT_PARAMS((lt_dlloader *place));
+LT_SCOPE lt_user_data *lt_dlloader_data LT_PARAMS((lt_dlloader *place));
+LT_SCOPE int lt_dlloader_add LT_PARAMS((lt_dlloader *place,
+ const struct lt_user_dlloader *dlloader,
+ const char *loader_name));
+LT_SCOPE int lt_dlloader_remove LT_PARAMS((
+ const char *loader_name));
\f
this way allows us to expand the macro in different contexts with
confidence that the enumeration of symbolic names will map correctly
onto the table of error strings. */
-#define lt_dlerror_table \
- LT_ERROR(UNKNOWN, "unknown error") \
- LT_ERROR(DLOPEN_NOT_SUPPORTED, "dlopen support not available") \
- LT_ERROR(INVALID_LOADER, "invalid loader") \
- LT_ERROR(INIT_LOADER, "loader initialization failed") \
- LT_ERROR(REMOVE_LOADER, "loader removal failed") \
- LT_ERROR(FILE_NOT_FOUND, "file not found") \
- LT_ERROR(DEPLIB_NOT_FOUND, "dependency library not found") \
- LT_ERROR(NO_SYMBOLS, "no symbols defined") \
- LT_ERROR(CANNOT_OPEN, "can't open the module") \
- LT_ERROR(CANNOT_CLOSE, "can't close the module") \
- LT_ERROR(SYMBOL_NOT_FOUND, "symbol not found") \
- LT_ERROR(NO_MEMORY, "not enough memory") \
- LT_ERROR(INVALID_HANDLE, "invalid module handle") \
- LT_ERROR(BUFFER_OVERFLOW, "internal buffer overflow") \
- LT_ERROR(INVALID_ERRORCODE, "invalid errorcode") \
- LT_ERROR(SHUTDOWN, "library already shutdown") \
- LT_ERROR(CLOSE_RESIDENT_MODULE, "can't close resident module") \
+#define lt_dlerror_table \
+ LT_ERROR(UNKNOWN, "unknown error") \
+ LT_ERROR(DLOPEN_NOT_SUPPORTED, "dlopen support not available") \
+ LT_ERROR(INVALID_LOADER, "invalid loader") \
+ LT_ERROR(INIT_LOADER, "loader initialization failed") \
+ LT_ERROR(REMOVE_LOADER, "loader removal failed") \
+ LT_ERROR(FILE_NOT_FOUND, "file not found") \
+ LT_ERROR(DEPLIB_NOT_FOUND, "dependency library not found") \
+ LT_ERROR(NO_SYMBOLS, "no symbols defined") \
+ LT_ERROR(CANNOT_OPEN, "can't open the module") \
+ LT_ERROR(CANNOT_CLOSE, "can't close the module") \
+ LT_ERROR(SYMBOL_NOT_FOUND, "symbol not found") \
+ LT_ERROR(NO_MEMORY, "not enough memory") \
+ LT_ERROR(INVALID_HANDLE, "invalid module handle") \
+ LT_ERROR(BUFFER_OVERFLOW, "internal buffer overflow") \
+ LT_ERROR(INVALID_ERRORCODE, "invalid errorcode") \
+ LT_ERROR(SHUTDOWN, "library already shutdown") \
+ LT_ERROR(CLOSE_RESIDENT_MODULE, "can't close resident module") \
LT_ERROR(INVALID_MUTEX_ARGS, "invalid mutex handler registration") \
- LT_ERROR(INVALID_POSITION, "invalid search path insert position")
+ LT_ERROR(INVALID_POSITION, "invalid search path insert position")
/* Enumerate the symbolic error names. */
enum {
-#define LT_ERROR(name, diagnostic) LT_CONC(LT_ERROR_, name),
- lt_dlerror_table
+#define LT_ERROR(name, diagnostic) LT_CONC(LT_ERROR_, name),
+ lt_dlerror_table
#undef LT_ERROR
- LT_ERROR_MAX
+ LT_ERROR_MAX
};
/* These functions are only useful from inside custom module loaders. */
-LT_SCOPE int lt_dladderror LT_PARAMS((const char *diagnostic));
-LT_SCOPE int lt_dlseterror LT_PARAMS((int errorcode));
+LT_SCOPE int lt_dladderror LT_PARAMS((const char *diagnostic));
+LT_SCOPE int lt_dlseterror LT_PARAMS((int errorcode));
#ifdef LT_NON_POSIX_NAMESPACE
-# define lt_ptr_t lt_ptr
-# define lt_module_t lt_module
-# define lt_module_open_t lt_module_open
-# define lt_module_close_t lt_module_close
-# define lt_find_sym_t lt_find_sym
-# define lt_dlloader_exit_t lt_dlloader_exit
-# define lt_dlloader_t lt_dlloader
-# define lt_dlloader_data_t lt_user_data
+# define lt_ptr_t lt_ptr
+# define lt_module_t lt_module
+# define lt_module_open_t lt_module_open
+# define lt_module_close_t lt_module_close
+# define lt_find_sym_t lt_find_sym
+# define lt_dlloader_exit_t lt_dlloader_exit
+# define lt_dlloader_t lt_dlloader
+# define lt_dlloader_data_t lt_user_data
#endif
LT_END_C_DECLS
#include "llvm/CodeGen/MachineRelocation.h"
-// Hack to rid us of a PPC pre-processor symbol which is erroneously
+// Hack to rid us of a PPC pre-processor symbol which is erroneously
// defined in a PowerPC header file (bug in Linux/PPC)
#ifdef PPC
#undef PPC
};
static void writePrologue (std::ostream &Out, const std::string &comment,
- const std::string &symName) {
+ const std::string &symName) {
// Prologue:
// Output a comment describing the object.
Out << "!" << comment << "\n";
Out << ".end_" << symName << ":\n";
// Output size directive giving the size of the object:
Out << "\t.size " << symName << ", .end_" << symName << "-" << symName
- << "\n";
+ << "\n";
}
// SparcV9BytecodeWriter - Write bytecode out to a stream that is sparc'ified
private:
friend class InstrSchedule;
- inline void addInstr(const SchedGraphNode* node, unsigned int slotNum) {
+ inline void addInstr(const SchedGraphNode* node, unsigned int slotNum) {
assert(slotNum < group.size());
group[slotNum] = node;
}
- /*ctor*/ InstrGroup(unsigned int nslots)
+ /*ctor*/ InstrGroup(unsigned int nslots)
: group(nslots, NULL) {}
- /*ctor*/ InstrGroup(); // disable: DO NOT IMPLEMENT
+ /*ctor*/ InstrGroup(); // disable: DO NOT IMPLEMENT
private:
std::vector<const SchedGraphNode*> group;
typedef ScheduleIterator<_NodeType> _Self;
/*ctor*/ inline ScheduleIterator(const InstrSchedule& _schedule,
- unsigned _cycleNum,
- unsigned _slotNum)
+ unsigned _cycleNum,
+ unsigned _slotNum)
: cycleNum(_cycleNum), slotNum(_slotNum), S(_schedule) {
skipToNextInstr();
}
inline _NodeType* operator*() const;
inline _NodeType* operator->() const { return operator*(); }
- _Self& operator++(); // Preincrement
- inline _Self operator++(int) { // Postincrement
+ _Self& operator++(); // Preincrement
+ inline _Self operator++(int) { // Postincrement
_Self tmp(*this); ++*this; return tmp;
}
private:
inline _Self& operator=(const _Self& x); // DISABLE -- DO NOT IMPLEMENT
- void skipToNextInstr();
+ void skipToNextInstr();
};
class InstrSchedule {
const unsigned int nslots;
unsigned int numInstr;
- std::vector<InstrGroup*> groups; // indexed by cycle number
- std::vector<CycleCount_t> startTime; // indexed by node id
+ std::vector<InstrGroup*> groups; // indexed by cycle number
+ std::vector<CycleCount_t> startTime; // indexed by node id
InstrSchedule(InstrSchedule&); // DO NOT IMPLEMENT
void operator=(InstrSchedule&); // DO NOT IMPLEMENT
const_iterator end() const { return const_iterator::end(*this); }
public: // constructors and destructor
- /*ctor*/ InstrSchedule (unsigned int _nslots,
- unsigned int _numNodes);
- /*dtor*/ ~InstrSchedule ();
+ /*ctor*/ InstrSchedule (unsigned int _nslots,
+ unsigned int _numNodes);
+ /*dtor*/ ~InstrSchedule ();
public: // accessor functions to query chosen schedule
- const SchedGraphNode* getInstr (unsigned int slotNum,
- CycleCount_t c) {
+ const SchedGraphNode* getInstr (unsigned int slotNum,
+ CycleCount_t c) {
const InstrGroup* igroup = this->getIGroup(c);
return (igroup == NULL)? NULL : (*igroup)[slotNum];
}
- inline InstrGroup* getIGroup (CycleCount_t c) {
+ inline InstrGroup* getIGroup (CycleCount_t c) {
if ((unsigned)c >= groups.size())
groups.resize(c+1);
if (groups[c] == NULL)
return groups[c];
}
- inline const InstrGroup* getIGroup (CycleCount_t c) const {
+ inline const InstrGroup* getIGroup (CycleCount_t c) const {
assert((unsigned)c < groups.size());
return groups[c];
}
- inline CycleCount_t getStartTime (unsigned int nodeId) const {
+ inline CycleCount_t getStartTime (unsigned int nodeId) const {
assert(nodeId < startTime.size());
return startTime[nodeId];
}
- unsigned int getNumInstructions() const {
+ unsigned int getNumInstructions() const {
return numInstr;
}
- inline void scheduleInstr (const SchedGraphNode* node,
- unsigned int slotNum,
- CycleCount_t cycle) {
+ inline void scheduleInstr (const SchedGraphNode* node,
+ unsigned int slotNum,
+ CycleCount_t cycle) {
InstrGroup* igroup = this->getIGroup(cycle);
if (!((*igroup)[slotNum] == NULL)) {
std::cerr << "Slot already filled?\n";
private:
friend class ScheduleIterator<SchedGraphNode>;
friend class ScheduleIterator<const SchedGraphNode>;
- /*ctor*/ InstrSchedule (); // Disable: DO NOT IMPLEMENT.
+ /*ctor*/ InstrSchedule (); // Disable: DO NOT IMPLEMENT.
};
template<class NodeType>
InstrSchedule::InstrSchedule(unsigned int _nslots, unsigned int _numNodes)
: nslots(_nslots),
numInstr(0),
- groups(2 * _numNodes / _nslots), // 2 x lower-bound for #cycles
- startTime(_numNodes, (CycleCount_t) -1) // set all to -1
+ groups(2 * _numNodes / _nslots), // 2 x lower-bound for #cycles
+ startTime(_numNodes, (CycleCount_t) -1) // set all to -1
{
}
{
for (unsigned c=0, NC=groups.size(); c < NC; c++)
if (groups[c] != NULL)
- delete groups[c]; // delete InstrGroup objects
+ delete groups[c]; // delete InstrGroup objects
}
ScheduleIterator<_NodeType>::skipToNextInstr()
{
while(cycleNum < S.groups.size() && S.groups[cycleNum] == NULL)
- ++cycleNum; // skip cycles with no instructions
+ ++cycleNum; // skip cycles with no instructions
while (cycleNum < S.groups.size() &&
- (*S.groups[cycleNum])[slotNum] == NULL)
+ (*S.groups[cycleNum])[slotNum] == NULL)
{
++slotNum;
if (slotNum == S.nslots) {
++cycleNum;
slotNum = 0;
while(cycleNum < S.groups.size() && S.groups[cycleNum] == NULL)
- ++cycleNum; // skip cycles with no instructions
+ ++cycleNum; // skip cycles with no instructions
}
}
}
template<class _NodeType>
inline
ScheduleIterator<_NodeType>&
-ScheduleIterator<_NodeType>::operator++() // Preincrement
+ScheduleIterator<_NodeType>::operator++() // Preincrement
{
++slotNum;
if (slotNum == S.nslots) {
DelaySlotInfo(const DelaySlotInfo &); // DO NOT IMPLEMENT
void operator=(const DelaySlotInfo&); // DO NOT IMPLEMENT
public:
- /*ctor*/ DelaySlotInfo (const SchedGraphNode* _brNode,
- unsigned _ndelays)
+ /*ctor*/ DelaySlotInfo (const SchedGraphNode* _brNode,
+ unsigned _ndelays)
: brNode(_brNode), ndelays(_ndelays),
delayedNodeCycle(0), delayedNodeSlotNum(0) {}
- inline unsigned getNumDelays () {
+ inline unsigned getNumDelays () {
return ndelays;
}
return delayNodeVec;
}
- inline void addDelayNode (const SchedGraphNode* node) {
+ inline void addDelayNode (const SchedGraphNode* node) {
delayNodeVec.push_back(node);
assert(delayNodeVec.size() <= ndelays && "Too many delay slot instrs!");
}
- inline void recordChosenSlot (CycleCount_t cycle, unsigned slotNum) {
+ inline void recordChosenSlot (CycleCount_t cycle, unsigned slotNum) {
delayedNodeCycle = cycle;
delayedNodeSlotNum = slotNum;
}
- unsigned scheduleDelayedNode (SchedulingManager& S);
+ unsigned scheduleDelayedNode (SchedulingManager& S);
};
private:
unsigned totalInstrCount;
CycleCount_t curTime;
- CycleCount_t nextEarliestIssueTime; // next cycle we can issue
+ CycleCount_t nextEarliestIssueTime; // next cycle we can issue
// indexed by slot#
std::vector<hash_set<const SchedGraphNode*> > choicesForSlot;
- std::vector<const SchedGraphNode*> choiceVec; // indexed by node ptr
- std::vector<int> numInClass; // indexed by sched class
- std::vector<CycleCount_t> nextEarliestStartTime; // indexed by opCode
+ std::vector<const SchedGraphNode*> choiceVec; // indexed by node ptr
+ std::vector<int> numInClass; // indexed by sched class
+ std::vector<CycleCount_t> nextEarliestStartTime; // indexed by opCode
hash_map<const SchedGraphNode*, DelaySlotInfo*> delaySlotInfoForBranches;
- // indexed by branch node ptr
+ // indexed by branch node ptr
public:
SchedulingManager(const TargetMachine& _target, const SchedGraph* graph,
// Simplify access to the machine instruction info
//----------------------------------------------------------------------
- inline const TargetInstrInfo& getInstrInfo () const {
+ inline const TargetInstrInfo& getInstrInfo () const {
return schedInfo.getInstrInfo();
}
// Interface for checking and updating the current time
//----------------------------------------------------------------------
- inline CycleCount_t getTime () const {
+ inline CycleCount_t getTime () const {
return curTime;
}
- inline CycleCount_t getEarliestIssueTime() const {
+ inline CycleCount_t getEarliestIssueTime() const {
return nextEarliestIssueTime;
}
- inline CycleCount_t getEarliestStartTimeForOp(MachineOpCode opCode) const {
+ inline CycleCount_t getEarliestStartTimeForOp(MachineOpCode opCode) const {
assert(opCode < (int) nextEarliestStartTime.size());
return nextEarliestStartTime[opCode];
}
// Update current time to specified cycle
- inline void updateTime (CycleCount_t c) {
+ inline void updateTime (CycleCount_t c) {
curTime = c;
schedPrio.updateTime(c);
}
// between choices for a single cycle
//----------------------------------------------------------------------
- inline unsigned int getNumChoices () const {
+ inline unsigned int getNumChoices () const {
return choiceVec.size();
}
- inline unsigned getNumChoicesInClass (const InstrSchedClass& sc) const {
+ inline unsigned getNumChoicesInClass (const InstrSchedClass& sc) const {
assert(sc < numInClass.size() && "Invalid op code or sched class!");
return numInClass[sc];
}
inline const SchedGraphNode* getChoice(unsigned int i) const {
- // assert(i < choiceVec.size()); don't check here.
+ // assert(i < choiceVec.size()); don't check here.
return choiceVec[i];
}
return choicesForSlot[slotNum];
}
- inline void addChoice (const SchedGraphNode* node) {
+ inline void addChoice (const SchedGraphNode* node) {
// Append the instruction to the vector of choices for current cycle.
// Increment numInClass[c] for the sched class to which the instr belongs.
choiceVec.push_back(node);
numInClass[sc]++;
}
- inline void addChoiceToSlot (unsigned int slotNum,
- const SchedGraphNode* node) {
+ inline void addChoiceToSlot (unsigned int slotNum,
+ const SchedGraphNode* node) {
// Add the instruction to the choice set for the specified slot
assert(slotNum < nslots);
choicesForSlot[slotNum].insert(node);
}
- inline void resetChoices () {
+ inline void resetChoices () {
choiceVec.clear();
for (unsigned int s=0; s < nslots; s++)
choicesForSlot[s].clear();
// Code to query and manage the partial instruction schedule so far
//----------------------------------------------------------------------
- inline unsigned int getNumScheduled () const {
+ inline unsigned int getNumScheduled () const {
return isched.getNumInstructions();
}
- inline unsigned int getNumUnscheduled() const {
+ inline unsigned int getNumUnscheduled() const {
return totalInstrCount - isched.getNumInstructions();
}
- inline bool isScheduled (const SchedGraphNode* node) const {
+ inline bool isScheduled (const SchedGraphNode* node) const {
return (isched.getStartTime(node->getNodeId()) >= 0);
}
- inline void scheduleInstr (const SchedGraphNode* node,
- unsigned int slotNum,
- CycleCount_t cycle)
+ inline void scheduleInstr (const SchedGraphNode* node,
+ unsigned int slotNum,
+ CycleCount_t cycle)
{
assert(! isScheduled(node) && "Instruction already scheduled?");
//----------------------------------------------------------------------
inline DelaySlotInfo* getDelaySlotInfoForInstr(const SchedGraphNode* bn,
- bool createIfMissing=false)
+ bool createIfMissing=false)
{
hash_map<const SchedGraphNode*, DelaySlotInfo*>::const_iterator
I = delaySlotInfoForBranches.find(bn);
/*ctor*/
SchedulingManager::SchedulingManager(const TargetMachine& target,
- const SchedGraph* graph,
- SchedPriorities& _schedPrio)
+ const SchedGraph* graph,
+ SchedPriorities& _schedPrio)
: nslots(target.getSchedInfo()->getMaxNumIssueTotal()),
schedInfo(*target.getSchedInfo()),
schedPrio(_schedPrio),
totalInstrCount(graph->getNumNodes() - 2),
nextEarliestIssueTime(0),
choicesForSlot(nslots),
- numInClass(target.getSchedInfo()->getNumSchedClasses(), 0), // set all to 0
+ numInClass(target.getSchedInfo()->getNumSchedClasses(), 0), // set all to 0
nextEarliestStartTime(target.getInstrInfo()->getNumOpcodes(),
- (CycleCount_t) 0) // set all to 0
+ (CycleCount_t) 0) // set all to 0
{
updateTime(0);
void
SchedulingManager::updateEarliestStartTimes(const SchedGraphNode* node,
- CycleCount_t schedTime)
+ CycleCount_t schedTime)
{
if (schedInfo.numBubblesAfter(node->getOpcode()) > 0)
{ // Update next earliest time before which *nothing* can issue.
nextEarliestIssueTime = std::max(nextEarliestIssueTime,
- curTime + 1 + schedInfo.numBubblesAfter(node->getOpcode()));
+ curTime + 1 + schedInfo.numBubblesAfter(node->getOpcode()));
}
const std::vector<MachineOpCode>&
if (!(I->getOpcode() == V9::NOP || I->getOpcode() == V9::PHI))
++numInstr;
assert(S.isched.getNumInstructions() >= numInstr &&
- "Lost some non-NOP instructions during scheduling!");
+ "Lost some non-NOP instructions during scheduling!");
if (S.isched.getNumInstructions() == 0)
- return; // empty basic block!
+ return; // empty basic block!
// First find the dummy instructions at the start of the basic block
MachineBasicBlock::iterator I = MBB.begin();
//
for (sg_succ_const_iterator SI = succ_begin(node); SI !=succ_end(node); ++SI)
if (! (*SI)->isDummyNode()
- && ! S.isScheduled(*SI)
- && ! S.schedPrio.nodeIsReady(*SI))
+ && ! S.isScheduled(*SI)
+ && ! S.schedPrio.nodeIsReady(*SI))
{
// successor not scheduled and not marked ready; check *its* preds.
-
+
bool succIsReady = true;
for (sg_pred_const_iterator P=pred_begin(*SI); P != pred_end(*SI); ++P)
if (! (*P)->isDummyNode() && ! S.isScheduled(*P)) {
succIsReady = false;
break;
}
-
- if (succIsReady) // add the successor to the ready list
+
+ if (succIsReady) // add the successor to the ready list
S.schedPrio.insertReady(*SI);
}
}
// of chosen instructions can be issued in a single group.
//
// Return value:
-// maxIssue : total number of feasible instructions
-// S.choicesForSlot[i=0..nslots] : set of instructions feasible in slot i
+// maxIssue : total number of feasible instructions
+// S.choicesForSlot[i=0..nslots] : set of instructions feasible in slot i
//
static unsigned
FindSlotChoices(SchedulingManager& S,
- DelaySlotInfo*& getDelaySlotInfo)
+ DelaySlotInfo*& getDelaySlotInfo)
{
// initialize result vectors to empty
S.resetChoices();
while (S.getNumChoices() < S.nslots - startSlot) {
const SchedGraphNode* nextNode=S.schedPrio.getNextHighest(S,S.getTime());
if (nextNode == NULL)
- break; // no more instructions for this cycle
+ break; // no more instructions for this cycle
if (S.getInstrInfo().getNumDelaySlots(nextNode->getOpcode()) > 0) {
delaySlotInfo = S.getDelaySlotInfoForInstr(nextNode);
}
if (indexForDelayedInstr < S.nslots)
- break; // leave the rest for delay slots
+ break; // leave the rest for delay slots
}
assert(S.getNumChoices() <= S.nslots);
assert(! (indexForDelayedInstr < S.nslots &&
- indexForBreakingNode < S.nslots) && "Cannot have both in a cycle");
+ indexForBreakingNode < S.nslots) && "Cannot have both in a cycle");
// Assign each chosen instruction to all possible slots for that instr.
// But if only one instruction was chosen, put it only in the first
S.addChoiceToSlot(s, S.getChoice(i));
noSlotFound = false;
}
-
+
// No slot before `delayedNodeSlot' was found for this opCode
// Use a later slot, and allow some delay slots to fall in
// the next cycle.
S.addChoiceToSlot(s, S.getChoice(i));
break;
}
-
+
assert(s < S.nslots && "No feasible slot for instruction?");
-
+
highestSlotUsed = std::max(highestSlotUsed, (int) s);
}
const SchedGraphNode* breakingNode=S.getChoice(indexForBreakingNode);
unsigned breakingSlot = INT_MAX;
unsigned int nslotsToUse = S.nslots;
-
+
// Find the last possible slot for this instruction.
for (int s = S.nslots-1; s >= (int) startSlot; s--)
if (S.schedInfo.instrCanUseSlot(breakingNode->getOpcode(), s)) {
i < S.getNumChoices() && i < indexForBreakingNode; i++)
{
MachineOpCode opCode =S.getChoice(i)->getOpcode();
-
+
// If a higher priority instruction cannot be assigned to
// any earlier slots, don't schedule the breaking instruction.
//
bool foundLowerSlot = false;
- nslotsToUse = S.nslots; // May be modified in the loop
+ nslotsToUse = S.nslots; // May be modified in the loop
for (unsigned int s=startSlot; s < nslotsToUse; s++)
if (S.schedInfo.instrCanUseSlot(opCode, s)) {
if (breakingSlot < S.nslots && s < breakingSlot) {
foundLowerSlot = true;
nslotsToUse = breakingSlot; // RESETS LOOP UPPER BOUND!
}
-
+
S.addChoiceToSlot(s, S.getChoice(i));
}
-
+
if (!foundLowerSlot)
- breakingSlot = INT_MAX; // disable breaking instr
+ breakingSlot = INT_MAX; // disable breaking instr
}
// Assign the breaking instruction (if any) to a single slot
nslotsToUse = breakingSlot;
} else
nslotsToUse = S.nslots;
-
+
// For lower priority instructions than the one that breaks the
// group, only assign them to slots lower than the breaking slot.
// Otherwise, just ignore the instruction.
ChooseOneGroup(SchedulingManager& S)
{
assert(S.schedPrio.getNumReady() > 0
- && "Don't get here without ready instructions.");
+ && "Don't get here without ready instructions.");
CycleCount_t firstCycle = S.getTime();
DelaySlotInfo* getDelaySlotInfo = NULL;
static bool
NodeCanFillDelaySlot(const SchedulingManager& S,
- const SchedGraphNode* node,
- const SchedGraphNode* brNode,
- bool nodeIsPredecessor)
+ const SchedGraphNode* node,
+ const SchedGraphNode* brNode,
+ bool nodeIsPredecessor)
{
assert(! node->isDummyNode());
for (SchedGraphNode::const_iterator EI = node->beginInEdges();
EI != node->endInEdges(); ++EI)
if (! ((SchedGraphNode*)(*EI)->getSrc())->isDummyNode()
- && mii.isLoad(((SchedGraphNode*)(*EI)->getSrc())->getOpcode())
- && (*EI)->getDepType() == SchedGraphEdge::CtrlDep)
+ && mii.isLoad(((SchedGraphNode*)(*EI)->getSrc())->getOpcode())
+ && (*EI)->getDepType() == SchedGraphEdge::CtrlDep)
return false;
// Finally, if the instruction precedes the branch, we make sure the
static void
MarkNodeForDelaySlot(SchedulingManager& S,
- SchedGraph* graph,
- SchedGraphNode* node,
- const SchedGraphNode* brNode,
- bool nodeIsPredecessor)
+ SchedGraph* graph,
+ SchedGraphNode* node,
+ const SchedGraphNode* brNode,
+ bool nodeIsPredecessor)
{
if (nodeIsPredecessor) {
// If node is in the same basic block (i.e., precedes brNode),
for (sg_pred_iterator P = pred_begin(brNode);
P != pred_end(brNode) && sdelayNodeVec.size() < ndelays; ++P)
if (! (*P)->isDummyNode() &&
- ! mii.isNop((*P)->getOpcode()) &&
- NodeCanFillDelaySlot(S, *P, brNode, /*pred*/ true))
+ ! mii.isNop((*P)->getOpcode()) &&
+ NodeCanFillDelaySlot(S, *P, brNode, /*pred*/ true))
{
if (mii.maxLatency((*P)->getOpcode()) > 1)
mdelayNodeVec.push_back(*P);
sdelayNodeVec.push_back(graph->getGraphNodeForInstr(MBBI));
else {
nopNodeVec.push_back(graph->getGraphNodeForInstr(MBBI));
-
+
//remove the MI from the Machine Code For Instruction
const TerminatorInst *TI = MBB.getBasicBlock()->getTerminator();
MachineCodeForInstruction& llvmMvec =
//
static void
ChooseInstructionsForDelaySlots(SchedulingManager& S, MachineBasicBlock &MBB,
- SchedGraph *graph)
+ SchedGraph *graph)
{
const TargetInstrInfo& mii = S.getInstrInfo();
{
assert(delayedNodeSlotNum < S.nslots && "Illegal slot for branch");
assert(S.isched.getInstr(delayedNodeSlotNum, delayedNodeCycle) == NULL
- && "Slot for branch should be empty");
+ && "Slot for branch should be empty");
unsigned int nextSlot = delayedNodeSlotNum;
CycleCount_t nextTime = delayedNodeCycle;
nextTime++;
}
} while (S.isched.getInstr(nextSlot, nextTime) != NULL);
-
+
S.scheduleInstr(delayNodeVec[i], nextSlot, nextTime);
break;
}
//
static inline bool
ConflictsWithChoices(const SchedulingManager& S,
- MachineOpCode opCode)
+ MachineOpCode opCode)
{
// Check if the instruction must issue by itself, and some feasible
// choices have already been made for this cycle
static inline bool
ViolatesMinimumGap(const SchedulingManager& S,
- MachineOpCode opCode,
- const CycleCount_t inCycle)
+ MachineOpCode opCode,
+ const CycleCount_t inCycle)
{
return (inCycle < S.getEarliestStartTimeForOp(opCode));
}
bool
instrIsFeasible(const SchedulingManager& S,
- MachineOpCode opCode)
+ MachineOpCode opCode)
{
// skip the instruction if it cannot be issued due to issue restrictions
// caused by previously issued instructions
bool InstructionSchedulingWithSSA::runOnFunction(Function &F)
{
- SchedGraphSet graphSet(&F, target);
+ SchedGraphSet graphSet(&F, target);
if (SchedDebugLevel >= Sched_PrintSchedGraphs) {
std::cerr << "\n*** SCHEDULING GRAPHS FOR INSTRUCTION SCHEDULING\n";
// Method: SchedGraphNode Destructor
//
// Description:
-// Free memory allocated by the SchedGraphNode object.
+// Free memory allocated by the SchedGraphNode object.
//
// Notes:
-// Do not delete the edges here. The base class will take care of that.
-// Only handle subclass specific stuff here (where currently there is
-// none).
+// Do not delete the edges here. The base class will take care of that.
+// Only handle subclass specific stuff here (where currently there is
+// none).
//
SchedGraphNode::~SchedGraphNode() {
}
// Method: SchedGraph Destructor
//
// Description:
-// This method deletes memory allocated by the SchedGraph object.
+// This method deletes memory allocated by the SchedGraph object.
//
// Notes:
-// Do not delete the graphRoot or graphLeaf here. The base class handles
-// that bit of work.
+// Do not delete the graphRoot or graphLeaf here. The base class handles
+// that bit of work.
//
SchedGraph::~SchedGraph() {
for (const_iterator I = begin(); I != end(); ++I)
void SchedGraph::addCDEdges(const TerminatorInst* term,
- const TargetMachine& target) {
+ const TargetMachine& target) {
const TargetInstrInfo& mii = *target.getInstrInfo();
MachineCodeForInstruction &termMvec = MachineCodeForInstruction::get(term);
! mii.isReturn(termMvec[first]->getOpcode()))
++first;
assert(first < termMvec.size() &&
- "No branch instructions for terminator? Ok, but weird!");
+ "No branch instructions for terminator? Ok, but weird!");
if (first == termMvec.size())
return;
assert(brNode && "No node for instr generated for branch/ret?");
(void) new SchedGraphEdge(brNode, toNode, SchedGraphEdge::CtrlDep,
SchedGraphEdge::NonDataDep, 0);
- break; // only one incoming edge is enough
+ break; // only one incoming edge is enough
}
}
SchedGraphNode* fromNode = getGraphNodeForInstr(I);
if (fromNode == NULL)
- continue; // dummy instruction, e.g., PHI
+ continue; // dummy instruction, e.g., PHI
(void) new SchedGraphEdge(fromNode, firstBrNode,
SchedGraphEdge::CtrlDep,
// latency does not otherwise matter (true dependences enforce that).
//
void SchedGraph::addMemEdges(const std::vector<SchedGraphNode*>& memNodeVec,
- const TargetMachine& target) {
+ const TargetMachine& target) {
const TargetInstrInfo& mii = *target.getInstrInfo();
// Instructions in memNodeVec are in execution order within the basic block,
// like with control dependences.
//
void SchedGraph::addCallDepEdges(const std::vector<SchedGraphNode*>& callDepNodeVec,
- const TargetMachine& target) {
+ const TargetMachine& target) {
const TargetInstrInfo& mii = *target.getInstrInfo();
// Instructions in memNodeVec are in execution order within the basic block,
if (mii.isCall(callDepNodeVec[ic]->getOpcode())) {
// Add SG_CALL_REF edges from all preds to this instruction.
for (unsigned jc=0; jc < ic; jc++)
- (void) new SchedGraphEdge(callDepNodeVec[jc], callDepNodeVec[ic],
- SchedGraphEdge::MachineRegister,
- MachineIntRegsRID, 0);
+ (void) new SchedGraphEdge(callDepNodeVec[jc], callDepNodeVec[ic],
+ SchedGraphEdge::MachineRegister,
+ MachineIntRegsRID, 0);
// And do the same from this instruction to all successors.
for (unsigned jc=ic+1; jc < NC; jc++)
- (void) new SchedGraphEdge(callDepNodeVec[ic], callDepNodeVec[jc],
- SchedGraphEdge::MachineRegister,
- MachineIntRegsRID, 0);
+ (void) new SchedGraphEdge(callDepNodeVec[ic], callDepNodeVec[jc],
+ SchedGraphEdge::MachineRegister,
+ MachineIntRegsRID, 0);
}
#ifdef CALL_DEP_NODE_VEC_CANNOT_WORK
void SchedGraph::addMachineRegEdges(RegToRefVecMap& regToRefVecMap,
- const TargetMachine& target) {
+ const TargetMachine& target) {
// This code assumes that two registers with different numbers are
// not aliased!
//
new SchedGraphEdge(prevNode, node, regNum,
SchedGraphEdge::AntiDep);
}
-
+
if (prevIsDef)
if (!isDef || isDefAndUse)
new SchedGraphEdge(prevNode, node, regNum,
// We do not consider other uses because we are not building use-use deps.
//
void SchedGraph::addEdgesForValue(SchedGraphNode* refNode,
- const RefVec& defVec,
- const Value* defValue,
- bool refNodeIsDef,
- bool refNodeIsUse,
- const TargetMachine& target) {
+ const RefVec& defVec,
+ const Value* defValue,
+ bool refNodeIsDef,
+ bool refNodeIsUse,
+ const TargetMachine& target) {
// Add true or output dep edges from all def nodes before refNode in BB.
// Add anti or output dep edges to all def nodes after refNode.
for (RefVec::const_iterator I=defVec.begin(), E=defVec.end(); I != E; ++I) {
void SchedGraph::addEdgesForInstruction(const MachineInstr& MI,
- const ValueToDefVecMap& valueToDefVecMap,
- const TargetMachine& target) {
+ const ValueToDefVecMap& valueToDefVecMap,
+ const TargetMachine& target) {
SchedGraphNode* node = getGraphNodeForInstr(&MI);
if (node == NULL)
return;
case MachineOperand::MO_UnextendedImmed:
case MachineOperand::MO_PCRelativeDisp:
case MachineOperand::MO_ConstantPoolIndex:
- break; // nothing to do for immediate fields
+ break; // nothing to do for immediate fields
default:
assert(0 && "Unknown machine operand type in SchedGraph builder");
void SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target,
- SchedGraphNode* node,
- std::vector<SchedGraphNode*>& memNodeVec,
- std::vector<SchedGraphNode*>& callDepNodeVec,
- RegToRefVecMap& regToRefVecMap,
- ValueToDefVecMap& valueToDefVecMap) {
+ SchedGraphNode* node,
+ std::vector<SchedGraphNode*>& memNodeVec,
+ std::vector<SchedGraphNode*>& callDepNodeVec,
+ RegToRefVecMap& regToRefVecMap,
+ ValueToDefVecMap& valueToDefVecMap) {
const TargetInstrInfo& mii = *target.getInstrInfo();
MachineOpCode opCode = node->getOpcode();
void SchedGraph::buildNodesForBB(const TargetMachine& target,
- MachineBasicBlock& MBB,
- std::vector<SchedGraphNode*>& memNodeVec,
- std::vector<SchedGraphNode*>& callDepNodeVec,
- RegToRefVecMap& regToRefVecMap,
- ValueToDefVecMap& valueToDefVecMap) {
+ MachineBasicBlock& MBB,
+ std::vector<SchedGraphNode*>& memNodeVec,
+ std::vector<SchedGraphNode*>& callDepNodeVec,
+ RegToRefVecMap& regToRefVecMap,
+ ValueToDefVecMap& valueToDefVecMap) {
const TargetInstrInfo& mii = *target.getInstrInfo();
// Build graph nodes for each VM instruction and gather def/use info.
this->addMachineRegEdges(regToRefVecMap, target);
// Finally, add edges from the dummy root and to dummy leaf
- this->addDummyEdges();
+ this->addDummyEdges();
}
// class SchedGraphSet
//
SchedGraphSet::SchedGraphSet(const Function* _function,
- const TargetMachine& target) :
+ const TargetMachine& target) :
function(_function) {
buildGraphsForMethod(function, target);
}
void SchedGraphSet::buildGraphsForMethod(const Function *F,
- const TargetMachine& target) {
+ const TargetMachine& target) {
MachineFunction &MF = MachineFunction::get(F);
for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
addGraph(new SchedGraph(*I, target));
<< sink->getNodeId() << "] : ";
switch(depType) {
- case SchedGraphEdge::CtrlDep:
+ case SchedGraphEdge::CtrlDep:
os<< "Control Dep";
break;
case SchedGraphEdge::ValueDep:
os<< "Reg Value " << *val;
break;
- case SchedGraphEdge::MemoryDep:
+ case SchedGraphEdge::MemoryDep:
os<< "Memory Dep";
break;
case SchedGraphEdge::MachineRegister:
SchedGraphNode(unsigned nodeId, MachineBasicBlock *mbb, int indexInBB,
- const TargetMachine& Target);
+ const TargetMachine& Target);
~SchedGraphNode();
- friend class SchedGraph; // give access for ctor and dtor
- friend class SchedGraphEdge; // give access for adding edges
+ friend class SchedGraph; // give access for ctor and dtor
+ friend class SchedGraphEdge; // give access for adding edges
public:
}
private:
- friend class SchedGraphSet; // give access to ctor
+ friend class SchedGraphSet; // give access to ctor
- inline void noteGraphNodeForInstr (const MachineInstr* minstr,
- SchedGraphNode* node) {
+ inline void noteGraphNodeForInstr (const MachineInstr* minstr,
+ SchedGraphNode* node) {
assert((*this)[minstr] == NULL);
(*this)[minstr] = node;
}
void buildGraph(const TargetMachine& target);
void buildNodesForBB(const TargetMachine& target,MachineBasicBlock &MBB,
- std::vector<SchedGraphNode*>& memNV,
- std::vector<SchedGraphNode*>& callNV,
- RegToRefVecMap& regToRefVecMap,
- ValueToDefVecMap& valueToDefVecMap);
+ std::vector<SchedGraphNode*>& memNV,
+ std::vector<SchedGraphNode*>& callNV,
+ RegToRefVecMap& regToRefVecMap,
+ ValueToDefVecMap& valueToDefVecMap);
void findDefUseInfoAtInstr(const TargetMachine& target, SchedGraphNode* node,
- std::vector<SchedGraphNode*>& memNV,
- std::vector<SchedGraphNode*>& callNV,
- RegToRefVecMap& regToRefVecMap,
- ValueToDefVecMap& valueToDefVecMap);
+ std::vector<SchedGraphNode*>& memNV,
+ std::vector<SchedGraphNode*>& callNV,
+ RegToRefVecMap& regToRefVecMap,
+ ValueToDefVecMap& valueToDefVecMap);
void addEdgesForInstruction(const MachineInstr& minstr,
- const ValueToDefVecMap& valueToDefVecMap,
- const TargetMachine& target);
+ const ValueToDefVecMap& valueToDefVecMap,
+ const TargetMachine& target);
void addCDEdges(const TerminatorInst* term, const TargetMachine& target);
void addMemEdges(const std::vector<SchedGraphNode*>& memNod,
- const TargetMachine& target);
+ const TargetMachine& target);
void addCallCCEdges(const std::vector<SchedGraphNode*>& memNod,
- MachineBasicBlock& bbMvec,
- const TargetMachine& target);
+ MachineBasicBlock& bbMvec,
+ const TargetMachine& target);
void addCallDepEdges(const std::vector<SchedGraphNode*>& callNV,
- const TargetMachine& target);
+ const TargetMachine& target);
void addMachineRegEdges(RegToRefVecMap& regToRefVecMap,
- const TargetMachine& target);
+ const TargetMachine& target);
void addEdgesForValue(SchedGraphNode* refNode, const RefVec& defVec,
- const Value* defValue, bool refNodeIsDef,
- bool refNodeIsDefAndUse,
- const TargetMachine& target);
+ const Value* defValue, bool refNodeIsDef,
+ bool refNodeIsDefAndUse,
+ const TargetMachine& target);
void addDummyEdges();
// class SchedGraphEdge
//
SchedGraphEdge::SchedGraphEdge(SchedGraphNodeCommon* _src,
- SchedGraphNodeCommon* _sink,
- SchedGraphEdgeDepType _depType,
- unsigned int _depOrderType,
- int _minDelay)
+ SchedGraphNodeCommon* _sink,
+ SchedGraphEdgeDepType _depType,
+ unsigned int _depOrderType,
+ int _minDelay)
: src(_src), sink(_sink), depType(_depType), depOrderType(_depOrderType),
minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()), val(NULL) {
}
SchedGraphEdge::SchedGraphEdge(SchedGraphNodeCommon* _src,
- SchedGraphNodeCommon* _sink,
- const Value* _val,
- unsigned int _depOrderType,
- int _minDelay)
+ SchedGraphNodeCommon* _sink,
+ const Value* _val,
+ unsigned int _depOrderType,
+ int _minDelay)
: src(_src), sink(_sink), depType(ValueDep), depOrderType(_depOrderType),
minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()), val(_val) {
iteDiff=0;
}
SchedGraphEdge::SchedGraphEdge(SchedGraphNodeCommon* _src,
- SchedGraphNodeCommon* _sink,
- unsigned int _regNum,
- unsigned int _depOrderType,
- int _minDelay)
+ SchedGraphNodeCommon* _sink,
+ unsigned int _regNum,
+ unsigned int _depOrderType,
+ int _minDelay)
: src(_src), sink(_sink), depType(MachineRegister),
depOrderType(_depOrderType),
minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()),
}
SchedGraphEdge::SchedGraphEdge(SchedGraphNodeCommon* _src,
- SchedGraphNodeCommon* _sink,
- ResourceId _resourceId,
- int _minDelay)
+ SchedGraphNodeCommon* _sink,
+ ResourceId _resourceId,
+ int _minDelay)
: src(_src), sink(_sink), depType(MachineResource), depOrderType(NonDataDep),
minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()),
resourceId(_resourceId) {
void SchedGraphCommon::eraseIncomingEdges(SchedGraphNodeCommon* node,
- bool addDummyEdges) {
+ bool addDummyEdges) {
// Delete and disconnect all in-edges for the node
for (SchedGraphNodeCommon::iterator I = node->beginInEdges();
I != node->endInEdges(); ++I) {
delete *I;
if (addDummyEdges && srcNode != getRoot() &&
- srcNode->beginOutEdges() == srcNode->endOutEdges()) {
+ srcNode->beginOutEdges() == srcNode->endOutEdges()) {
// srcNode has no more out edges, so add an edge to dummy EXIT node
assert(node != getLeaf() && "Adding edge that was just removed?");
(void) new SchedGraphEdge(srcNode, getLeaf(),
- SchedGraphEdge::CtrlDep,
- SchedGraphEdge::NonDataDep, 0);
+ SchedGraphEdge::CtrlDep,
+ SchedGraphEdge::NonDataDep, 0);
}
}
}
void SchedGraphCommon::eraseOutgoingEdges(SchedGraphNodeCommon* node,
- bool addDummyEdges) {
+ bool addDummyEdges) {
// Delete and disconnect all out-edges for the node
for (SchedGraphNodeCommon::iterator I = node->beginOutEdges();
I != node->endOutEdges(); ++I) {
delete *I;
if (addDummyEdges &&
- sinkNode != getLeaf() &&
- sinkNode->beginInEdges() == sinkNode->endInEdges()) {
+ sinkNode != getLeaf() &&
+ sinkNode->beginInEdges() == sinkNode->endInEdges()) {
//sinkNode has no more in edges, so add an edge from dummy ENTRY node
assert(node != getRoot() && "Adding edge that was just removed?");
(void) new SchedGraphEdge(getRoot(), sinkNode,
- SchedGraphEdge::CtrlDep,
- SchedGraphEdge::NonDataDep, 0);
+ SchedGraphEdge::CtrlDep,
+ SchedGraphEdge::NonDataDep, 0);
}
}
}
void SchedGraphCommon::eraseIncidentEdges(SchedGraphNodeCommon* node,
- bool addDummyEdges) {
- this->eraseIncomingEdges(node, addDummyEdges);
- this->eraseOutgoingEdges(node, addDummyEdges);
+ bool addDummyEdges) {
+ this->eraseIncomingEdges(node, addDummyEdges);
+ this->eraseOutgoingEdges(node, addDummyEdges);
}
} // End llvm namespace
std::ostream &operator<<(std::ostream &os, const NodeDelayPair* nd) {
return os << "Delay for node " << nd->node->getNodeId()
- << " = " << (long)nd->delay << "\n";
+ << " = " << (long)nd->delay << "\n";
}
void
SchedPriorities::issuedReadyNodeAt(CycleCount_t curTime,
- const SchedGraphNode* node) {
+ const SchedGraphNode* node) {
candsAsHeap.removeNode(node);
candsAsSet.erase(node);
mcands.clear(); // ensure reset choices is called before any more choices
inline int
SchedPriorities::chooseByRule1(std::vector<candIndex>& mcands) {
- return (mcands.size() == 1)? 0 // only one choice exists so take it
- : -1; // -1 indicates multiple choices
+ return (mcands.size() == 1)? 0 // only one choice exists so take it
+ : -1; // -1 indicates multiple choices
}
inline int
assert(mcands.size() >= 1 && "Should have at least one candidate here.");
for (unsigned i=0, N = mcands.size(); i < N; i++)
if (instructionHasLastUse(methodLiveVarInfo,
- candsAsHeap.getNode(mcands[i])))
+ candsAsHeap.getNode(mcands[i])))
return i;
return -1;
}
inline int
SchedPriorities::chooseByRule3(std::vector<candIndex>& mcands) {
assert(mcands.size() >= 1 && "Should have at least one candidate here.");
- int maxUses = candsAsHeap.getNode(mcands[0])->getNumOutEdges();
+ int maxUses = candsAsHeap.getNode(mcands[0])->getNumOutEdges();
int indexWithMaxUses = 0;
for (unsigned i=1, N = mcands.size(); i < N; i++) {
int numUses = candsAsHeap.getNode(mcands[i])->getNumOutEdges();
const SchedGraphNode*
SchedPriorities::getNextHighest(const SchedulingManager& S,
- CycleCount_t curTime) {
+ CycleCount_t curTime) {
int nextIdx = -1;
const SchedGraphNode* nextChoice = NULL;
findSetWithMaxDelay(mcands, S);
while (nextIdx < 0 && mcands.size() > 0) {
- nextIdx = chooseByRule1(mcands); // rule 1
+ nextIdx = chooseByRule1(mcands); // rule 1
if (nextIdx == -1)
nextIdx = chooseByRule2(mcands); // rule 2
nextIdx = chooseByRule3(mcands); // rule 3
if (nextIdx == -1)
- nextIdx = 0; // default to first choice by delays
+ nextIdx = 0; // default to first choice by delays
// We have found the next best candidate. Check if it ready in
// the current cycle, and if it is feasible.
void
SchedPriorities::findSetWithMaxDelay(std::vector<candIndex>& mcands,
- const SchedulingManager& S)
+ const SchedulingManager& S)
{
if (mcands.size() == 0 && nextToTry != candsAsHeap.end())
{ // out of choices at current maximum delay;
candIndex next = nextToTry;
CycleCount_t maxDelay = candsAsHeap.getDelay(next);
for (; next != candsAsHeap.end()
- && candsAsHeap.getDelay(next) == maxDelay; ++next)
- mcands.push_back(next);
+ && candsAsHeap.getDelay(next) == maxDelay; ++next)
+ mcands.push_back(next);
nextToTry = next;
bool
SchedPriorities::instructionHasLastUse(FunctionLiveVarInfo &LVI,
- const SchedGraphNode* graphNode) {
+ const SchedGraphNode* graphNode) {
const MachineInstr *MI = graphNode->getMachineInstr();
hash_map<const MachineInstr*, bool>::const_iterator
inline unsigned size() const { return _size; }
- const SchedGraphNode* getNode (const_iterator i) const { return (*i)->node; }
- CycleCount_t getDelay(const_iterator i) const { return (*i)->delay;}
+ const SchedGraphNode* getNode (const_iterator i) const { return (*i)->node; }
+ CycleCount_t getDelay(const_iterator i) const { return (*i)->delay;}
- inline void makeHeap() {
+ inline void makeHeap() {
// make_heap(begin(), end(), NDPLessThan);
}
- inline iterator findNode(const SchedGraphNode* node) {
+ inline iterator findNode(const SchedGraphNode* node) {
for (iterator I=begin(); I != end(); ++I)
if (getNode(I) == node)
- return I;
+ return I;
return end();
}
- inline void removeNode (const SchedGraphNode* node) {
+ inline void removeNode (const SchedGraphNode* node) {
iterator ndpPtr = findNode(node);
if (ndpPtr != end())
{
- delete *ndpPtr;
- erase(ndpPtr);
- --_size;
+ delete *ndpPtr;
+ erase(ndpPtr);
+ --_size;
}
};
- void insert(const SchedGraphNode* node, CycleCount_t delay) {
+ void insert(const SchedGraphNode* node, CycleCount_t delay) {
NodeDelayPair* ndp = new NodeDelayPair(node, delay);
if (_size == 0 || front()->delay < delay)
push_front(ndp);
else
{
- iterator I=begin();
- for ( ; I != end() && getDelay(I) >= delay; ++I)
- ;
- std::list<NodeDelayPair*>::insert(I, ndp);
+ iterator I=begin();
+ for ( ; I != end() && getDelay(I) >= delay; ++I)
+ ;
+ std::list<NodeDelayPair*>::insert(I, ndp);
}
_size++;
}
// This must be called before scheduling begins.
- void initialize ();
+ void initialize ();
- CycleCount_t getTime () const { return curTime; }
- CycleCount_t getEarliestReadyTime () const { return earliestReadyTime; }
- unsigned getNumReady () const { return candsAsHeap.size(); }
- bool nodeIsReady (const SchedGraphNode* node) const {
+ CycleCount_t getTime () const { return curTime; }
+ CycleCount_t getEarliestReadyTime () const { return earliestReadyTime; }
+ unsigned getNumReady () const { return candsAsHeap.size(); }
+ bool nodeIsReady (const SchedGraphNode* node) const {
return (candsAsSet.find(node) != candsAsSet.end());
}
- void issuedReadyNodeAt (CycleCount_t curTime,
- const SchedGraphNode* node);
+ void issuedReadyNodeAt (CycleCount_t curTime,
+ const SchedGraphNode* node);
- void insertReady (const SchedGraphNode* node);
+ void insertReady (const SchedGraphNode* node);
- void updateTime (CycleCount_t /*unused*/);
+ void updateTime (CycleCount_t /*unused*/);
- const SchedGraphNode* getNextHighest (const SchedulingManager& S,
- CycleCount_t curTime);
- // choose next highest priority instr
+ const SchedGraphNode* getNextHighest (const SchedulingManager& S,
+ CycleCount_t curTime);
+ // choose next highest priority instr
private:
typedef NodeHeap::iterator candIndex;
std::vector<CycleCount_t> nodeEarliestUseVec;
std::vector<CycleCount_t> earliestReadyTimeForNode;
CycleCount_t earliestReadyTime;
- NodeHeap candsAsHeap; // candidate nodes, ready to go
+ NodeHeap candsAsHeap; // candidate nodes, ready to go
hash_set<const SchedGraphNode*> candsAsSet; //same entries as candsAsHeap,
- // but as set for fast lookup
+ // but as set for fast lookup
std::vector<candIndex> mcands; // holds pointers into cands
- candIndex nextToTry; // next cand after the last
- // one tried in this cycle
+ candIndex nextToTry; // next cand after the last
+ // one tried in this cycle
- int chooseByRule1 (std::vector<candIndex>& mcands);
- int chooseByRule2 (std::vector<candIndex>& mcands);
- int chooseByRule3 (std::vector<candIndex>& mcands);
+ int chooseByRule1 (std::vector<candIndex>& mcands);
+ int chooseByRule2 (std::vector<candIndex>& mcands);
+ int chooseByRule3 (std::vector<candIndex>& mcands);
- void findSetWithMaxDelay (std::vector<candIndex>& mcands,
- const SchedulingManager& S);
+ void findSetWithMaxDelay (std::vector<candIndex>& mcands,
+ const SchedulingManager& S);
- void computeDelays (const SchedGraph* graph);
+ void computeDelays (const SchedGraph* graph);
- void initializeReadyHeap (const SchedGraph* graph);
+ void initializeReadyHeap (const SchedGraph* graph);
- bool instructionHasLastUse (FunctionLiveVarInfo& LVI,
- const SchedGraphNode* graphNode);
+ bool instructionHasLastUse (FunctionLiveVarInfo& LVI,
+ const SchedGraphNode* graphNode);
// NOTE: The next two return references to the actual vector entries.
// Use the following two if you don't need to modify the value.
- CycleCount_t& getNodeDelayRef (const SchedGraphNode* node) {
+ CycleCount_t& getNodeDelayRef (const SchedGraphNode* node) {
assert(node->getNodeId() < nodeDelayVec.size());
return nodeDelayVec[node->getNodeId()];
}
for (MachineInstr::const_val_op_iterator OpI = MI->begin(), OpE = MI->end();
OpI != OpE; ++OpI)
if (OpI.isDef()) // add to Defs if this operand is a def
- addDef(*OpI);
+ addDef(*OpI);
// do for implicit operands as well
for (unsigned i = 0; i < MI->getNumImplicitRefs(); ++i)
if (MI->getImplicitOp(i).isDef())
- addDef(MI->getImplicitRef(i));
+ addDef(MI->getImplicitRef(i));
// iterate over MI operands to find uses
for (MachineInstr::const_val_op_iterator OpI = MI->begin(), OpE = MI->end();
const Value *Op = *OpI;
if (isa<BasicBlock>(Op))
- continue; // don't process labels
+ continue; // don't process labels
if (OpI.isUse()) { // add to Uses only if this operand is a use
//
// Put Phi operands in UseSet for the incoming edge, not node.
// They must not "hide" later defs, and must be handled specially
// during set propagation over the CFG.
- if (MI->getOpcode() == V9::PHI) { // for a phi node
+ if (MI->getOpcode() == V9::PHI) { // for a phi node
const Value *ArgVal = Op;
- const BasicBlock *PredBB = cast<BasicBlock>(*++OpI); // next ptr is BB
-
- PredToEdgeInSetMap[PredBB].insert(ArgVal);
-
- if (DEBUG_LV >= LV_DEBUG_Verbose)
- std::cerr << " - phi operand " << RAV(ArgVal) << " came from BB "
+ const BasicBlock *PredBB = cast<BasicBlock>(*++OpI); // next ptr is BB
+
+ PredToEdgeInSetMap[PredBB].insert(ArgVal);
+
+ if (DEBUG_LV >= LV_DEBUG_Verbose)
+ std::cerr << " - phi operand " << RAV(ArgVal) << " came from BB "
<< RAV(PredBB) << "\n";
- } // if( IsPhi )
+ } // if( IsPhi )
else {
// It is not a Phi use: add to regular use set and remove later defs.
addUse(Op);
const Value *Op = MI->getImplicitRef(i);
if (Op->getType() == Type::LabelTy) // don't process labels
- continue;
+ continue;
if (MI->getImplicitOp(i).isUse())
- addUse(Op);
+ addUse(Op);
}
} // for all machine instructions
}
-
+
//-----------------------------------------------------------------------------
// To add an operand which is a def
//-----------------------------------------------------------------------------
// if the predec POID is lower than mine
if (PredLVBB->getPOId() <= POID)
- needAnotherIt = true;
+ needAnotherIt = true;
}
} // for
void SparcV9FunctionInfo::CalculateArgSize() {
maxOptionalArgsSize = ComputeMaxOptionalArgsSize(MF.getTarget(),
- MF.getFunction(),
+ MF.getFunction(),
maxOptionalNumArgs);
staticStackSize = maxOptionalArgsSize + 176;
}
int
SparcV9FunctionInfo::computeOffsetforLocalVar(const Value* val,
- unsigned &getPaddedSize,
- unsigned sizeToUse)
+ unsigned &getPaddedSize,
+ unsigned sizeToUse)
{
if (sizeToUse == 0) {
// All integer types smaller than ints promote to 4 byte integers.
bool growUp;
int firstOffset = MF.getTarget().getFrameInfo()->getFirstAutomaticVarOffset(MF,
- growUp);
+ growUp);
int offset = growUp? firstOffset + getAutomaticVarsSize()
: firstOffset - (getAutomaticVarsSize() + sizeToUse);
: firstOffset - (currentTmpValuesSize + size);
int aligned = MF.getTarget().getFrameInfo()->adjustAlignment(offset, growUp,
- align);
+ align);
size += abs(aligned - offset); // include alignment padding in size
incrementTmpAreaSize(size); // update "current" size of tmp area
hash_set<const Constant*> constantsForConstPool;
hash_map<const Value*, int> offsets;
- unsigned staticStackSize;
- unsigned automaticVarsSize;
- unsigned regSpillsSize;
- unsigned maxOptionalArgsSize;
- unsigned maxOptionalNumArgs;
- unsigned currentTmpValuesSize;
- unsigned maxTmpValuesSize;
+ unsigned staticStackSize;
+ unsigned automaticVarsSize;
+ unsigned regSpillsSize;
+ unsigned maxOptionalArgsSize;
+ unsigned maxOptionalNumArgs;
+ unsigned currentTmpValuesSize;
+ unsigned maxTmpValuesSize;
bool compiledAsLeaf;
bool spillsAreaFrozen;
bool automaticVarsAreaFrozen;
void MappingInfo::byteVector::dumpAssembly (std::ostream &Out) {
for (iterator i = begin (), e = end (); i != e; ++i)
- Out << ".byte " << (int)*i << "\n";
+ Out << ".byte " << (int)*i << "\n";
}
static void writePrologue (std::ostream &Out, const std::string &comment,
- const std::string &symName) {
+ const std::string &symName) {
// Prologue:
// Output a comment describing the object.
Out << "!" << comment << "\n";
public:
void outByte (unsigned char b) { bytes.push_back (b); }
MappingInfo (std::string Comment, std::string SymbolPrefix,
- unsigned FunctionNumber) : comment(Comment),
- symbolPrefix(SymbolPrefix), functionNumber(FunctionNumber) {}
+ unsigned FunctionNumber) : comment(Comment),
+ symbolPrefix(SymbolPrefix), functionNumber(FunctionNumber) {}
void dumpAssembly (std::ostream &Out);
unsigned char *getBytes (unsigned &length) {
- length = bytes.size(); return &bytes[0];
+ length = bytes.size(); return &bytes[0];
}
};
Statistic<> NoDeps("depanalyzer-nodeps", "Number of dependences eliminated");
Statistic<> NumDeps("depanalyzer-deps",
- "Number of dependences could not eliminate");
+ "Number of dependences could not eliminate");
Statistic<> AdvDeps("depanalyzer-advdeps",
- "Number of dependences using advanced techniques");
+ "Number of dependences using advanced techniques");
bool DependenceAnalyzer::runOnFunction(Function &F) {
AA = &getAnalysis<AliasAnalysis>();
}
static RegisterAnalysis<DependenceAnalyzer>X("depanalyzer",
- "Dependence Analyzer");
+ "Dependence Analyzer");
// - Get inter and intra dependences between loads and stores
//
// further (Step 4)
// Step 4: do advanced analysis
void DependenceAnalyzer::AnalyzeDeps(Value *val, Value *val2, bool valLoad,
- bool val2Load,
- std::vector<Dependence> &deps,
- BasicBlock *BB,
- bool srcBeforeDest) {
+ bool val2Load,
+ std::vector<Dependence> &deps,
+ BasicBlock *BB,
+ bool srcBeforeDest) {
bool loopInvariant = true;
//If Loop invariant, let AA decide
if(loopInvariant) {
if(AA->alias(val, (unsigned)TD->getTypeSize(val->getType()),
- val2,(unsigned)TD->getTypeSize(val2->getType()))
+ val2,(unsigned)TD->getTypeSize(val2->getType()))
!= AliasAnalysis::NoAlias) {
createDep(deps, valLoad, val2Load, srcBeforeDest);
}
Value *GPop = GP->getOperand(0);
Value *GP2op = GP2->getOperand(0);
int alias = AA->alias(GPop, (unsigned)TD->getTypeSize(GPop->getType()),
- GP2op,(unsigned)TD->getTypeSize(GP2op->getType()));
+ GP2op,(unsigned)TD->getTypeSize(GP2op->getType()));
if(alias == AliasAnalysis::MustAlias) {
// advancedDepAnalysis - Do advanced data dependence tests
void DependenceAnalyzer::advancedDepAnalysis(GetElementPtrInst *gp1,
- GetElementPtrInst *gp2,
- bool valLoad,
- bool val2Load,
- std::vector<Dependence> &deps,
- bool srcBeforeDest) {
+ GetElementPtrInst *gp2,
+ bool valLoad,
+ bool val2Load,
+ std::vector<Dependence> &deps,
+ bool srcBeforeDest) {
//Check if both GEPs are in a simple form: 3 ops, constant 0 as second arg
if(gp1->getNumOperands() != 3 || gp2->getNumOperands() != 3) {
if(Constant *c1 = dyn_cast<Constant>(gp1->getOperand(1)))
if(Constant *c2 = dyn_cast<Constant>(gp2->getOperand(1)))
if(c1->isNullValue() && c2->isNullValue())
- GPok = true;
+ GPok = true;
if(!GPok) {
createDep(deps, valLoad, val2Load, srcBeforeDest);
// Create dependences once its determined these two instructions
// references the same memory
void DependenceAnalyzer::createDep(std::vector<Dependence> &deps,
- bool valLoad, bool val2Load,
- bool srcBeforeDest, int diff) {
+ bool valLoad, bool val2Load,
+ bool srcBeforeDest, int diff) {
//If the source instruction occurs after the destination instruction
//(execution order), then this dependence is across iterations
//Get Dependence Info for a pair of Instructions
DependenceResult DependenceAnalyzer::getDependenceInfo(Instruction *inst1,
- Instruction *inst2,
- bool srcBeforeDest) {
+ Instruction *inst2,
+ bool srcBeforeDest) {
std::vector<Dependence> deps;
DEBUG(std::cerr << "Inst1: " << *inst1 << "\n");
if(StoreInst *stInst = dyn_cast<StoreInst>(inst2))
AnalyzeDeps(ldInst->getOperand(0), stInst->getOperand(1),
- true, false, deps, ldInst->getParent(), srcBeforeDest);
+ true, false, deps, ldInst->getParent(), srcBeforeDest);
}
else if(StoreInst *stInst = dyn_cast<StoreInst>(inst1)) {
if(LoadInst *ldInst = dyn_cast<LoadInst>(inst2))
AnalyzeDeps(stInst->getOperand(1), ldInst->getOperand(0), false, true,
- deps, ldInst->getParent(), srcBeforeDest);
+ deps, ldInst->getParent(), srcBeforeDest);
else if(StoreInst *stInst2 = dyn_cast<StoreInst>(inst2))
AnalyzeDeps(stInst->getOperand(1), stInst2->getOperand(1), false, false,
- deps, stInst->getParent(), srcBeforeDest);
+ deps, stInst->getParent(), srcBeforeDest);
}
else
assert(0 && "Expected a load or a store\n");
#include <vector>
namespace llvm {
-
+
//class to represent a dependence
struct Dependence {
class DependenceAnalyzer : public FunctionPass {
-
+
AliasAnalysis *AA;
TargetData *TD;
ScalarEvolution *SE;
- void advancedDepAnalysis(GetElementPtrInst *gp1, GetElementPtrInst *gp2,
- bool valLoad, bool val2Load,
- std::vector<Dependence> &deps, bool srcBeforeDest);
+ void advancedDepAnalysis(GetElementPtrInst *gp1, GetElementPtrInst *gp2,
+ bool valLoad, bool val2Load,
+ std::vector<Dependence> &deps, bool srcBeforeDest);
+
+ void AnalyzeDeps(Value *val, Value *val2, bool val1Load, bool val2Load,
+ std::vector<Dependence> &deps, BasicBlock *BB,
+ bool srcBeforeDest);
- void AnalyzeDeps(Value *val, Value *val2, bool val1Load, bool val2Load,
- std::vector<Dependence> &deps, BasicBlock *BB,
- bool srcBeforeDest);
-
- void createDep(std::vector<Dependence> &deps, bool valLoad, bool val2Load,
- bool srcBeforeDest, int diff = 0);
+ void createDep(std::vector<Dependence> &deps, bool valLoad, bool val2Load,
+ bool srcBeforeDest, int diff = 0);
public:
DependenceAnalyzer() { AA = 0; TD = 0; SE = 0; }
}
//get dependence info
- DependenceResult getDependenceInfo(Instruction *inst1, Instruction *inst2,
- bool srcBeforeDest);
+ DependenceResult getDependenceInfo(Instruction *inst1, Instruction *inst2,
+ bool srcBeforeDest);
};
if (schedule[cycle].size() < numIssue) {
//Now check if all the resources in their respective cycles are available
if(resourcesFree(node, cycle, II)) {
- //Insert to preserve dependencies
- addToSchedule(cycle,node);
- DEBUG(std::cerr << "Found spot in map, and there is an issue slot\n");
- return false;
+ //Insert to preserve dependencies
+ addToSchedule(cycle,node);
+ DEBUG(std::cerr << "Found spot in map, and there is an issue slot\n");
+ return false;
}
}
}
if(resourceNumPerCycle[cycle].count(resourceNum)) {
int maxRes = CPUResource::getCPUResource(resourceNum)->maxNumUsers;
if(resourceNumPerCycle[cycle][resourceNum] >= maxRes)
- isFree = false;
+ isFree = false;
}
}
//Loop over resources in each cycle and increments their usage count
for(unsigned i=0; i < resources.size(); ++i) {
for(unsigned j=0; j < resources[i].size(); ++j) {
-
- //Get Resource to check its availability
- int resourceNum = resources[i][j];
-
- DEBUG(std::cerr << "Attempting to schedule Resource Num: " << resourceNum << " in cycle: " << currentCycle << "\n");
-
- success = resourceAvailable(resourceNum, currentCycle);
-
- if(!success)
- break;
-
+
+ //Get Resource to check its availability
+ int resourceNum = resources[i][j];
+
+ DEBUG(std::cerr << "Attempting to schedule Resource Num: " << resourceNum << " in cycle: " << currentCycle << "\n");
+
+ success = resourceAvailable(resourceNum, currentCycle);
+
+ if(!success)
+ break;
+
}
if(!success)
- break;
+ break;
//Increase cycle
currentCycle++;
//Loop over resources in each cycle and increments their usage count
for(unsigned i=0; i < resources.size(); ++i) {
for(unsigned j=0; j < resources[i].size(); ++j) {
- int resourceNum = resources[i][j];
- useResource(resourceNum, currentCycle);
+ int resourceNum = resources[i][j];
+ useResource(resourceNum, currentCycle);
}
currentCycle++;
}
int count = 0;
for(int i = index; i <= (schedule.rbegin()->first); i+=II) {
if(schedule.count(i)) {
- for(std::vector<MSchedGraphNode*>::iterator I = schedule[i].begin(),
- E = schedule[i].end(); I != E; ++I) {
- //Check if its a branch
- assert(!(*I)->isBranch() && "Branch should not be schedule!");
-
- tempKernel.push_back(std::make_pair(*I, count));
- maxSN = std::max(maxSN, count);
-
- }
+ for(std::vector<MSchedGraphNode*>::iterator I = schedule[i].begin(),
+ E = schedule[i].end(); I != E; ++I) {
+ //Check if its a branch
+ assert(!(*I)->isBranch() && "Branch should not be schedule!");
+
+ tempKernel.push_back(std::make_pair(*I, count));
+ maxSN = std::max(maxSN, count);
+
+ }
}
++count;
}
for(std::map<const MachineInstr*, unsigned>::iterator N = indVar.begin(), NE = indVar.end(); N != NE; ++N) {
- if(N->second < I->first->getIndex())
- tmpMap[N->second] = (MachineInstr*) N->first;
+ if(N->second < I->first->getIndex())
+ tmpMap[N->second] = (MachineInstr*) N->first;
}
//Add to kernel, and delete from indVar
for(std::map<unsigned, MachineInstr*>::iterator N = tmpMap.begin(), NE = tmpMap.end(); N != NE; ++N) {
- kernel.push_back(std::make_pair(N->second, 0));
- indVar.erase(N->second);
+ kernel.push_back(std::make_pair(N->second, 0));
+ indVar.erase(N->second);
}
}
const MachineOperand &mOp = inst->getOperand(i);
if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef()) {
if(def == mOp.getVRegValue()) {
- if(P->second >= stage)
- return false;
- else
- return true;
+ if(P->second >= stage)
+ return false;
+ else
+ return true;
}
}
}
os << "Kernel:\n";
for(std::vector<std::pair<MachineInstr*, int> >::const_iterator I = kernel.begin(),
- E = kernel.end(); I != E; ++I)
+ E = kernel.end(); I != E; ++I)
os << "Node: " << *(I->first) << " Stage: " << I->second << "\n";
}
std::map<int, std::map<int, int> > resourceNumPerCycle;
//Check if all resources are free
- bool resourcesFree(MSchedGraphNode*, int, int II);
+ bool resourcesFree(MSchedGraphNode*, int, int II);
bool resourceAvailable(int resourceNum, int cycle);
void useResource(int resourceNum, int cycle);
if (schedule[cycle].size() < numIssue) {
//Now check if all the resources in their respective cycles are available
if(resourcesFree(node, cycle, II)) {
- //Insert to preserve dependencies
- addToSchedule(cycle,node);
- DEBUG(std::cerr << "Found spot in map, and there is an issue slot\n");
- return false;
+ //Insert to preserve dependencies
+ addToSchedule(cycle,node);
+ DEBUG(std::cerr << "Found spot in map, and there is an issue slot\n");
+ return false;
}
}
}
if(resourceNumPerCycle[cycle].count(resourceNum)) {
int maxRes = CPUResource::getCPUResource(resourceNum)->maxNumUsers;
if(resourceNumPerCycle[cycle][resourceNum] >= maxRes)
- isFree = false;
+ isFree = false;
}
}
//Loop over resources in each cycle and increments their usage count
for(unsigned i=0; i < resources.size(); ++i) {
for(unsigned j=0; j < resources[i].size(); ++j) {
-
- //Get Resource to check its availability
- int resourceNum = resources[i][j];
-
- DEBUG(std::cerr << "Attempting to schedule Resource Num: " << resourceNum << " in cycle: " << currentCycle << "\n");
-
- success = resourceAvailable(resourceNum, currentCycle);
-
- if(!success)
- break;
-
+
+ //Get Resource to check its availability
+ int resourceNum = resources[i][j];
+
+ DEBUG(std::cerr << "Attempting to schedule Resource Num: " << resourceNum << " in cycle: " << currentCycle << "\n");
+
+ success = resourceAvailable(resourceNum, currentCycle);
+
+ if(!success)
+ break;
+
}
if(!success)
- break;
+ break;
//Increase cycle
currentCycle++;
//Loop over resources in each cycle and increments their usage count
for(unsigned i=0; i < resources.size(); ++i) {
for(unsigned j=0; j < resources[i].size(); ++j) {
- int resourceNum = resources[i][j];
- useResource(resourceNum, currentCycle);
+ int resourceNum = resources[i][j];
+ useResource(resourceNum, currentCycle);
}
currentCycle++;
}
int count = 0;
for(int i = index; i <= (schedule.rbegin()->first); i+=II) {
if(schedule.count(i)) {
- for(std::vector<MSchedGraphSBNode*>::iterator I = schedule[i].begin(),
- E = schedule[i].end(); I != E; ++I) {
- //Check if its a branch
- assert(!(*I)->isBranch() && "Branch should not be schedule!");
-
- tempKernel.push_back(std::make_pair(*I, count));
- maxSN = std::max(maxSN, count);
-
- }
+ for(std::vector<MSchedGraphSBNode*>::iterator I = schedule[i].begin(),
+ E = schedule[i].end(); I != E; ++I) {
+ //Check if its a branch
+ assert(!(*I)->isBranch() && "Branch should not be schedule!");
+
+ tempKernel.push_back(std::make_pair(*I, count));
+ maxSN = std::max(maxSN, count);
+
+ }
}
++count;
}
for(std::map<const MachineInstr*, unsigned>::iterator N = indVar.begin(), NE = indVar.end(); N != NE; ++N) {
- if(N->second < I->first->getIndex())
- tmpMap[N->second] = (MachineInstr*) N->first;
+ if(N->second < I->first->getIndex())
+ tmpMap[N->second] = (MachineInstr*) N->first;
}
//Add to kernel, and delete from indVar
for(std::map<unsigned, MachineInstr*>::iterator N = tmpMap.begin(), NE = tmpMap.end(); N != NE; ++N) {
- kernel.push_back(std::make_pair(N->second, 0));
- indVar.erase(N->second);
+ kernel.push_back(std::make_pair(N->second, 0));
+ indVar.erase(N->second);
}
}
//assert(I->second == 0 && "Predicate node must be from current iteration\n");
std::vector<const MachineInstr*> otherInstrs = I->first->getOtherInstrs();
for(std::vector<const MachineInstr*>::iterator O = otherInstrs.begin(), OE = otherInstrs.end(); O != OE; ++O) {
- kernel.push_back(std::make_pair((MachineInstr*) *O, I->second));
+ kernel.push_back(std::make_pair((MachineInstr*) *O, I->second));
}
}
const MachineOperand &mOp = inst->getOperand(i);
if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef()) {
if(def == mOp.getVRegValue()) {
- if(P->second >= stage)
- return false;
- else
- return true;
+ if(P->second >= stage)
+ return false;
+ else
+ return true;
}
}
}
os << "Kernel:\n";
for(std::vector<std::pair<MachineInstr*, int> >::const_iterator I = kernel.begin(),
- E = kernel.end(); I != E; ++I)
+ E = kernel.end(); I != E; ++I)
os << "Node: " << *(I->first) << " Stage: " << I->second << "\n";
}
std::map<int, std::map<int, int> > resourceNumPerCycle;
//Check if all resources are free
- bool resourcesFree(MSchedGraphSBNode*, int, int II);
+ bool resourcesFree(MSchedGraphSBNode*, int, int II);
bool resourceAvailable(int resourceNum, int cycle);
void useResource(int resourceNum, int cycle);
//MSchedGraphNode constructor
MSchedGraphNode::MSchedGraphNode(const MachineInstr* inst,
- MSchedGraph *graph, unsigned idx,
- unsigned late, bool isBranch)
+ MSchedGraph *graph, unsigned idx,
+ unsigned late, bool isBranch)
: Inst(inst), Parent(graph), index(idx), latency(late),
isBranchInstr(isBranch) {
//Get the iteration difference for the edge from this node to its successor
unsigned MSchedGraphNode::getIteDiff(MSchedGraphNode *succ) {
for(std::vector<MSchedGraphEdge>::iterator I = Successors.begin(),
- E = Successors.end();
+ E = Successors.end();
I != E; ++I) {
if(I->getDest() == succ)
return I->getIteDiff();
//return the edge the corresponds to this in edge
int count = 0;
for(MSchedGraphNode::succ_iterator I = pred->succ_begin(),
- E = pred->succ_end();
+ E = pred->succ_end();
I != E; ++I) {
if(*I == this)
return count;
//Dtermine if pred is a predecessor of this node
bool MSchedGraphNode::isPredecessor(MSchedGraphNode *pred) {
if(std::find( Predecessors.begin(), Predecessors.end(),
- pred) != Predecessors.end())
+ pred) != Predecessors.end())
return true;
else
return false;
//Add a node to the graph
void MSchedGraph::addNode(const MachineInstr *MI,
- MSchedGraphNode *node) {
+ MSchedGraphNode *node) {
//Make sure node does not already exist
assert(GraphMap.find(MI) == GraphMap.end()
- && "New MSchedGraphNode already exists for this instruction");
+ && "New MSchedGraphNode already exists for this instruction");
GraphMap[MI] = node;
}
//is a special case in Modulo Scheduling. We only want to deal with
//the body of the loop.
MSchedGraph::MSchedGraph(const MachineBasicBlock *bb,
- const TargetMachine &targ,
- std::map<const MachineInstr*, unsigned> &ignoreInstrs,
- DependenceAnalyzer &DA,
- std::map<MachineInstr*, Instruction*> &machineTollvm)
+ const TargetMachine &targ,
+ std::map<const MachineInstr*, unsigned> &ignoreInstrs,
+ DependenceAnalyzer &DA,
+ std::map<MachineInstr*, Instruction*> &machineTollvm)
: Target(targ) {
//Make sure BB is not null,
//is a special case in Modulo Scheduling. We only want to deal with
//the body of the loop.
MSchedGraph::MSchedGraph(std::vector<const MachineBasicBlock*> &bbs,
- const TargetMachine &targ,
- std::map<const MachineInstr*, unsigned> &ignoreInstrs,
- DependenceAnalyzer &DA,
- std::map<MachineInstr*, Instruction*> &machineTollvm)
+ const TargetMachine &targ,
+ std::map<const MachineInstr*, unsigned> &ignoreInstrs,
+ DependenceAnalyzer &DA,
+ std::map<MachineInstr*, Instruction*> &machineTollvm)
: BBs(bbs), Target(targ) {
//Make sure there is at least one BB and it is not null,
//Copies the graph and keeps a map from old to new nodes
MSchedGraph::MSchedGraph(const MSchedGraph &G,
- std::map<MSchedGraphNode*, MSchedGraphNode*> &newNodes)
+ std::map<MSchedGraphNode*, MSchedGraphNode*> &newNodes)
: Target(G.Target) {
BBs = G.BBs;
std::map<MSchedGraphNode*, MSchedGraphNode*> oldToNew;
//Copy all nodes
for(MSchedGraph::const_iterator N = G.GraphMap.begin(),
- NE = G.GraphMap.end(); N != NE; ++N) {
+ NE = G.GraphMap.end(); N != NE; ++N) {
MSchedGraphNode *newNode = new MSchedGraphNode(*(N->second));
oldToNew[&*(N->second)] = newNode;
}
//Experimental code to add edges from the branch to all nodes dependent upon it.
void hasPath(MSchedGraphNode *node, std::set<MSchedGraphNode*> &visited,
- std::set<MSchedGraphNode*> &branches, MSchedGraphNode *startNode,
- std::set<std::pair<MSchedGraphNode*,MSchedGraphNode*> > &newEdges ) {
+ std::set<MSchedGraphNode*> &branches, MSchedGraphNode *startNode,
+ std::set<std::pair<MSchedGraphNode*,MSchedGraphNode*> > &newEdges ) {
visited.insert(node);
DEBUG(std::cerr << "Visiting: " << *node << "\n");
//only visit if we have not already
else if(!visited.count(dest)) {
if(edge->getIteDiff() == 0)
- hasPath(dest, visited, branches, startNode, newEdges);}
+ hasPath(dest, visited, branches, startNode, newEdges);}
}
I != E; ++I) {
if(I->second->isBranch())
if(I->second->hasPredecessors())
- branches.insert(I->second);
+ branches.insert(I->second);
}
//See if there is a path first instruction to the branches, if so, add an
unsigned min = GraphMap.size();
if(newEdges.size() == 1) {
((newEdges.begin())->first)->addOutEdge(((newEdges.begin())->second),
- MSchedGraphEdge::BranchDep,
- MSchedGraphEdge::NonDataDep, 1);
+ MSchedGraphEdge::BranchDep,
+ MSchedGraphEdge::NonDataDep, 1);
}
else {
DEBUG(std::cerr << "Branch Edge from: " << *(I->first) << " to " << *(I->second) << "\n");
// if(I->second->getIndex() <= min) {
- start = I->first;
- end = I->second;
- //min = I->second->getIndex();
- //}
- start->addOutEdge(end,
- MSchedGraphEdge::BranchDep,
- MSchedGraphEdge::NonDataDep, 1);
+ start = I->first;
+ end = I->second;
+ //min = I->second->getIndex();
+ //}
+ start->addOutEdge(end,
+ MSchedGraphEdge::BranchDep,
+ MSchedGraphEdge::NonDataDep, 1);
}
}
}
//Add edges between the nodes
void MSchedGraph::buildNodesAndEdges(std::map<const MachineInstr*, unsigned> &ignoreInstrs,
- DependenceAnalyzer &DA,
- std::map<MachineInstr*, Instruction*> &machineTollvm) {
+ DependenceAnalyzer &DA,
+ std::map<MachineInstr*, Instruction*> &machineTollvm) {
//Get Machine target information for calculating latency
unsigned index = 0;
for(std::vector<const MachineBasicBlock*>::iterator B = BBs.begin(),
- BE = BBs.end(); B != BE; ++B) {
+ BE = BBs.end(); B != BE; ++B) {
const MachineBasicBlock *BB = *B;
//Loop over instructions in MBB and add nodes and edges
for (MachineBasicBlock::const_iterator MI = BB->begin(), e = BB->end();
- MI != e; ++MI) {
+ MI != e; ++MI) {
//Ignore indvar instructions
if(ignoreInstrs.count(MI)) {
- ++index;
- continue;
+ ++index;
+ continue;
}
//Get each instruction of machine basic block, get the delay
//Check if subsequent instructions can be issued before
//the result is ready, if so use min delay.
if(MTI->hasResultInterlock(MIopCode))
- delay = MTI->minLatency(MIopCode);
+ delay = MTI->minLatency(MIopCode);
else
#endif
- //Get delay
- delay = MTI->maxLatency(opCode);
+ //Get delay
+ delay = MTI->maxLatency(opCode);
//Create new node for this machine instruction and add to the graph.
//Create only if not a nop
if(MTI->isNop(opCode))
- continue;
+ continue;
//Sparc BE does not use PHI opcode, so assert on this case
assert(opCode != TargetInstrInfo::PHI && "Did not expect PHI opcode");
//We want to flag the branch node to treat it special
if(MTI->isBranch(opCode))
- isBranch = true;
+ isBranch = true;
//Node is created and added to the graph automatically
MSchedGraphNode *node = new MSchedGraphNode(MI, this, index, delay,
- isBranch);
+ isBranch);
DEBUG(std::cerr << "Created Node: " << *node << "\n");
//Check OpCode to keep track of memory operations to add memory
//dependencies later.
if(MTI->isLoad(opCode) || MTI->isStore(opCode))
- memInstructions.push_back(node);
+ memInstructions.push_back(node);
//Loop over all operands, and put them into the register number to
//graph node map for determining dependencies
//If an operands is a use/def, we have an anti dependence to itself
for(unsigned i=0; i < MI->getNumOperands(); ++i) {
- //Get Operand
- const MachineOperand &mOp = MI->getOperand(i);
-
- //Check if it has an allocated register
- if(mOp.hasAllocatedReg()) {
- int regNum = mOp.getReg();
-
- if(regNum != SparcV9::g0) {
- //Put into our map
- regNumtoNodeMap[regNum].push_back(std::make_pair(i, node));
- }
- continue;
- }
-
-
- //Add virtual registers dependencies
- //Check if any exist in the value map already and create dependencies
- //between them.
- if(mOp.getType() == MachineOperand::MO_VirtualRegister
- || mOp.getType() == MachineOperand::MO_CCRegister) {
-
- //Make sure virtual register value is not null
- assert((mOp.getVRegValue() != NULL) && "Null value is defined");
-
- //Check if this is a read operation in a phi node, if so DO NOT PROCESS
- if(mOp.isUse() && (opCode == TargetInstrInfo::PHI)) {
- DEBUG(std::cerr << "Read Operation in a PHI node\n");
- continue;
- }
-
- if (const Value* srcI = mOp.getVRegValue()) {
-
- //Find value in the map
- std::map<const Value*, std::vector<OpIndexNodePair> >::iterator V
- = valuetoNodeMap.find(srcI);
-
- //If there is something in the map already, add edges from
- //those instructions
- //to this one we are processing
- if(V != valuetoNodeMap.end()) {
- addValueEdges(V->second, node, mOp.isUse(), mOp.isDef(), phiInstrs);
-
- //Add to value map
- V->second.push_back(std::make_pair(i,node));
- }
- //Otherwise put it in the map
- else
- //Put into value map
- valuetoNodeMap[mOp.getVRegValue()].push_back(std::make_pair(i, node));
- }
- }
+ //Get Operand
+ const MachineOperand &mOp = MI->getOperand(i);
+
+ //Check if it has an allocated register
+ if(mOp.hasAllocatedReg()) {
+ int regNum = mOp.getReg();
+
+ if(regNum != SparcV9::g0) {
+ //Put into our map
+ regNumtoNodeMap[regNum].push_back(std::make_pair(i, node));
+ }
+ continue;
+ }
+
+
+ //Add virtual registers dependencies
+ //Check if any exist in the value map already and create dependencies
+ //between them.
+ if(mOp.getType() == MachineOperand::MO_VirtualRegister
+ || mOp.getType() == MachineOperand::MO_CCRegister) {
+
+ //Make sure virtual register value is not null
+ assert((mOp.getVRegValue() != NULL) && "Null value is defined");
+
+ //Check if this is a read operation in a phi node, if so DO NOT PROCESS
+ if(mOp.isUse() && (opCode == TargetInstrInfo::PHI)) {
+ DEBUG(std::cerr << "Read Operation in a PHI node\n");
+ continue;
+ }
+
+ if (const Value* srcI = mOp.getVRegValue()) {
+
+ //Find value in the map
+ std::map<const Value*, std::vector<OpIndexNodePair> >::iterator V
+ = valuetoNodeMap.find(srcI);
+
+ //If there is something in the map already, add edges from
+ //those instructions
+ //to this one we are processing
+ if(V != valuetoNodeMap.end()) {
+ addValueEdges(V->second, node, mOp.isUse(), mOp.isDef(), phiInstrs);
+
+ //Add to value map
+ V->second.push_back(std::make_pair(i,node));
+ }
+ //Otherwise put it in the map
+ else
+ //Put into value map
+ valuetoNodeMap[mOp.getVRegValue()].push_back(std::make_pair(i, node));
+ }
+ }
}
++index;
}
//phiInstr list to process
const BasicBlock *llvm_bb = BB->getBasicBlock();
for(BasicBlock::const_iterator I = llvm_bb->begin(), E = llvm_bb->end();
- I != E; ++I) {
+ I != E; ++I) {
if(const PHINode *PN = dyn_cast<PHINode>(I)) {
- MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(PN);
- for (unsigned j = 0; j < tempMvec.size(); j++) {
- if(!ignoreInstrs.count(tempMvec[j])) {
- DEBUG(std::cerr << "Inserting phi instr into map: " << *tempMvec[j] << "\n");
- phiInstrs.push_back((MachineInstr*) tempMvec[j]);
- }
- }
+ MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(PN);
+ for (unsigned j = 0; j < tempMvec.size(); j++) {
+ if(!ignoreInstrs.count(tempMvec[j])) {
+ DEBUG(std::cerr << "Inserting phi instr into map: " << *tempMvec[j] << "\n");
+ phiInstrs.push_back((MachineInstr*) tempMvec[j]);
+ }
+ }
}
}
//Finally deal with PHI Nodes and Value*
for(std::vector<const MachineInstr*>::iterator I = phiInstrs.begin(),
- E = phiInstrs.end(); I != E; ++I) {
+ E = phiInstrs.end(); I != E; ++I) {
//Get Node for this instruction
std::map<const MachineInstr*, MSchedGraphNode*>::iterator X;
X = find(*I);
if(X == GraphMap.end())
- continue;
+ continue;
MSchedGraphNode *node = X->second;
//Loop over operands for this instruction and add value edges
for(unsigned i=0; i < (*I)->getNumOperands(); ++i) {
- //Get Operand
- const MachineOperand &mOp = (*I)->getOperand(i);
- if((mOp.getType() == MachineOperand::MO_VirtualRegister
- || mOp.getType() == MachineOperand::MO_CCRegister) && mOp.isUse()) {
-
- //find the value in the map
- if (const Value* srcI = mOp.getVRegValue()) {
-
- //Find value in the map
- std::map<const Value*, std::vector<OpIndexNodePair> >::iterator V
- = valuetoNodeMap.find(srcI);
-
- //If there is something in the map already, add edges from
- //those instructions
- //to this one we are processing
- if(V != valuetoNodeMap.end()) {
- addValueEdges(V->second, node, mOp.isUse(), mOp.isDef(),
- phiInstrs, 1);
- }
- }
- }
+ //Get Operand
+ const MachineOperand &mOp = (*I)->getOperand(i);
+ if((mOp.getType() == MachineOperand::MO_VirtualRegister
+ || mOp.getType() == MachineOperand::MO_CCRegister) && mOp.isUse()) {
+
+ //find the value in the map
+ if (const Value* srcI = mOp.getVRegValue()) {
+
+ //Find value in the map
+ std::map<const Value*, std::vector<OpIndexNodePair> >::iterator V
+ = valuetoNodeMap.find(srcI);
+
+ //If there is something in the map already, add edges from
+ //those instructions
+ //to this one we are processing
+ if(V != valuetoNodeMap.end()) {
+ addValueEdges(V->second, node, mOp.isUse(), mOp.isDef(),
+ phiInstrs, 1);
+ }
+ }
+ }
}
}
}
}
//Add dependencies for Value*s
void MSchedGraph::addValueEdges(std::vector<OpIndexNodePair> &NodesInMap,
- MSchedGraphNode *destNode, bool nodeIsUse,
- bool nodeIsDef, std::vector<const MachineInstr*> &phiInstrs, int diff) {
+ MSchedGraphNode *destNode, bool nodeIsUse,
+ bool nodeIsDef, std::vector<const MachineInstr*> &phiInstrs, int diff) {
for(std::vector<OpIndexNodePair>::iterator I = NodesInMap.begin(),
- E = NodesInMap.end(); I != E; ++I) {
+ E = NodesInMap.end(); I != E; ++I) {
//Get node in vectors machine operand that is the same value as node
MSchedGraphNode *srcNode = I->second;
if(diff > 0)
if(std::find(phiInstrs.begin(), phiInstrs.end(), srcNode->getInst()) == phiInstrs.end())
- continue;
+ continue;
//Node is a Def, so add output dep.
if(nodeIsDef) {
if(mOp.isUse()) {
- DEBUG(std::cerr << "Edge from " << *srcNode << " to " << *destNode << " (itediff=" << diff << ", type=anti)\n");
- srcNode->addOutEdge(destNode, MSchedGraphEdge::ValueDep,
- MSchedGraphEdge::AntiDep, diff);
+ DEBUG(std::cerr << "Edge from " << *srcNode << " to " << *destNode << " (itediff=" << diff << ", type=anti)\n");
+ srcNode->addOutEdge(destNode, MSchedGraphEdge::ValueDep,
+ MSchedGraphEdge::AntiDep, diff);
}
if(mOp.isDef()) {
- DEBUG(std::cerr << "Edge from " << *srcNode << " to " << *destNode << " (itediff=" << diff << ", type=output)\n");
- srcNode->addOutEdge(destNode, MSchedGraphEdge::ValueDep,
- MSchedGraphEdge::OutputDep, diff);
+ DEBUG(std::cerr << "Edge from " << *srcNode << " to " << *destNode << " (itediff=" << diff << ", type=output)\n");
+ srcNode->addOutEdge(destNode, MSchedGraphEdge::ValueDep,
+ MSchedGraphEdge::OutputDep, diff);
}
}
if(nodeIsUse) {
if(mOp.isDef()) {
- DEBUG(std::cerr << "Edge from " << *srcNode << " to " << *destNode << " (itediff=" << diff << ", type=true)\n");
- srcNode->addOutEdge(destNode, MSchedGraphEdge::ValueDep,
- MSchedGraphEdge::TrueDep, diff);
+ DEBUG(std::cerr << "Edge from " << *srcNode << " to " << *destNode << " (itediff=" << diff << ", type=true)\n");
+ srcNode->addOutEdge(destNode, MSchedGraphEdge::ValueDep,
+ MSchedGraphEdge::TrueDep, diff);
}
}
}
//Look at all instructions after this in execution order
for(unsigned j=i+1; j < Nodes.size(); ++j) {
-
- //Sink node is a write
- if(Nodes[j].second->getInst()->getOperand(Nodes[j].first).isDef()) {
- //Src only uses the register (read)
+
+ //Sink node is a write
+ if(Nodes[j].second->getInst()->getOperand(Nodes[j].first).isDef()) {
+ //Src only uses the register (read)
if(srcIsUse)
- srcNode->addOutEdge(Nodes[j].second,
- MSchedGraphEdge::MachineRegister,
- MSchedGraphEdge::AntiDep);
-
+ srcNode->addOutEdge(Nodes[j].second,
+ MSchedGraphEdge::MachineRegister,
+ MSchedGraphEdge::AntiDep);
+
else if(srcIsUseandDef) {
- srcNode->addOutEdge(Nodes[j].second,
- MSchedGraphEdge::MachineRegister,
- MSchedGraphEdge::AntiDep);
-
- srcNode->addOutEdge(Nodes[j].second,
- MSchedGraphEdge::MachineRegister,
- MSchedGraphEdge::OutputDep);
- }
+ srcNode->addOutEdge(Nodes[j].second,
+ MSchedGraphEdge::MachineRegister,
+ MSchedGraphEdge::AntiDep);
+
+ srcNode->addOutEdge(Nodes[j].second,
+ MSchedGraphEdge::MachineRegister,
+ MSchedGraphEdge::OutputDep);
+ }
else
- srcNode->addOutEdge(Nodes[j].second,
- MSchedGraphEdge::MachineRegister,
- MSchedGraphEdge::OutputDep);
- }
- //Dest node is a read
- else {
- if(!srcIsUse || srcIsUseandDef)
- srcNode->addOutEdge(Nodes[j].second,
- MSchedGraphEdge::MachineRegister,
- MSchedGraphEdge::TrueDep);
- }
+ srcNode->addOutEdge(Nodes[j].second,
+ MSchedGraphEdge::MachineRegister,
+ MSchedGraphEdge::OutputDep);
+ }
+ //Dest node is a read
+ else {
+ if(!srcIsUse || srcIsUseandDef)
+ srcNode->addOutEdge(Nodes[j].second,
+ MSchedGraphEdge::MachineRegister,
+ MSchedGraphEdge::TrueDep);
+ }
}
//Look at all the instructions before this one since machine registers
//could live across iterations.
for(unsigned j = 0; j < i; ++j) {
- //Sink node is a write
- if(Nodes[j].second->getInst()->getOperand(Nodes[j].first).isDef()) {
- //Src only uses the register (read)
+ //Sink node is a write
+ if(Nodes[j].second->getInst()->getOperand(Nodes[j].first).isDef()) {
+ //Src only uses the register (read)
if(srcIsUse)
- srcNode->addOutEdge(Nodes[j].second,
- MSchedGraphEdge::MachineRegister,
- MSchedGraphEdge::AntiDep, 1);
+ srcNode->addOutEdge(Nodes[j].second,
+ MSchedGraphEdge::MachineRegister,
+ MSchedGraphEdge::AntiDep, 1);
else if(srcIsUseandDef) {
- srcNode->addOutEdge(Nodes[j].second,
- MSchedGraphEdge::MachineRegister,
- MSchedGraphEdge::AntiDep, 1);
-
- srcNode->addOutEdge(Nodes[j].second,
- MSchedGraphEdge::MachineRegister,
- MSchedGraphEdge::OutputDep, 1);
- }
+ srcNode->addOutEdge(Nodes[j].second,
+ MSchedGraphEdge::MachineRegister,
+ MSchedGraphEdge::AntiDep, 1);
+
+ srcNode->addOutEdge(Nodes[j].second,
+ MSchedGraphEdge::MachineRegister,
+ MSchedGraphEdge::OutputDep, 1);
+ }
else
- srcNode->addOutEdge(Nodes[j].second,
- MSchedGraphEdge::MachineRegister,
- MSchedGraphEdge::OutputDep, 1);
- }
- //Dest node is a read
- else {
- if(!srcIsUse || srcIsUseandDef)
- srcNode->addOutEdge(Nodes[j].second,
- MSchedGraphEdge::MachineRegister,
- MSchedGraphEdge::TrueDep,1 );
- }
-
+ srcNode->addOutEdge(Nodes[j].second,
+ MSchedGraphEdge::MachineRegister,
+ MSchedGraphEdge::OutputDep, 1);
+ }
+ //Dest node is a read
+ else {
+ if(!srcIsUse || srcIsUseandDef)
+ srcNode->addOutEdge(Nodes[j].second,
+ MSchedGraphEdge::MachineRegister,
+ MSchedGraphEdge::TrueDep,1 );
+ }
+
}
//Add edges between all loads and stores
//Can be less strict with alias analysis and data dependence analysis.
void MSchedGraph::addMemEdges(const std::vector<MSchedGraphNode*>& memInst,
- DependenceAnalyzer &DA,
- std::map<MachineInstr*, Instruction*> &machineTollvm) {
+ DependenceAnalyzer &DA,
+ std::map<MachineInstr*, Instruction*> &machineTollvm) {
//Get Target machine instruction info
const TargetInstrInfo *TMI = Target.getInstrInfo();
//No self loops
if(destIndex == srcIndex)
- continue;
+ continue;
MachineInstr *destInst = (MachineInstr*) memInst[destIndex]->getInst();
//Assuming instructions without corresponding llvm instructions
//are from constant pools.
if (!machineTollvm.count(srcInst) || !machineTollvm.count(destInst))
- continue;
+ continue;
bool useDepAnalyzer = true;
Instruction *srcLLVM = machineTollvm[srcInst];
Instruction *destLLVM = machineTollvm[destInst];
if(!isa<LoadInst>(srcLLVM)
- && !isa<StoreInst>(srcLLVM)) {
- if(isa<BinaryOperator>(srcLLVM)) {
- if(isa<ConstantFP>(srcLLVM->getOperand(0)) || isa<ConstantFP>(srcLLVM->getOperand(1)))
- continue;
- }
- useDepAnalyzer = false;
+ && !isa<StoreInst>(srcLLVM)) {
+ if(isa<BinaryOperator>(srcLLVM)) {
+ if(isa<ConstantFP>(srcLLVM->getOperand(0)) || isa<ConstantFP>(srcLLVM->getOperand(1)))
+ continue;
+ }
+ useDepAnalyzer = false;
}
if(!isa<LoadInst>(destLLVM)
- && !isa<StoreInst>(destLLVM)) {
- if(isa<BinaryOperator>(destLLVM)) {
- if(isa<ConstantFP>(destLLVM->getOperand(0)) || isa<ConstantFP>(destLLVM->getOperand(1)))
- continue;
- }
- useDepAnalyzer = false;
+ && !isa<StoreInst>(destLLVM)) {
+ if(isa<BinaryOperator>(destLLVM)) {
+ if(isa<ConstantFP>(destLLVM->getOperand(0)) || isa<ConstantFP>(destLLVM->getOperand(1)))
+ continue;
+ }
+ useDepAnalyzer = false;
}
//Use dep analysis when we have corresponding llvm loads/stores
if(useDepAnalyzer) {
- bool srcBeforeDest = true;
- if(destIndex < srcIndex)
- srcBeforeDest = false;
-
- DependenceResult dr = DA.getDependenceInfo(machineTollvm[srcInst],
- machineTollvm[destInst],
- srcBeforeDest);
-
- for(std::vector<Dependence>::iterator d = dr.dependences.begin(),
- de = dr.dependences.end(); d != de; ++d) {
- //Add edge from load to store
- memInst[srcIndex]->addOutEdge(memInst[destIndex],
- MSchedGraphEdge::MemoryDep,
- d->getDepType(), d->getIteDiff());
-
- }
+ bool srcBeforeDest = true;
+ if(destIndex < srcIndex)
+ srcBeforeDest = false;
+
+ DependenceResult dr = DA.getDependenceInfo(machineTollvm[srcInst],
+ machineTollvm[destInst],
+ srcBeforeDest);
+
+ for(std::vector<Dependence>::iterator d = dr.dependences.begin(),
+ de = dr.dependences.end(); d != de; ++d) {
+ //Add edge from load to store
+ memInst[srcIndex]->addOutEdge(memInst[destIndex],
+ MSchedGraphEdge::MemoryDep,
+ d->getDepType(), d->getIteDiff());
+
+ }
}
//Otherwise, we can not do any further analysis and must make a dependence
else {
-
- //Get the machine opCode to determine type of memory instruction
- MachineOpCode destNodeOpCode = destInst->getOpcode();
-
- //Get the Value* that we are reading from the load, always the first op
- const MachineOperand &mOp = srcInst->getOperand(0);
- const MachineOperand &mOp2 = destInst->getOperand(0);
-
- if(mOp.hasAllocatedReg())
- if(mOp.getReg() == SparcV9::g0)
- continue;
- if(mOp2.hasAllocatedReg())
- if(mOp2.getReg() == SparcV9::g0)
- continue;
-
- DEBUG(std::cerr << "Adding dependence for machine instructions\n");
- //Load-Store deps
- if(TMI->isLoad(srcNodeOpCode)) {
-
- if(TMI->isStore(destNodeOpCode))
- memInst[srcIndex]->addOutEdge(memInst[destIndex],
- MSchedGraphEdge::MemoryDep,
- MSchedGraphEdge::AntiDep, 0);
- }
- else if(TMI->isStore(srcNodeOpCode)) {
- if(TMI->isStore(destNodeOpCode))
- memInst[srcIndex]->addOutEdge(memInst[destIndex],
- MSchedGraphEdge::MemoryDep,
- MSchedGraphEdge::OutputDep, 0);
-
- else
- memInst[srcIndex]->addOutEdge(memInst[destIndex],
- MSchedGraphEdge::MemoryDep,
- MSchedGraphEdge::TrueDep, 0);
- }
+
+ //Get the machine opCode to determine type of memory instruction
+ MachineOpCode destNodeOpCode = destInst->getOpcode();
+
+ //Get the Value* that we are reading from the load, always the first op
+ const MachineOperand &mOp = srcInst->getOperand(0);
+ const MachineOperand &mOp2 = destInst->getOperand(0);
+
+ if(mOp.hasAllocatedReg())
+ if(mOp.getReg() == SparcV9::g0)
+ continue;
+ if(mOp2.hasAllocatedReg())
+ if(mOp2.getReg() == SparcV9::g0)
+ continue;
+
+ DEBUG(std::cerr << "Adding dependence for machine instructions\n");
+ //Load-Store deps
+ if(TMI->isLoad(srcNodeOpCode)) {
+
+ if(TMI->isStore(destNodeOpCode))
+ memInst[srcIndex]->addOutEdge(memInst[destIndex],
+ MSchedGraphEdge::MemoryDep,
+ MSchedGraphEdge::AntiDep, 0);
+ }
+ else if(TMI->isStore(srcNodeOpCode)) {
+ if(TMI->isStore(destNodeOpCode))
+ memInst[srcIndex]->addOutEdge(memInst[destIndex],
+ MSchedGraphEdge::MemoryDep,
+ MSchedGraphEdge::OutputDep, 0);
+
+ else
+ memInst[srcIndex]->addOutEdge(memInst[destIndex],
+ MSchedGraphEdge::MemoryDep,
+ MSchedGraphEdge::TrueDep, 0);
+ }
}
}
}
private:
friend class MSchedGraphNode;
MSchedGraphEdge(MSchedGraphNode *destination, MSchedGraphEdgeType type,
- unsigned deptype, unsigned diff)
+ unsigned deptype, unsigned diff)
: dest(destination), depType(type), depOrderType(deptype), iteDiff(diff) {}
MSchedGraphNode *dest;
public:
MSchedGraphNode(const MachineInstr *inst, MSchedGraph *graph,
- unsigned index, unsigned late=0, bool isBranch=false);
+ unsigned index, unsigned late=0, bool isBranch=false);
MSchedGraphNode(const MSchedGraphNode &N);
pred_const_iterator pred_end() const { return Predecessors.end(); }
typedef MSchedGraphNodeIterator<std::vector<MSchedGraphEdge>::const_iterator,
- const MSchedGraphNode> succ_const_iterator;
+ const MSchedGraphNode> succ_const_iterator;
succ_const_iterator succ_begin() const;
succ_const_iterator succ_end() const;
typedef MSchedGraphNodeIterator<std::vector<MSchedGraphEdge>::iterator,
- MSchedGraphNode> succ_iterator;
+ MSchedGraphNode> succ_iterator;
succ_iterator succ_begin();
succ_iterator succ_end();
unsigned succ_size() { return Successors.size(); }
void deleteSuccessor(MSchedGraphNode *node) {
for (unsigned i = 0; i != Successors.size(); ++i)
- if (Successors[i].getDest() == node) {
- Successors.erase(Successors.begin()+i);
- node->Predecessors.erase(std::find(node->Predecessors.begin(),
- node->Predecessors.end(), this));
- --i; //Decrease index var since we deleted a node
- }
+ if (Successors[i].getDest() == node) {
+ Successors.erase(Successors.begin()+i);
+ node->Predecessors.erase(std::find(node->Predecessors.begin(),
+ node->Predecessors.end(), this));
+ --i; //Decrease index var since we deleted a node
+ }
}
void addOutEdge(MSchedGraphNode *destination,
- MSchedGraphEdge::MSchedGraphEdgeType type,
- unsigned deptype, unsigned diff=0) {
+ MSchedGraphEdge::MSchedGraphEdgeType type,
+ unsigned deptype, unsigned diff=0) {
Successors.push_back(MSchedGraphEdge(destination, type, deptype,diff));
destination->Predecessors.push_back(this);
}
// ostream << operator for MSGraphNode class
inline std::ostream &operator<<(std::ostream &os,
- const MSchedGraphNode &node) {
+ const MSchedGraphNode &node) {
node.print(os);
return os;
}
typedef std::pair<int, MSchedGraphNode*> OpIndexNodePair;
void buildNodesAndEdges(std::map<const MachineInstr*, unsigned> &ignoreInstrs, DependenceAnalyzer &DA, std::map<MachineInstr*, Instruction*> &machineTollvm);
void addValueEdges(std::vector<OpIndexNodePair> &NodesInMap,
- MSchedGraphNode *node,
- bool nodeIsUse, bool nodeIsDef, std::vector<const MachineInstr*> &phiInstrs, int diff=0);
+ MSchedGraphNode *node,
+ bool nodeIsUse, bool nodeIsDef, std::vector<const MachineInstr*> &phiInstrs, int diff=0);
void addMachRegEdges(std::map<int,
- std::vector<OpIndexNodePair> >& regNumtoNodeMap);
+ std::vector<OpIndexNodePair> >& regNumtoNodeMap);
void addMemEdges(const std::vector<MSchedGraphNode*>& memInst,
- DependenceAnalyzer &DA, std::map<MachineInstr*, Instruction*> &machineTollvm);
+ DependenceAnalyzer &DA, std::map<MachineInstr*, Instruction*> &machineTollvm);
void addBranchEdges();
public:
MSchedGraph(const MachineBasicBlock *bb, const TargetMachine &targ,
- std::map<const MachineInstr*, unsigned> &ignoreInstrs,
- DependenceAnalyzer &DA, std::map<MachineInstr*, Instruction*> &machineTollvm);
+ std::map<const MachineInstr*, unsigned> &ignoreInstrs,
+ DependenceAnalyzer &DA, std::map<MachineInstr*, Instruction*> &machineTollvm);
//Copy constructor with maps to link old nodes to new nodes
MSchedGraph(const MSchedGraph &G, std::map<MSchedGraphNode*, MSchedGraphNode*> &newNodes);
-
- MSchedGraph(std::vector<const MachineBasicBlock*> &bbs,
- const TargetMachine &targ,
- std::map<const MachineInstr*, unsigned> &ignoreInstrs,
- DependenceAnalyzer &DA,
- std::map<MachineInstr*, Instruction*> &machineTollvm);
+
+ MSchedGraph(std::vector<const MachineBasicBlock*> &bbs,
+ const TargetMachine &targ,
+ std::map<const MachineInstr*, unsigned> &ignoreInstrs,
+ DependenceAnalyzer &DA,
+ std::map<MachineInstr*, Instruction*> &machineTollvm);
//Print graph
void print(std::ostream &os) const;
// Provide specializations of GraphTraits to be able to use graph
// iterators on the scheduling graph
static MSchedGraphNode& getSecond(std::pair<const MachineInstr* const,
- MSchedGraphNode*> &Pair) {
+ MSchedGraphNode*> &Pair) {
return *Pair.second;
}
return N->succ_end();
}
typedef std::pointer_to_unary_function<std::pair<const MachineInstr* const,
- MSchedGraphNode*>&, MSchedGraphNode&> DerefFun;
+ MSchedGraphNode*>&, MSchedGraphNode&> DerefFun;
typedef mapped_iterator<MSchedGraph::iterator, DerefFun> nodes_iterator;
static nodes_iterator nodes_begin(MSchedGraph *G) {
}
typedef std::pointer_to_unary_function<std::pair<const MachineInstr* const,
- MSchedGraphNode*>&, MSchedGraphNode&> DerefFun;
+ MSchedGraphNode*>&, MSchedGraphNode&> DerefFun;
typedef mapped_iterator<MSchedGraph::iterator, DerefFun> nodes_iterator;
static nodes_iterator nodes_begin(MSchedGraph *G) {
//MSchedGraphSBNode constructor
MSchedGraphSBNode::MSchedGraphSBNode(const MachineInstr* inst,
- MSchedGraphSB *graph, unsigned idx,
- unsigned late, bool isBranch)
+ MSchedGraphSB *graph, unsigned idx,
+ unsigned late, bool isBranch)
: Inst(inst), Parent(graph), index(idx), latency(late),
isBranchInstr(isBranch) {
//MSchedGraphSBNode constructor
MSchedGraphSBNode::MSchedGraphSBNode(const MachineInstr* inst,
- std::vector<const MachineInstr*> &other,
- MSchedGraphSB *graph, unsigned idx,
- unsigned late, bool isPNode)
+ std::vector<const MachineInstr*> &other,
+ MSchedGraphSB *graph, unsigned idx,
+ unsigned late, bool isPNode)
: Inst(inst), otherInstrs(other), Parent(graph), index(idx), latency(late), isPredicateNode(isPNode) {
//Get the iteration difference for the edge from this node to its successor
unsigned MSchedGraphSBNode::getIteDiff(MSchedGraphSBNode *succ) {
for(std::vector<MSchedGraphSBEdge>::iterator I = Successors.begin(),
- E = Successors.end();
+ E = Successors.end();
I != E; ++I) {
if(I->getDest() == succ)
return I->getIteDiff();
//return the edge the corresponds to this in edge
int count = 0;
for(MSchedGraphSBNode::succ_iterator I = pred->succ_begin(),
- E = pred->succ_end();
+ E = pred->succ_end();
I != E; ++I) {
if(*I == this)
return count;
//Dtermine if pred is a predecessor of this node
bool MSchedGraphSBNode::isPredecessor(MSchedGraphSBNode *pred) {
if(std::find( Predecessors.begin(), Predecessors.end(),
- pred) != Predecessors.end())
+ pred) != Predecessors.end())
return true;
else
return false;
//Add a node to the graph
void MSchedGraphSB::addNode(const MachineInstr* MI,
- MSchedGraphSBNode *node) {
+ MSchedGraphSBNode *node) {
//Make sure node does not already exist
assert(GraphMap.find(MI) == GraphMap.end()
- && "New MSchedGraphSBNode already exists for this instruction");
+ && "New MSchedGraphSBNode already exists for this instruction");
GraphMap[MI] = node;
}
//is a special case in Modulo Scheduling. We only want to deal with
//the body of the loop.
MSchedGraphSB::MSchedGraphSB(std::vector<const MachineBasicBlock*> &bbs,
- const TargetMachine &targ,
- std::map<const MachineInstr*, unsigned> &ignoreInstrs,
- DependenceAnalyzer &DA,
- std::map<MachineInstr*, Instruction*> &machineTollvm)
+ const TargetMachine &targ,
+ std::map<const MachineInstr*, unsigned> &ignoreInstrs,
+ DependenceAnalyzer &DA,
+ std::map<MachineInstr*, Instruction*> &machineTollvm)
: BBs(bbs), Target(targ) {
//Make sure there is at least one BB and it is not null,
assert(cond && "Condition must not be null!");
if(Instruction *I = dyn_cast<Instruction>(cond)) {
- MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(I);
- if(tempMvec.size() > 0) {
- DEBUG(std::cerr << *(tempMvec[tempMvec.size()-1]) << "\n");;
- instr = (MachineInstr*) tempMvec[tempMvec.size()-1];
- }
+ MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(I);
+ if(tempMvec.size() > 0) {
+ DEBUG(std::cerr << *(tempMvec[tempMvec.size()-1]) << "\n");;
+ instr = (MachineInstr*) tempMvec[tempMvec.size()-1];
+ }
}
}
for (unsigned j = 0; j < tempMvec.size(); j++) {
MachineInstr *mi = tempMvec[j];
if(MTI->isNop(mi->getOpcode()))
- continue;
+ continue;
if(!instr) {
- instr = mi;
- DEBUG(std::cerr << "No Cond MI: " << *mi << "\n");
+ instr = mi;
+ DEBUG(std::cerr << "No Cond MI: " << *mi << "\n");
}
else {
- DEBUG(std::cerr << *mi << "\n");;
- otherInstrs.push_back(mi);
+ DEBUG(std::cerr << *mi << "\n");;
+ otherInstrs.push_back(mi);
}
}
for(MachineBasicBlock::iterator I = mb->begin(), E = mb->end(); I != E; ++I) {
MachineInstr *instr = I;
if(MTI->isNop(instr->getOpcode()) || MTI->isBranch(instr->getOpcode()))
- continue;
+ continue;
if(node->getInst() == instr)
- continue;
+ continue;
for(unsigned i=0; i < instr->getNumOperands(); ++i) {
- MachineOperand &mOp = instr->getOperand(i);
- if(mOp.isDef() && mOp.getType() == MachineOperand::MO_VirtualRegister) {
- Value *val = mOp.getVRegValue();
- //Check if there is a use not in the trace
- for(Value::use_iterator V = val->use_begin(), VE = val->use_end(); V != VE; ++V) {
- if (Instruction *Inst = dyn_cast<Instruction>(*V)) {
- if(llvmBBs.count(Inst->getParent()))
- liveOutsideTrace[node].insert(instr);
- }
- }
- }
+ MachineOperand &mOp = instr->getOperand(i);
+ if(mOp.isDef() && mOp.getType() == MachineOperand::MO_VirtualRegister) {
+ Value *val = mOp.getVRegValue();
+ //Check if there is a use not in the trace
+ for(Value::use_iterator V = val->use_begin(), VE = val->use_end(); V != VE; ++V) {
+ if (Instruction *Inst = dyn_cast<Instruction>(*V)) {
+ if(llvmBBs.count(Inst->getParent()))
+ liveOutsideTrace[node].insert(instr);
+ }
+ }
+ }
}
}
//Copies the graph and keeps a map from old to new nodes
MSchedGraphSB::MSchedGraphSB(const MSchedGraphSB &G,
- std::map<MSchedGraphSBNode*, MSchedGraphSBNode*> &newNodes)
+ std::map<MSchedGraphSBNode*, MSchedGraphSBNode*> &newNodes)
: Target(G.Target) {
BBs = G.BBs;
std::map<MSchedGraphSBNode*, MSchedGraphSBNode*> oldToNew;
//Copy all nodes
for(MSchedGraphSB::const_iterator N = G.GraphMap.begin(),
- NE = G.GraphMap.end(); N != NE; ++N) {
+ NE = G.GraphMap.end(); N != NE; ++N) {
MSchedGraphSBNode *newNode = new MSchedGraphSBNode(*(N->second));
oldToNew[&*(N->second)] = newNode;
//Add edges between the nodes
void MSchedGraphSB::buildNodesAndEdges(std::map<const MachineInstr*, unsigned> &ignoreInstrs,
- DependenceAnalyzer &DA,
- std::map<MachineInstr*, Instruction*> &machineTollvm,
- std::map<MSchedGraphSBNode*, std::set<MachineInstr*> > &liveOutsideTrace) {
+ DependenceAnalyzer &DA,
+ std::map<MachineInstr*, Instruction*> &machineTollvm,
+ std::map<MSchedGraphSBNode*, std::set<MachineInstr*> > &liveOutsideTrace) {
//Get Machine target information for calculating latency
for(std::vector<const MachineBasicBlock*>::iterator B = BBs.begin(),
- BE = BBs.end(); B != BE; ++B) {
+ BE = BBs.end(); B != BE; ++B) {
const MachineBasicBlock *BB = *B;
//Loop over instructions in MBB and add nodes and edges
for (MachineBasicBlock::const_iterator MI = BB->begin(), e = BB->end();
- MI != e; ++MI) {
+ MI != e; ++MI) {
//Ignore indvar instructions
if(ignoreInstrs.count(MI)) {
- ++index;
- continue;
+ ++index;
+ continue;
}
//Get each instruction of machine basic block, get the delay
//Create new node for this machine instruction and add to the graph.
//Create only if not a nop
if(MTI->isNop(opCode))
- continue;
+ continue;
//Sparc BE does not use PHI opcode, so assert on this case
assert(opCode != TargetInstrInfo::PHI && "Did not expect PHI opcode");
//Skip branches
if(MTI->isBranch(opCode))
- continue;
+ continue;
//Node is created and added to the graph automatically
MSchedGraphSBNode *node = 0;
if(!GraphMap.count(MI)){
- node = new MSchedGraphSBNode(MI, this, index, delay);
- DEBUG(std::cerr << "Created Node: " << *node << "\n");
+ node = new MSchedGraphSBNode(MI, this, index, delay);
+ DEBUG(std::cerr << "Created Node: " << *node << "\n");
}
else {
- node = GraphMap[MI];
- if(node->isPredicate()) {
- //Create edge between this node and last pred, then switch to new pred
- if(lastPred) {
- lastPred->addOutEdge(node, MSchedGraphSBEdge::PredDep,
- MSchedGraphSBEdge::NonDataDep, 0);
-
- if(liveOutsideTrace.count(lastPred)) {
- for(std::set<MachineInstr*>::iterator L = liveOutsideTrace[lastPred].begin(), LE = liveOutsideTrace[lastPred].end(); L != LE; ++L)
- lastPred->addOutEdge(GraphMap[*L], MSchedGraphSBEdge::PredDep,
- MSchedGraphSBEdge::NonDataDep, 1);
- }
-
- }
-
- lastPred = node;
- }
+ node = GraphMap[MI];
+ if(node->isPredicate()) {
+ //Create edge between this node and last pred, then switch to new pred
+ if(lastPred) {
+ lastPred->addOutEdge(node, MSchedGraphSBEdge::PredDep,
+ MSchedGraphSBEdge::NonDataDep, 0);
+
+ if(liveOutsideTrace.count(lastPred)) {
+ for(std::set<MachineInstr*>::iterator L = liveOutsideTrace[lastPred].begin(), LE = liveOutsideTrace[lastPred].end(); L != LE; ++L)
+ lastPred->addOutEdge(GraphMap[*L], MSchedGraphSBEdge::PredDep,
+ MSchedGraphSBEdge::NonDataDep, 1);
+ }
+
+ }
+
+ lastPred = node;
+ }
}
//Add dependencies to instructions that cause exceptions
if(lastPred)
- lastPred->print(std::cerr);
+ lastPred->print(std::cerr);
if(!node->isPredicate() && instrCauseException(opCode)) {
- if(lastPred) {
- lastPred->addOutEdge(node, MSchedGraphSBEdge::PredDep,
- MSchedGraphSBEdge::NonDataDep, 0);
- }
+ if(lastPred) {
+ lastPred->addOutEdge(node, MSchedGraphSBEdge::PredDep,
+ MSchedGraphSBEdge::NonDataDep, 0);
+ }
}
//Check OpCode to keep track of memory operations to add memory
//dependencies later.
if(MTI->isLoad(opCode) || MTI->isStore(opCode))
- memInstructions.push_back(node);
+ memInstructions.push_back(node);
//Loop over all operands, and put them into the register number to
//graph node map for determining dependencies
//If an operands is a use/def, we have an anti dependence to itself
for(unsigned i=0; i < MI->getNumOperands(); ++i) {
- //Get Operand
- const MachineOperand &mOp = MI->getOperand(i);
-
- //Check if it has an allocated register
- if(mOp.hasAllocatedReg()) {
- int regNum = mOp.getReg();
-
- if(regNum != SparcV9::g0) {
- //Put into our map
- regNumtoNodeMap[regNum].push_back(std::make_pair(i, node));
- }
- continue;
- }
-
-
- //Add virtual registers dependencies
- //Check if any exist in the value map already and create dependencies
- //between them.
- if(mOp.getType() == MachineOperand::MO_VirtualRegister
- || mOp.getType() == MachineOperand::MO_CCRegister) {
-
- //Make sure virtual register value is not null
- assert((mOp.getVRegValue() != NULL) && "Null value is defined");
-
- //Check if this is a read operation in a phi node, if so DO NOT PROCESS
- if(mOp.isUse() && (opCode == TargetInstrInfo::PHI)) {
- DEBUG(std::cerr << "Read Operation in a PHI node\n");
- continue;
- }
-
- if (const Value* srcI = mOp.getVRegValue()) {
-
- //Find value in the map
- std::map<const Value*, std::vector<OpIndexNodePair> >::iterator V
- = valuetoNodeMap.find(srcI);
-
- //If there is something in the map already, add edges from
- //those instructions
- //to this one we are processing
- if(V != valuetoNodeMap.end()) {
- addValueEdges(V->second, node, mOp.isUse(), mOp.isDef(), phiInstrs);
-
- //Add to value map
- V->second.push_back(std::make_pair(i,node));
- }
- //Otherwise put it in the map
- else
- //Put into value map
- valuetoNodeMap[mOp.getVRegValue()].push_back(std::make_pair(i, node));
- }
- }
+ //Get Operand
+ const MachineOperand &mOp = MI->getOperand(i);
+
+ //Check if it has an allocated register
+ if(mOp.hasAllocatedReg()) {
+ int regNum = mOp.getReg();
+
+ if(regNum != SparcV9::g0) {
+ //Put into our map
+ regNumtoNodeMap[regNum].push_back(std::make_pair(i, node));
+ }
+ continue;
+ }
+
+
+ //Add virtual registers dependencies
+ //Check if any exist in the value map already and create dependencies
+ //between them.
+ if(mOp.getType() == MachineOperand::MO_VirtualRegister
+ || mOp.getType() == MachineOperand::MO_CCRegister) {
+
+ //Make sure virtual register value is not null
+ assert((mOp.getVRegValue() != NULL) && "Null value is defined");
+
+ //Check if this is a read operation in a phi node, if so DO NOT PROCESS
+ if(mOp.isUse() && (opCode == TargetInstrInfo::PHI)) {
+ DEBUG(std::cerr << "Read Operation in a PHI node\n");
+ continue;
+ }
+
+ if (const Value* srcI = mOp.getVRegValue()) {
+
+ //Find value in the map
+ std::map<const Value*, std::vector<OpIndexNodePair> >::iterator V
+ = valuetoNodeMap.find(srcI);
+
+ //If there is something in the map already, add edges from
+ //those instructions
+ //to this one we are processing
+ if(V != valuetoNodeMap.end()) {
+ addValueEdges(V->second, node, mOp.isUse(), mOp.isDef(), phiInstrs);
+
+ //Add to value map
+ V->second.push_back(std::make_pair(i,node));
+ }
+ //Otherwise put it in the map
+ else
+ //Put into value map
+ valuetoNodeMap[mOp.getVRegValue()].push_back(std::make_pair(i, node));
+ }
+ }
}
++index;
}
//phiInstr list to process
const BasicBlock *llvm_bb = BB->getBasicBlock();
for(BasicBlock::const_iterator I = llvm_bb->begin(), E = llvm_bb->end();
- I != E; ++I) {
+ I != E; ++I) {
if(const PHINode *PN = dyn_cast<PHINode>(I)) {
- MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(PN);
- for (unsigned j = 0; j < tempMvec.size(); j++) {
- if(!ignoreInstrs.count(tempMvec[j])) {
- DEBUG(std::cerr << "Inserting phi instr into map: " << *tempMvec[j] << "\n");
- phiInstrs.push_back((MachineInstr*) tempMvec[j]);
- }
- }
+ MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(PN);
+ for (unsigned j = 0; j < tempMvec.size(); j++) {
+ if(!ignoreInstrs.count(tempMvec[j])) {
+ DEBUG(std::cerr << "Inserting phi instr into map: " << *tempMvec[j] << "\n");
+ phiInstrs.push_back((MachineInstr*) tempMvec[j]);
+ }
+ }
}
}
//Finally deal with PHI Nodes and Value*
for(std::vector<const MachineInstr*>::iterator I = phiInstrs.begin(),
- E = phiInstrs.end(); I != E; ++I) {
+ E = phiInstrs.end(); I != E; ++I) {
//Get Node for this instruction
std::map<const MachineInstr*, MSchedGraphSBNode*>::iterator X;
X = find(*I);
if(X == GraphMap.end())
- continue;
+ continue;
MSchedGraphSBNode *node = X->second;
//Loop over operands for this instruction and add value edges
for(unsigned i=0; i < (*I)->getNumOperands(); ++i) {
- //Get Operand
- const MachineOperand &mOp = (*I)->getOperand(i);
- if((mOp.getType() == MachineOperand::MO_VirtualRegister
- || mOp.getType() == MachineOperand::MO_CCRegister) && mOp.isUse()) {
-
- //find the value in the map
- if (const Value* srcI = mOp.getVRegValue()) {
-
- //Find value in the map
- std::map<const Value*, std::vector<OpIndexNodePair> >::iterator V
- = valuetoNodeMap.find(srcI);
-
- //If there is something in the map already, add edges from
- //those instructions
- //to this one we are processing
- if(V != valuetoNodeMap.end()) {
- addValueEdges(V->second, node, mOp.isUse(), mOp.isDef(),
- phiInstrs, 1);
- }
- }
- }
+ //Get Operand
+ const MachineOperand &mOp = (*I)->getOperand(i);
+ if((mOp.getType() == MachineOperand::MO_VirtualRegister
+ || mOp.getType() == MachineOperand::MO_CCRegister) && mOp.isUse()) {
+
+ //find the value in the map
+ if (const Value* srcI = mOp.getVRegValue()) {
+
+ //Find value in the map
+ std::map<const Value*, std::vector<OpIndexNodePair> >::iterator V
+ = valuetoNodeMap.find(srcI);
+
+ //If there is something in the map already, add edges from
+ //those instructions
+ //to this one we are processing
+ if(V != valuetoNodeMap.end()) {
+ addValueEdges(V->second, node, mOp.isUse(), mOp.isDef(),
+ phiInstrs, 1);
+ }
+ }
+ }
}
}
}
}
//Add dependencies for Value*s
void MSchedGraphSB::addValueEdges(std::vector<OpIndexNodePair> &NodesInMap,
- MSchedGraphSBNode *destNode, bool nodeIsUse,
- bool nodeIsDef, std::vector<const MachineInstr*> &phiInstrs, int diff) {
+ MSchedGraphSBNode *destNode, bool nodeIsUse,
+ bool nodeIsDef, std::vector<const MachineInstr*> &phiInstrs, int diff) {
for(std::vector<OpIndexNodePair>::iterator I = NodesInMap.begin(),
- E = NodesInMap.end(); I != E; ++I) {
+ E = NodesInMap.end(); I != E; ++I) {
//Get node in vectors machine operand that is the same value as node
MSchedGraphSBNode *srcNode = I->second;
if(diff > 0)
if(std::find(phiInstrs.begin(), phiInstrs.end(), srcNode->getInst()) == phiInstrs.end())
- continue;
+ continue;
//Node is a Def, so add output dep.
if(nodeIsDef) {
if(mOp.isUse()) {
- DEBUG(std::cerr << "Edge from " << *srcNode << " to " << *destNode << " (itediff=" << diff << ", type=anti)\n");
- srcNode->addOutEdge(destNode, MSchedGraphSBEdge::ValueDep,
- MSchedGraphSBEdge::AntiDep, diff);
+ DEBUG(std::cerr << "Edge from " << *srcNode << " to " << *destNode << " (itediff=" << diff << ", type=anti)\n");
+ srcNode->addOutEdge(destNode, MSchedGraphSBEdge::ValueDep,
+ MSchedGraphSBEdge::AntiDep, diff);
}
if(mOp.isDef()) {
- DEBUG(std::cerr << "Edge from " << *srcNode << " to " << *destNode << " (itediff=" << diff << ", type=output)\n");
- srcNode->addOutEdge(destNode, MSchedGraphSBEdge::ValueDep,
- MSchedGraphSBEdge::OutputDep, diff);
+ DEBUG(std::cerr << "Edge from " << *srcNode << " to " << *destNode << " (itediff=" << diff << ", type=output)\n");
+ srcNode->addOutEdge(destNode, MSchedGraphSBEdge::ValueDep,
+ MSchedGraphSBEdge::OutputDep, diff);
}
}
if(nodeIsUse) {
if(mOp.isDef()) {
- DEBUG(std::cerr << "Edge from " << *srcNode << " to " << *destNode << " (itediff=" << diff << ", type=true)\n");
- srcNode->addOutEdge(destNode, MSchedGraphSBEdge::ValueDep,
- MSchedGraphSBEdge::TrueDep, diff);
+ DEBUG(std::cerr << "Edge from " << *srcNode << " to " << *destNode << " (itediff=" << diff << ", type=true)\n");
+ srcNode->addOutEdge(destNode, MSchedGraphSBEdge::ValueDep,
+ MSchedGraphSBEdge::TrueDep, diff);
}
}
}
//Look at all instructions after this in execution order
for(unsigned j=i+1; j < Nodes.size(); ++j) {
-
- //Sink node is a write
- if(Nodes[j].second->getInst()->getOperand(Nodes[j].first).isDef()) {
- //Src only uses the register (read)
+
+ //Sink node is a write
+ if(Nodes[j].second->getInst()->getOperand(Nodes[j].first).isDef()) {
+ //Src only uses the register (read)
if(srcIsUse)
- srcNode->addOutEdge(Nodes[j].second,
- MSchedGraphSBEdge::MachineRegister,
- MSchedGraphSBEdge::AntiDep);
-
+ srcNode->addOutEdge(Nodes[j].second,
+ MSchedGraphSBEdge::MachineRegister,
+ MSchedGraphSBEdge::AntiDep);
+
else if(srcIsUseandDef) {
- srcNode->addOutEdge(Nodes[j].second,
- MSchedGraphSBEdge::MachineRegister,
- MSchedGraphSBEdge::AntiDep);
-
- srcNode->addOutEdge(Nodes[j].second,
- MSchedGraphSBEdge::MachineRegister,
- MSchedGraphSBEdge::OutputDep);
- }
+ srcNode->addOutEdge(Nodes[j].second,
+ MSchedGraphSBEdge::MachineRegister,
+ MSchedGraphSBEdge::AntiDep);
+
+ srcNode->addOutEdge(Nodes[j].second,
+ MSchedGraphSBEdge::MachineRegister,
+ MSchedGraphSBEdge::OutputDep);
+ }
else
- srcNode->addOutEdge(Nodes[j].second,
- MSchedGraphSBEdge::MachineRegister,
- MSchedGraphSBEdge::OutputDep);
- }
- //Dest node is a read
- else {
- if(!srcIsUse || srcIsUseandDef)
- srcNode->addOutEdge(Nodes[j].second,
- MSchedGraphSBEdge::MachineRegister,
- MSchedGraphSBEdge::TrueDep);
- }
+ srcNode->addOutEdge(Nodes[j].second,
+ MSchedGraphSBEdge::MachineRegister,
+ MSchedGraphSBEdge::OutputDep);
+ }
+ //Dest node is a read
+ else {
+ if(!srcIsUse || srcIsUseandDef)
+ srcNode->addOutEdge(Nodes[j].second,
+ MSchedGraphSBEdge::MachineRegister,
+ MSchedGraphSBEdge::TrueDep);
+ }
}
//Look at all the instructions before this one since machine registers
//could live across iterations.
for(unsigned j = 0; j < i; ++j) {
- //Sink node is a write
- if(Nodes[j].second->getInst()->getOperand(Nodes[j].first).isDef()) {
- //Src only uses the register (read)
+ //Sink node is a write
+ if(Nodes[j].second->getInst()->getOperand(Nodes[j].first).isDef()) {
+ //Src only uses the register (read)
if(srcIsUse)
- srcNode->addOutEdge(Nodes[j].second,
- MSchedGraphSBEdge::MachineRegister,
- MSchedGraphSBEdge::AntiDep, 1);
+ srcNode->addOutEdge(Nodes[j].second,
+ MSchedGraphSBEdge::MachineRegister,
+ MSchedGraphSBEdge::AntiDep, 1);
else if(srcIsUseandDef) {
- srcNode->addOutEdge(Nodes[j].second,
- MSchedGraphSBEdge::MachineRegister,
- MSchedGraphSBEdge::AntiDep, 1);
-
- srcNode->addOutEdge(Nodes[j].second,
- MSchedGraphSBEdge::MachineRegister,
- MSchedGraphSBEdge::OutputDep, 1);
- }
+ srcNode->addOutEdge(Nodes[j].second,
+ MSchedGraphSBEdge::MachineRegister,
+ MSchedGraphSBEdge::AntiDep, 1);
+
+ srcNode->addOutEdge(Nodes[j].second,
+ MSchedGraphSBEdge::MachineRegister,
+ MSchedGraphSBEdge::OutputDep, 1);
+ }
else
- srcNode->addOutEdge(Nodes[j].second,
- MSchedGraphSBEdge::MachineRegister,
- MSchedGraphSBEdge::OutputDep, 1);
- }
- //Dest node is a read
- else {
- if(!srcIsUse || srcIsUseandDef)
- srcNode->addOutEdge(Nodes[j].second,
- MSchedGraphSBEdge::MachineRegister,
- MSchedGraphSBEdge::TrueDep,1 );
- }
-
+ srcNode->addOutEdge(Nodes[j].second,
+ MSchedGraphSBEdge::MachineRegister,
+ MSchedGraphSBEdge::OutputDep, 1);
+ }
+ //Dest node is a read
+ else {
+ if(!srcIsUse || srcIsUseandDef)
+ srcNode->addOutEdge(Nodes[j].second,
+ MSchedGraphSBEdge::MachineRegister,
+ MSchedGraphSBEdge::TrueDep,1 );
+ }
+
}
//Add edges between all loads and stores
//Can be less strict with alias analysis and data dependence analysis.
void MSchedGraphSB::addMemEdges(const std::vector<MSchedGraphSBNode*>& memInst,
- DependenceAnalyzer &DA,
- std::map<MachineInstr*, Instruction*> &machineTollvm) {
+ DependenceAnalyzer &DA,
+ std::map<MachineInstr*, Instruction*> &machineTollvm) {
//Get Target machine instruction info
const TargetInstrInfo *TMI = Target.getInstrInfo();
//No self loops
if(destIndex == srcIndex)
- continue;
+ continue;
MachineInstr *destInst = (MachineInstr*) memInst[destIndex]->getInst();
//Assuming instructions without corresponding llvm instructions
//are from constant pools.
if (!machineTollvm.count(srcInst) || !machineTollvm.count(destInst))
- continue;
+ continue;
bool useDepAnalyzer = true;
Instruction *srcLLVM = machineTollvm[srcInst];
Instruction *destLLVM = machineTollvm[destInst];
if(!isa<LoadInst>(srcLLVM)
- && !isa<StoreInst>(srcLLVM)) {
- if(isa<BinaryOperator>(srcLLVM)) {
- if(isa<ConstantFP>(srcLLVM->getOperand(0)) || isa<ConstantFP>(srcLLVM->getOperand(1)))
- continue;
- }
- useDepAnalyzer = false;
+ && !isa<StoreInst>(srcLLVM)) {
+ if(isa<BinaryOperator>(srcLLVM)) {
+ if(isa<ConstantFP>(srcLLVM->getOperand(0)) || isa<ConstantFP>(srcLLVM->getOperand(1)))
+ continue;
+ }
+ useDepAnalyzer = false;
}
if(!isa<LoadInst>(destLLVM)
- && !isa<StoreInst>(destLLVM)) {
- if(isa<BinaryOperator>(destLLVM)) {
- if(isa<ConstantFP>(destLLVM->getOperand(0)) || isa<ConstantFP>(destLLVM->getOperand(1)))
- continue;
- }
- useDepAnalyzer = false;
+ && !isa<StoreInst>(destLLVM)) {
+ if(isa<BinaryOperator>(destLLVM)) {
+ if(isa<ConstantFP>(destLLVM->getOperand(0)) || isa<ConstantFP>(destLLVM->getOperand(1)))
+ continue;
+ }
+ useDepAnalyzer = false;
}
//Use dep analysis when we have corresponding llvm loads/stores
if(useDepAnalyzer) {
- bool srcBeforeDest = true;
- if(destIndex < srcIndex)
- srcBeforeDest = false;
-
- DependenceResult dr = DA.getDependenceInfo(machineTollvm[srcInst],
- machineTollvm[destInst],
- srcBeforeDest);
-
- for(std::vector<Dependence>::iterator d = dr.dependences.begin(),
- de = dr.dependences.end(); d != de; ++d) {
- //Add edge from load to store
- memInst[srcIndex]->addOutEdge(memInst[destIndex],
- MSchedGraphSBEdge::MemoryDep,
- d->getDepType(), d->getIteDiff());
-
- }
+ bool srcBeforeDest = true;
+ if(destIndex < srcIndex)
+ srcBeforeDest = false;
+
+ DependenceResult dr = DA.getDependenceInfo(machineTollvm[srcInst],
+ machineTollvm[destInst],
+ srcBeforeDest);
+
+ for(std::vector<Dependence>::iterator d = dr.dependences.begin(),
+ de = dr.dependences.end(); d != de; ++d) {
+ //Add edge from load to store
+ memInst[srcIndex]->addOutEdge(memInst[destIndex],
+ MSchedGraphSBEdge::MemoryDep,
+ d->getDepType(), d->getIteDiff());
+
+ }
}
//Otherwise, we can not do any further analysis and must make a dependence
else {
-
- //Get the machine opCode to determine type of memory instruction
- MachineOpCode destNodeOpCode = destInst->getOpcode();
-
- //Get the Value* that we are reading from the load, always the first op
- const MachineOperand &mOp = srcInst->getOperand(0);
- const MachineOperand &mOp2 = destInst->getOperand(0);
-
- if(mOp.hasAllocatedReg())
- if(mOp.getReg() == SparcV9::g0)
- continue;
- if(mOp2.hasAllocatedReg())
- if(mOp2.getReg() == SparcV9::g0)
- continue;
-
- DEBUG(std::cerr << "Adding dependence for machine instructions\n");
- //Load-Store deps
- if(TMI->isLoad(srcNodeOpCode)) {
-
- if(TMI->isStore(destNodeOpCode))
- memInst[srcIndex]->addOutEdge(memInst[destIndex],
- MSchedGraphSBEdge::MemoryDep,
- MSchedGraphSBEdge::AntiDep, 0);
- }
- else if(TMI->isStore(srcNodeOpCode)) {
- if(TMI->isStore(destNodeOpCode))
- memInst[srcIndex]->addOutEdge(memInst[destIndex],
- MSchedGraphSBEdge::MemoryDep,
- MSchedGraphSBEdge::OutputDep, 0);
-
- else
- memInst[srcIndex]->addOutEdge(memInst[destIndex],
- MSchedGraphSBEdge::MemoryDep,
- MSchedGraphSBEdge::TrueDep, 0);
- }
+
+ //Get the machine opCode to determine type of memory instruction
+ MachineOpCode destNodeOpCode = destInst->getOpcode();
+
+ //Get the Value* that we are reading from the load, always the first op
+ const MachineOperand &mOp = srcInst->getOperand(0);
+ const MachineOperand &mOp2 = destInst->getOperand(0);
+
+ if(mOp.hasAllocatedReg())
+ if(mOp.getReg() == SparcV9::g0)
+ continue;
+ if(mOp2.hasAllocatedReg())
+ if(mOp2.getReg() == SparcV9::g0)
+ continue;
+
+ DEBUG(std::cerr << "Adding dependence for machine instructions\n");
+ //Load-Store deps
+ if(TMI->isLoad(srcNodeOpCode)) {
+
+ if(TMI->isStore(destNodeOpCode))
+ memInst[srcIndex]->addOutEdge(memInst[destIndex],
+ MSchedGraphSBEdge::MemoryDep,
+ MSchedGraphSBEdge::AntiDep, 0);
+ }
+ else if(TMI->isStore(srcNodeOpCode)) {
+ if(TMI->isStore(destNodeOpCode))
+ memInst[srcIndex]->addOutEdge(memInst[destIndex],
+ MSchedGraphSBEdge::MemoryDep,
+ MSchedGraphSBEdge::OutputDep, 0);
+
+ else
+ memInst[srcIndex]->addOutEdge(memInst[destIndex],
+ MSchedGraphSBEdge::MemoryDep,
+ MSchedGraphSBEdge::TrueDep, 0);
+ }
}
}
}
private:
friend class MSchedGraphSBNode;
MSchedGraphSBEdge(MSchedGraphSBNode *destination, MSchedGraphSBEdgeType type,
- unsigned deptype, unsigned diff)
+ unsigned deptype, unsigned diff)
: dest(destination), depType(type), depOrderType(deptype), iteDiff(diff) {}
MSchedGraphSBNode *dest;
public:
MSchedGraphSBNode(const MachineInstr* inst, MSchedGraphSB *graph,
- unsigned index, unsigned late=0, bool isBranch=false);
- MSchedGraphSBNode(const MachineInstr* inst, std::vector<const MachineInstr*> &other,
- MSchedGraphSB *graph,
- unsigned index, unsigned late=0, bool isPNode=true);
+ unsigned index, unsigned late=0, bool isBranch=false);
+ MSchedGraphSBNode(const MachineInstr* inst, std::vector<const MachineInstr*> &other,
+ MSchedGraphSB *graph,
+ unsigned index, unsigned late=0, bool isPNode=true);
MSchedGraphSBNode(const MSchedGraphSBNode &N);
//Iterators - Predecessor and Succussor
pred_const_iterator pred_end() const { return Predecessors.end(); }
typedef MSchedGraphSBNodeIterator<std::vector<MSchedGraphSBEdge>::const_iterator,
- const MSchedGraphSBNode> succ_const_iterator;
+ const MSchedGraphSBNode> succ_const_iterator;
succ_const_iterator succ_begin() const;
succ_const_iterator succ_end() const;
typedef MSchedGraphSBNodeIterator<std::vector<MSchedGraphSBEdge>::iterator,
- MSchedGraphSBNode> succ_iterator;
+ MSchedGraphSBNode> succ_iterator;
succ_iterator succ_begin();
succ_iterator succ_end();
unsigned succ_size() { return Successors.size(); }
void deleteSuccessor(MSchedGraphSBNode *node) {
for (unsigned i = 0; i != Successors.size(); ++i)
- if (Successors[i].getDest() == node) {
- Successors.erase(Successors.begin()+i);
- node->Predecessors.erase(std::find(node->Predecessors.begin(),
- node->Predecessors.end(), this));
- --i; //Decrease index var since we deleted a node
- }
+ if (Successors[i].getDest() == node) {
+ Successors.erase(Successors.begin()+i);
+ node->Predecessors.erase(std::find(node->Predecessors.begin(),
+ node->Predecessors.end(), this));
+ --i; //Decrease index var since we deleted a node
+ }
}
void addOutEdge(MSchedGraphSBNode *destination,
- MSchedGraphSBEdge::MSchedGraphSBEdgeType type,
- unsigned deptype, unsigned diff=0) {
+ MSchedGraphSBEdge::MSchedGraphSBEdgeType type,
+ unsigned deptype, unsigned diff=0) {
Successors.push_back(MSchedGraphSBEdge(destination, type, deptype,diff));
destination->Predecessors.push_back(this);
}
// ostream << operator for MSGraphNode class
inline std::ostream &operator<<(std::ostream &os,
- const MSchedGraphSBNode &node) {
+ const MSchedGraphSBNode &node) {
node.print(os);
return os;
}
typedef std::pair<int, MSchedGraphSBNode*> OpIndexNodePair;
void buildNodesAndEdges(std::map<const MachineInstr*, unsigned> &ignoreInstrs, DependenceAnalyzer &DA, std::map<MachineInstr*, Instruction*> &machineTollvm, std::map<MSchedGraphSBNode*, std::set<MachineInstr*> > &liveOutsideTrace);
void addValueEdges(std::vector<OpIndexNodePair> &NodesInMap,
- MSchedGraphSBNode *node,
- bool nodeIsUse, bool nodeIsDef, std::vector<const MachineInstr*> &phiInstrs, int diff=0);
+ MSchedGraphSBNode *node,
+ bool nodeIsUse, bool nodeIsDef, std::vector<const MachineInstr*> &phiInstrs, int diff=0);
void addMachRegEdges(std::map<int,
- std::vector<OpIndexNodePair> >& regNumtoNodeMap);
+ std::vector<OpIndexNodePair> >& regNumtoNodeMap);
void addMemEdges(const std::vector<MSchedGraphSBNode*>& memInst,
- DependenceAnalyzer &DA, std::map<MachineInstr*, Instruction*> &machineTollvm);
-
+ DependenceAnalyzer &DA, std::map<MachineInstr*, Instruction*> &machineTollvm);
+
bool instrCauseException(MachineOpCode opCode);
public:
MSchedGraphSB(const MachineBasicBlock *bb, const TargetMachine &targ,
- std::map<const MachineInstr*, unsigned> &ignoreInstrs,
- DependenceAnalyzer &DA, std::map<MachineInstr*, Instruction*> &machineTollvm);
+ std::map<const MachineInstr*, unsigned> &ignoreInstrs,
+ DependenceAnalyzer &DA, std::map<MachineInstr*, Instruction*> &machineTollvm);
//Copy constructor with maps to link old nodes to new nodes
MSchedGraphSB(const MSchedGraphSB &G, std::map<MSchedGraphSBNode*, MSchedGraphSBNode*> &newNodes);
-
- MSchedGraphSB(std::vector<const MachineBasicBlock*> &bbs,
- const TargetMachine &targ,
- std::map<const MachineInstr*, unsigned> &ignoreInstrs,
- DependenceAnalyzer &DA,
- std::map<MachineInstr*, Instruction*> &machineTollvm);
+
+ MSchedGraphSB(std::vector<const MachineBasicBlock*> &bbs,
+ const TargetMachine &targ,
+ std::map<const MachineInstr*, unsigned> &ignoreInstrs,
+ DependenceAnalyzer &DA,
+ std::map<MachineInstr*, Instruction*> &machineTollvm);
//Print graph
void print(std::ostream &os) const;
// Provide specializations of GraphTraits to be able to use graph
// iterators on the scheduling graph
static MSchedGraphSBNode& getSecond(std::pair<const MachineInstr* const,
- MSchedGraphSBNode*> &Pair) {
+ MSchedGraphSBNode*> &Pair) {
return *Pair.second;
}
return N->succ_end();
}
typedef std::pointer_to_unary_function<std::pair<const MachineInstr* const,
- MSchedGraphSBNode*>&, MSchedGraphSBNode&> DerefFun;
+ MSchedGraphSBNode*>&, MSchedGraphSBNode&> DerefFun;
typedef mapped_iterator<MSchedGraphSB::iterator, DerefFun> nodes_iterator;
static nodes_iterator nodes_begin(MSchedGraphSB *G) {
}
typedef std::pointer_to_unary_function<std::pair<const MachineInstr* const,
- MSchedGraphSBNode*>&, MSchedGraphSBNode&> DerefFun;
+ MSchedGraphSBNode*>&, MSchedGraphSBNode&> DerefFun;
typedef mapped_iterator<MSchedGraphSB::iterator, DerefFun> nodes_iterator;
static nodes_iterator nodes_begin(MSchedGraphSB *G) {
static std::string getNodeLabel(MSchedGraphNode *Node, MSchedGraph *Graph) {
if (Node->getInst()) {
- std::stringstream ss;
- ss << *(Node->getInst());
- return ss.str(); //((MachineInstr*)Node->getInst());
+ std::stringstream ss;
+ ss << *(Node->getInst());
+ return ss.str(); //((MachineInstr*)Node->getInst());
}
else
- return "No Inst";
+ return "No Inst";
}
static std::string getEdgeSourceLabel(MSchedGraphNode *Node,
- MSchedGraphNode::succ_iterator I) {
+ MSchedGraphNode::succ_iterator I) {
//Label each edge with the type of dependence
std::string edgelabel = "";
switch (I.getEdge().getDepOrderType()) {
-
+
case MSchedGraphEdge::TrueDep:
- edgelabel = "True";
- break;
+ edgelabel = "True";
+ break;
case MSchedGraphEdge::AntiDep:
- edgelabel = "Anti";
- break;
-
+ edgelabel = "Anti";
+ break;
+
case MSchedGraphEdge::OutputDep:
- edgelabel = "Output";
- break;
-
+ edgelabel = "Output";
+ break;
+
default:
- edgelabel = "Unknown";
- break;
+ edgelabel = "Unknown";
+ break;
}
//FIXME
for (MachineFunction::iterator BI = MF.begin(); BI != MF.end(); ++BI)
if(MachineBBisValid(BI)) {
if(BI->size() < 100) {
- Worklist.push_back(&*BI);
- ++ValidLoops;
+ Worklist.push_back(&*BI);
+ ++ValidLoops;
}
else
- ++JumboBB;
+ ++JumboBB;
}
//Iterate over the worklist and perform scheduling
for(std::vector<MachineBasicBlock*>::iterator BI = Worklist.begin(),
- BE = Worklist.end(); BI != BE; ++BI) {
+ BE = Worklist.end(); BI != BE; ++BI) {
//Print out BB for debugging
DEBUG(std::cerr << "BB Size: " << (*BI)->size() << "\n");
//Dump node properties if in debug mode
DEBUG(for(std::map<MSchedGraphNode*, MSNodeAttributes>::iterator I = nodeToAttributesMap.begin(),
- E = nodeToAttributesMap.end(); I !=E; ++I) {
- std::cerr << "Node: " << *(I->first) << " ASAP: " << I->second.ASAP << " ALAP: "
- << I->second.ALAP << " MOB: " << I->second.MOB << " Depth: " << I->second.depth
- << " Height: " << I->second.height << "\n";
- });
+ E = nodeToAttributesMap.end(); I !=E; ++I) {
+ std::cerr << "Node: " << *(I->first) << " ASAP: " << I->second.ASAP << " ALAP: "
+ << I->second.ALAP << " MOB: " << I->second.MOB << " Depth: " << I->second.depth
+ << " Height: " << I->second.height << "\n";
+ });
//Calculate Node Properties
calculateNodeAttributes(MSG, ResMII);
//Dump node properties if in debug mode
DEBUG(for(std::map<MSchedGraphNode*, MSNodeAttributes>::iterator I = nodeToAttributesMap.begin(),
- E = nodeToAttributesMap.end(); I !=E; ++I) {
- std::cerr << "Node: " << *(I->first) << " ASAP: " << I->second.ASAP << " ALAP: "
- << I->second.ALAP << " MOB: " << I->second.MOB << " Depth: " << I->second.depth
- << " Height: " << I->second.height << "\n";
- });
+ E = nodeToAttributesMap.end(); I !=E; ++I) {
+ std::cerr << "Node: " << *(I->first) << " ASAP: " << I->second.ASAP << " ALAP: "
+ << I->second.ALAP << " MOB: " << I->second.MOB << " Depth: " << I->second.depth
+ << " Height: " << I->second.height << "\n";
+ });
//Put nodes in order to schedule them
computePartialOrder();
//Dump out partial order
DEBUG(for(std::vector<std::set<MSchedGraphNode*> >::iterator I = partialOrder.begin(),
- E = partialOrder.end(); I !=E; ++I) {
- std::cerr << "Start set in PO\n";
- for(std::set<MSchedGraphNode*>::iterator J = I->begin(), JE = I->end(); J != JE; ++J)
- std::cerr << "PO:" << **J << "\n";
- });
+ E = partialOrder.end(); I !=E; ++I) {
+ std::cerr << "Start set in PO\n";
+ for(std::set<MSchedGraphNode*>::iterator J = I->begin(), JE = I->end(); J != JE; ++J)
+ std::cerr << "PO:" << **J << "\n";
+ });
//Place nodes in final order
orderNodes();
//Dump out order of nodes
DEBUG(for(std::vector<MSchedGraphNode*>::iterator I = FinalNodeOrder.begin(), E = FinalNodeOrder.end(); I != E; ++I) {
- std::cerr << "FO:" << **I << "\n";
- });
+ std::cerr << "FO:" << **I << "\n";
+ });
//Finally schedule nodes
bool haveSched = computeSchedule(*BI, MSG);
IISum += mII;
if(schedule.getMaxStage() == 0)
- ++SameStage;
+ ++SameStage;
}
else {
++NoSched;
for(unsigned opNum = 0; opNum < I->getNumOperands(); ++opNum) {
const MachineOperand &mOp = I->getOperand(opNum);
if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef()) {
- //assert if this is the second def we have seen
- //DEBUG(std::cerr << "Putting " << *(mOp.getVRegValue()) << " into map\n");
- //assert(!defMap.count(mOp.getVRegValue()) && "Def already in the map");
- if(defMap.count(mOp.getVRegValue()))
- return false;
+ //assert if this is the second def we have seen
+ //DEBUG(std::cerr << "Putting " << *(mOp.getVRegValue()) << " into map\n");
+ //assert(!defMap.count(mOp.getVRegValue()) && "Def already in the map");
+ if(defMap.count(mOp.getVRegValue()))
+ return false;
- defMap[mOp.getVRegValue()] = &*I;
+ defMap[mOp.getVRegValue()] = &*I;
}
//See if we can use this Value* as our defaultInst
if(!defaultInst && mOp.getType() == MachineOperand::MO_VirtualRegister) {
- Value *V = mOp.getVRegValue();
- if(!isa<TmpInstruction>(V) && !isa<Argument>(V) && !isa<Constant>(V) && !isa<PHINode>(V))
- defaultInst = (Instruction*) V;
+ Value *V = mOp.getVRegValue();
+
if(!isa<TmpInstruction>(V) && !isa<Argument>(V) && !isa<Constant>(V) && !isa<PHINode>(V))
+ defaultInst = (Instruction*) V;
}
}
}
//Check first if its a valid loop
for(succ_const_iterator I = succ_begin(BI->getBasicBlock()),
- E = succ_end(BI->getBasicBlock()); I != E; ++I) {
+ E = succ_end(BI->getBasicBlock()); I != E; ++I) {
if (*I == BI->getBasicBlock()) // has single block loop
isLoop = true;
}
if(Instruction *I = dyn_cast<Instruction>(cond))
if(I->getParent() == BB) {
if (!assocIndVar(I, indVar, stack, BB)) {
- ++InvalidLoops;
- return false;
+ ++InvalidLoops;
+ return false;
}
}
else {
//Dump out instructions associate with indvar for debug reasons
DEBUG(for(std::set<Instruction*>::iterator N = indVar.begin(), NE = indVar.end(); N != NE; ++N) {
- std::cerr << **N << "\n";
- });
+ std::cerr << **N << "\n";
+ });
//Create map of machine instr to llvm instr
std::map<MachineInstr*, Instruction*> mllvm;
for (unsigned j = 0; j < tempMvec.size(); j++) {
MachineOpCode OC = (tempMvec[j])->getOpcode();
if(TMI->isNop(OC))
- continue;
+ continue;
if(!indexMap.count(tempMvec[j]))
- continue;
+ continue;
mIndVar[(MachineInstr*) tempMvec[j]] = indexMap[(MachineInstr*) tempMvec[j]];
DEBUG(std::cerr << *(tempMvec[j]) << " at index " << indexMap[(MachineInstr*) tempMvec[j]] << "\n");
}
}
bool ModuloSchedulingPass::assocIndVar(Instruction *I, std::set<Instruction*> &indVar,
- std::vector<Instruction*> &stack, BasicBlock *BB) {
+ std::vector<Instruction*> &stack, BasicBlock *BB) {
stack.push_back(I);
if (Inc->getOpcode() == Instruction::Add && Inc->getOperand(0) == PN)
if (ConstantInt *CI = dyn_cast<ConstantInt>(Inc->getOperand(1)))
if (CI->equalsInt(1)) {
- //We have found the indvar, so add the stack, and inc instruction to the set
- indVar.insert(stack.begin(), stack.end());
- indVar.insert(Inc);
- stack.pop_back();
- return true;
- }
+ //We have found the indvar, so add the stack, and inc instruction to the set
+ indVar.insert(stack.begin(), stack.end());
+ indVar.insert(Inc);
+ stack.pop_back();
+ return true;
+ }
return false;
}
else {
//Loop over each of the instructions operands, check if they are an instruction and in this BB
for(unsigned i = 0; i < I->getNumOperands(); ++i) {
if(Instruction *N = dyn_cast<Instruction>(I->getOperand(i))) {
- if(N->getParent() == BB)
- if(!assocIndVar(N, indVar, stack, BB))
- return false;
+ if(N->getParent() == BB)
+ if(!assocIndVar(N, indVar, stack, BB))
+ return false;
}
}
}
//Loop over resources in each cycle and increments their usage count
for(unsigned i=0; i < resources.size(); ++i)
for(unsigned j=0; j < resources[i].size(); ++j) {
- if(!resourceUsageCount.count(resources[i][j])) {
- resourceUsageCount[resources[i][j]] = 1;
- }
- else {
- resourceUsageCount[resources[i][j]] = resourceUsageCount[resources[i][j]] + 1;
- }
+ if(!resourceUsageCount.count(resources[i][j])) {
+ resourceUsageCount[resources[i][j]] = 1;
+ }
+ else {
+ resourceUsageCount[resources[i][j]] = resourceUsageCount[resources[i][j]] + 1;
+ }
}
}
//Assert if its already in the map
assert(nodeToAttributesMap.count(I->second) == 0 &&
- "Node attributes are already in the map");
+ "Node attributes are already in the map");
//Put into the map with default attribute values
nodeToAttributesMap[I->second] = MSNodeAttributes();
int ModuloSchedulingPass::calculateALAP(MSchedGraphNode *node, int MII,
- int maxASAP, MSchedGraphNode *srcNode) {
+ int maxASAP, MSchedGraphNode *srcNode) {
DEBUG(std::cerr << "Calculating ALAP for " << *node << "\n");
//Iterate over all of the predecessors and fine max
for(MSchedGraphNode::succ_iterator P = node->succ_begin(),
- E = node->succ_end(); P != E; ++P) {
+ E = node->succ_end(); P != E; ++P) {
//Only process if we are not ignoring the edge
if(!ignoreEdge(node, *P)) {
- processedOneEdge = true;
- int succALAP = -1;
- succALAP = calculateALAP(*P, MII, maxASAP, node);
-
- assert(succALAP != -1 && "Successors ALAP should have been caclulated");
-
- int iteDiff = P.getEdge().getIteDiff();
-
- int currentSuccValue = succALAP - node->getLatency() + iteDiff * MII;
-
- DEBUG(std::cerr << "succ ALAP: " << succALAP << ", iteDiff: " << iteDiff << ", SuccLatency: " << (*P)->getLatency() << ", Current ALAP succ: " << currentSuccValue << "\n");
-
- minSuccValue = std::min(minSuccValue, currentSuccValue);
+ processedOneEdge = true;
+ int succALAP = -1;
+ succALAP = calculateALAP(*P, MII, maxASAP, node);
+
+ assert(succALAP != -1 && "Successors ALAP should have been caclulated");
+
+ int iteDiff = P.getEdge().getIteDiff();
+
+ int currentSuccValue = succALAP - node->getLatency() + iteDiff * MII;
+
+ DEBUG(std::cerr << "succ ALAP: " << succALAP << ", iteDiff: " << iteDiff << ", SuccLatency: " << (*P)->getLatency() << ", Current ALAP succ: " << currentSuccValue << "\n");
+
+ minSuccValue = std::min(minSuccValue, currentSuccValue);
}
}
if(processedOneEdge)
- attributes.ALAP = minSuccValue;
+ attributes.ALAP = minSuccValue;
else
attributes.ALAP = maxASAP;
int maxASAP = 0;
for(std::map<MSchedGraphNode*, MSNodeAttributes>::iterator I = nodeToAttributesMap.begin(),
- E = nodeToAttributesMap.end(); I != E; ++I)
+ E = nodeToAttributesMap.end(); I != E; ++I)
maxASAP = std::max(maxASAP, I->second.ASAP);
return maxASAP;
}
//Iterate over all of the predecessors and find max
for(MSchedGraphNode::succ_iterator P = node->succ_begin(),
- E = node->succ_end(); P != E; ++P) {
+ E = node->succ_end(); P != E; ++P) {
if(!ignoreEdge(node, *P)) {
int ModuloSchedulingPass::calculateDepth(MSchedGraphNode *node,
- MSchedGraphNode *destNode) {
+ MSchedGraphNode *destNode) {
MSNodeAttributes &attributes = nodeToAttributesMap.find(node)->second;
if(R->second.size() == recurrence.size()) {
for(std::vector<MSchedGraphNode*>::const_iterator node = R->second.begin(), end = R->second.end(); node != end; ++node) {
- if(std::find(recurrence.begin(), recurrence.end(), *node) == recurrence.end()) {
- all_same = all_same && false;
- break;
- }
- else
- all_same = all_same && true;
+ if(std::find(recurrence.begin(), recurrence.end(), *node) == recurrence.end()) {
+ all_same = all_same && false;
+ break;
+ }
+ else
+ all_same = all_same && true;
}
if(all_same) {
- same = true;
- break;
+ same = true;
+ break;
}
}
}
//DEBUG(std::cerr << "NOT A BACKEDGE\n");
//find actual backedge HACK HACK
for(unsigned i=0; i< recurrence.size()-1; ++i) {
- if(recurrence[i+1]->getInEdge(recurrence[i]).getIteDiff() == 1) {
- srcBENode = recurrence[i];
- destBENode = recurrence[i+1];
- break;
- }
-
+ if(recurrence[i+1]->getInEdge(recurrence[i]).getIteDiff() == 1) {
+ srcBENode = recurrence[i];
+ destBENode = recurrence[i+1];
+ break;
+ }
+
}
}
int CircCount;
void ModuloSchedulingPass::unblock(MSchedGraphNode *u, std::set<MSchedGraphNode*> &blocked,
- std::map<MSchedGraphNode*, std::set<MSchedGraphNode*> > &B) {
+ std::map<MSchedGraphNode*, std::set<MSchedGraphNode*> > &B) {
//Unblock u
DEBUG(std::cerr << "Unblocking: " << *u << "\n");
}
bool ModuloSchedulingPass::circuit(MSchedGraphNode *v, std::vector<MSchedGraphNode*> &stack,
- std::set<MSchedGraphNode*> &blocked, std::vector<MSchedGraphNode*> &SCC,
- MSchedGraphNode *s, std::map<MSchedGraphNode*, std::set<MSchedGraphNode*> > &B,
- int II, std::map<MSchedGraphNode*, MSchedGraphNode*> &newNodes) {
+ std::set<MSchedGraphNode*> &blocked, std::vector<MSchedGraphNode*> &SCC,
+ MSchedGraphNode *s, std::map<MSchedGraphNode*, std::set<MSchedGraphNode*> > &B,
+ int II, std::map<MSchedGraphNode*, MSchedGraphNode*> &newNodes) {
bool f = false;
DEBUG(std::cerr << "Finding Circuits Starting with: ( " << v << ")"<< *v << "\n");
}
else if(!blocked.count(*I)) {
if(circuit(*I, stack, blocked, SCC, s, B, II, newNodes))
- f = true;
+ f = true;
}
else
DEBUG(std::cerr << "Blocked: " << **I << "\n");
std::vector<MSchedGraphNode*> recc;
//Dump recurrence for now
DEBUG(std::cerr << "Starting Recc\n");
-
+
int totalDelay = 0;
int totalDistance = 0;
MSchedGraphNode *lastN = 0;
totalDistance += iteDiff;
if(iteDiff > 0) {
- start = lastN;
- end = *N;
+ start = lastN;
+ end = *N;
}
}
//Get the original node
DEBUG(std::cerr << "End Recc\n");
CircCount++;
- if(start && end) {
+ if(start && end) {
//Insert reccurrence into the list
DEBUG(std::cerr << "Ignore Edge from!!: " << *start << " to " << *end << "\n");
edgesToIgnore.insert(std::make_pair(newNodes[start], (newNodes[end])->getInEdgeNum(newNodes[start])));
int value = totalDelay-(RecMII * totalDistance);
int lastII = II;
while(value < 0) {
-
+
lastII = RecMII;
RecMII--;
value = totalDelay-(RecMII * totalDistance);
for(unsigned i = 0; i < (*N)->succ_size(); ++i) {
MSchedGraphEdge *edge = (*N)->getSuccessor(i);
if(find(SCC.begin(), SCC.end(), edge->getDest()) != SCC.end()) {
- totalDistance += edge->getIteDiff();
- if(edge->getIteDiff() > 0)
- if(!start && !end) {
- start = *N;
- end = edge->getDest();
- }
-
+ totalDistance += edge->getIteDiff();
+ if(edge->getIteDiff() > 0)
+ if(!start && !end) {
+ start = *N;
+ end = edge->getDest();
+ }
+
}
}
assert( (start && end) && "Must have start and end node to ignore edge for SCC");
- if(start && end) {
+ if(start && end) {
//Insert reccurrence into the list
DEBUG(std::cerr << "Ignore Edge from!!: " << *start << " to " << *end << "\n");
edgesToIgnore.insert(std::make_pair(newNodes[start], (newNodes[end])->getInEdgeNum(newNodes[start])));
//Find scc with the least vertex
for (MSchedGraph::iterator GI = MSG->begin(), E = MSG->end(); GI != E; ++GI)
if (Visited.insert(GI->second).second) {
- for (scc_iterator<MSchedGraphNode*> SCCI = scc_begin(GI->second),
- E = scc_end(GI->second); SCCI != E; ++SCCI) {
- std::vector<MSchedGraphNode*> &nextSCC = *SCCI;
-
- if (Visited.insert(nextSCC[0]).second) {
- Visited.insert(nextSCC.begin()+1, nextSCC.end());
-
- if(nextSCC.size() > 1) {
- std::cerr << "SCC size: " << nextSCC.size() << "\n";
-
- for(unsigned i = 0; i < nextSCC.size(); ++i) {
- //Loop over successor and see if in scc, then count edge
- MSchedGraphNode *node = nextSCC[i];
- for(MSchedGraphNode::succ_iterator S = node->succ_begin(), SE = node->succ_end(); S != SE; ++S) {
- if(find(nextSCC.begin(), nextSCC.end(), *S) != nextSCC.end())
- numEdges++;
- }
- }
- std::cerr << "Num Edges: " << numEdges << "\n";
- }
-
- //Ignore self loops
- if(nextSCC.size() > 1) {
-
- //Get least vertex in Vk
- if(!s) {
- s = nextSCC[0];
- Vk = nextSCC;
- }
-
- for(unsigned i = 0; i < nextSCC.size(); ++i) {
- if(nextSCC[i] < s) {
- s = nextSCC[i];
- Vk = nextSCC;
- }
- }
- }
- }
- }
+ for (scc_iterator<MSchedGraphNode*> SCCI = scc_begin(GI->second),
+ E = scc_end(GI->second); SCCI != E; ++SCCI) {
+ std::vector<MSchedGraphNode*> &nextSCC = *SCCI;
+
+ if (Visited.insert(nextSCC[0]).second) {
+ Visited.insert(nextSCC.begin()+1, nextSCC.end());
+
+ if(nextSCC.size() > 1) {
+ std::cerr << "SCC size: " << nextSCC.size() << "\n";
+
+ for(unsigned i = 0; i < nextSCC.size(); ++i) {
+ //Loop over successor and see if in scc, then count edge
+ MSchedGraphNode *node = nextSCC[i];
+ for(MSchedGraphNode::succ_iterator S = node->succ_begin(), SE = node->succ_end(); S != SE; ++S) {
+ if(find(nextSCC.begin(), nextSCC.end(), *S) != nextSCC.end())
+ numEdges++;
+ }
+ }
+ std::cerr << "Num Edges: " << numEdges << "\n";
+ }
+
+ //Ignore self loops
+ if(nextSCC.size() > 1) {
+
+ //Get least vertex in Vk
+ if(!s) {
+ s = nextSCC[0];
+ Vk = nextSCC;
+ }
+
+ for(unsigned i = 0; i < nextSCC.size(); ++i) {
+ if(nextSCC[i] < s) {
+ s = nextSCC[i];
+ Vk = nextSCC;
+ }
+ }
+ }
+ }
+ }
}
//Process SCC
DEBUG(for(std::vector<MSchedGraphNode*>::iterator N = Vk.begin(), NE = Vk.end();
- N != NE; ++N) { std::cerr << *((*N)->getInst()); });
+ N != NE; ++N) { std::cerr << *((*N)->getInst()); });
//Iterate over all nodes in this scc
for(std::vector<MSchedGraphNode*>::iterator N = Vk.begin(), NE = Vk.end();
- N != NE; ++N) {
+ N != NE; ++N) {
blocked.erase(*N);
B[*N].clear();
}
if(Vk.size() > 1) {
if(numEdges < 98)
- circuit(s, stack, blocked, Vk, s, B, II, newNodes);
+ circuit(s, stack, blocked, Vk, s, B, II, newNodes);
else
- addSCC(Vk, newNodes);
+ addSCC(Vk, newNodes);
//Delete nodes from the graph
//Find all nodes up to s and delete them
std::vector<MSchedGraphNode*> nodesToRemove;
nodesToRemove.push_back(s);
for(MSchedGraph::iterator N = MSG->begin(), NE = MSG->end(); N != NE; ++N) {
- if(N->second < s )
- nodesToRemove.push_back(N->second);
+ if(N->second < s )
+ nodesToRemove.push_back(N->second);
}
for(std::vector<MSchedGraphNode*>::iterator N = nodesToRemove.begin(), NE = nodesToRemove.end(); N != NE; ++N) {
- DEBUG(std::cerr << "Deleting Node: " << **N << "\n");
- MSG->deleteNode(*N);
+ DEBUG(std::cerr << "Deleting Node: " << **N << "\n");
+ MSG->deleteNode(*N);
}
}
else
void ModuloSchedulingPass::findAllReccurrences(MSchedGraphNode *node,
- std::vector<MSchedGraphNode*> &visitedNodes,
- int II) {
+ std::vector<MSchedGraphNode*> &visitedNodes,
+ int II) {
if(std::find(visitedNodes.begin(), visitedNodes.end(), node) != visitedNodes.end()) {
for(std::vector<MSchedGraphNode*>::iterator I = visitedNodes.begin(), E = visitedNodes.end();
- I !=E; ++I) {
+ I !=E; ++I) {
if(*I == node)
- first = false;
+ first = false;
if(first)
- continue;
+ continue;
delay = delay + (*I)->getLatency();
if(*I != node) {
- int diff = (*I)->getInEdge(last).getIteDiff();
- distance += diff;
- if(diff > 0) {
- srcBackEdge = last;
- destBackEdge = *I;
- }
+ int diff = (*I)->getInEdge(last).getIteDiff();
+ distance += diff;
+ if(diff > 0) {
+ srcBackEdge = last;
+ destBackEdge = *I;
+ }
}
recurrence.push_back(*I);
}
void ModuloSchedulingPass::searchPath(MSchedGraphNode *node,
- std::vector<MSchedGraphNode*> &path,
- std::set<MSchedGraphNode*> &nodesToAdd,
- std::set<MSchedGraphNode*> &new_reccurrence) {
+ std::vector<MSchedGraphNode*> &path,
+ std::set<MSchedGraphNode*> &nodesToAdd,
+ std::set<MSchedGraphNode*> &new_reccurrence) {
//Push node onto the path
path.push_back(node);
//final vector
bool found = false;
for(std::vector<std::set<MSchedGraphNode*> >::iterator PO = partialOrder.begin(),
- PE = partialOrder.end(); PO != PE; ++PO) {
+ PE = partialOrder.end(); PO != PE; ++PO) {
if(PO->count(*S)) {
- found = true;
- break;
+ found = true;
+ break;
}
}
}
void ModuloSchedulingPass::pathToRecc(MSchedGraphNode *node,
- std::vector<MSchedGraphNode*> &path,
- std::set<MSchedGraphNode*> &poSet,
- std::set<MSchedGraphNode*> &lastNodes) {
+ std::vector<MSchedGraphNode*> &path,
+ std::set<MSchedGraphNode*> &poSet,
+ std::set<MSchedGraphNode*> &lastNodes) {
//Push node onto the path
path.push_back(node);
DEBUG(std::cerr << "Found path to recc from no pred\n");
//Loop over path, if it exists in lastNodes, then add to poset, and remove from lastNodes
for(std::vector<MSchedGraphNode*>::iterator I = path.begin(), IE = path.end(); I != IE; ++I) {
- if(lastNodes.count(*I)) {
- DEBUG(std::cerr << "Inserting node into recc: " << **I << "\n");
- poSet.insert(*I);
- lastNodes.erase(*I);
- }
+ if(lastNodes.count(*I)) {
+ DEBUG(std::cerr << "Inserting node into recc: " << **I << "\n");
+ poSet.insert(*I);
+ lastNodes.erase(*I);
+ }
}
}
else
//along with any nodes that connect this recurrence to recurrences
//already in the partial order
for(std::set<std::pair<int, std::vector<MSchedGraphNode*> > >::reverse_iterator
- I = recurrenceList.rbegin(), E=recurrenceList.rend(); I !=E; ++I) {
+ I = recurrenceList.rbegin(), E=recurrenceList.rend(); I !=E; ++I) {
std::set<MSchedGraphNode*> new_recurrence;
//Loop through recurrence and remove any nodes already in the partial order
for(std::vector<MSchedGraphNode*>::const_iterator N = I->second.begin(),
- NE = I->second.end(); N != NE; ++N) {
+ NE = I->second.end(); N != NE; ++N) {
bool found = false;
for(std::vector<std::set<MSchedGraphNode*> >::iterator PO = partialOrder.begin(),
- PE = partialOrder.end(); PO != PE; ++PO) {
- if(PO->count(*N))
- found = true;
+ PE = partialOrder.end(); PO != PE; ++PO) {
+ if(PO->count(*N))
+ found = true;
}
//Check if its a branch, and remove to handle special
if(!found) {
- if((*N)->isBranch() && !(*N)->hasPredecessors()) {
- branches.push_back(*N);
- }
- else
- new_recurrence.insert(*N);
+ if((*N)->isBranch() && !(*N)->hasPredecessors()) {
+ branches.push_back(*N);
+ }
+ else
+ new_recurrence.insert(*N);
}
}
//Add nodes that connect this recurrence to recurrences in the partial path
for(std::set<MSchedGraphNode*>::iterator N = new_recurrence.begin(),
NE = new_recurrence.end(); N != NE; ++N)
- searchPath(*N, path, nodesToAdd, new_recurrence);
+ searchPath(*N, path, nodesToAdd, new_recurrence);
//Add nodes to this recurrence if they are not already in the partial order
for(std::set<MSchedGraphNode*>::iterator N = nodesToAdd.begin(), NE = nodesToAdd.end();
- N != NE; ++N) {
- bool found = false;
- for(std::vector<std::set<MSchedGraphNode*> >::iterator PO = partialOrder.begin(),
- PE = partialOrder.end(); PO != PE; ++PO) {
- if(PO->count(*N))
- found = true;
- }
- if(!found) {
- assert("FOUND CONNECTOR");
- new_recurrence.insert(*N);
- }
+ N != NE; ++N) {
+ bool found = false;
+ for(std::vector<std::set<MSchedGraphNode*> >::iterator PO = partialOrder.begin(),
+ PE = partialOrder.end(); PO != PE; ++PO) {
+ if(PO->count(*N))
+ found = true;
+ }
+ if(!found) {
+ assert("FOUND CONNECTOR");
+ new_recurrence.insert(*N);
+ }
}
partialOrder.push_back(new_recurrence);
//Dump out partial order
DEBUG(for(std::vector<std::set<MSchedGraphNode*> >::iterator I = partialOrder.begin(),
- E = partialOrder.end(); I !=E; ++I) {
- std::cerr << "Start set in PO\n";
- for(std::set<MSchedGraphNode*>::iterator J = I->begin(), JE = I->end(); J != JE; ++J)
- std::cerr << "PO:" << **J << "\n";
- });
+ E = partialOrder.end(); I !=E; ++I) {
+ std::cerr << "Start set in PO\n";
+ for(std::set<MSchedGraphNode*>::iterator J = I->begin(), JE = I->end(); J != JE; ++J)
+ std::cerr << "PO:" << **J << "\n";
+ });
}
}
std::set<MSchedGraphNode*> lastNodes;
std::set<MSchedGraphNode*> noPredNodes;
for(std::map<MSchedGraphNode*, MSNodeAttributes>::iterator I = nodeToAttributesMap.begin(),
- E = nodeToAttributesMap.end(); I != E; ++I) {
+ E = nodeToAttributesMap.end(); I != E; ++I) {
bool found = false;
//Check if its already in our partial order, if not add it to the final vector
for(std::vector<std::set<MSchedGraphNode*> >::iterator PO = partialOrder.begin(),
- PE = partialOrder.end(); PO != PE; ++PO) {
+ PE = partialOrder.end(); PO != PE; ++PO) {
if(PO->count(I->first))
- found = true;
+ found = true;
}
if(!found)
lastNodes.insert(I->first);
N != NE; ++N) {
DEBUG(std::cerr << "No Pred Path from: " << **N << "\n");
for(std::vector<std::set<MSchedGraphNode*> >::iterator PO = partialOrder.begin(),
- PE = partialOrder.end(); PO != PE; ++PO) {
+ PE = partialOrder.end(); PO != PE; ++PO) {
std::vector<MSchedGraphNode*> path;
pathToRecc(*N, path, *PO, lastNodes);
}
std::set<MSchedGraphNode*> ccSet;
connectedComponentSet(*(lastNodes.begin()),ccSet, lastNodes);
if(ccSet.size() > 0)
- partialOrder.push_back(ccSet);
+ partialOrder.push_back(ccSet);
}
for(unsigned j=0; j < FinalNodeOrder.size(); ++j) {
for(MSchedGraphNode::pred_iterator P = FinalNodeOrder[j]->pred_begin(),
- E = FinalNodeOrder[j]->pred_end(); P != E; ++P) {
+ E = FinalNodeOrder[j]->pred_end(); P != E; ++P) {
//Check if we are supposed to ignore this edge or not
if(ignoreEdge(*P,FinalNodeOrder[j]))
- continue;
-
+ continue;
+
if(CurrentSet.count(*P))
- if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), *P) == FinalNodeOrder.end())
- IntersectResult.insert(*P);
+ if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), *P) == FinalNodeOrder.end())
+ IntersectResult.insert(*P);
}
}
}
for(unsigned j=0; j < FinalNodeOrder.size(); ++j) {
for(MSchedGraphNode::succ_iterator P = FinalNodeOrder[j]->succ_begin(),
- E = FinalNodeOrder[j]->succ_end(); P != E; ++P) {
+ E = FinalNodeOrder[j]->succ_end(); P != E; ++P) {
//Check if we are supposed to ignore this edge or not
if(ignoreEdge(FinalNodeOrder[j],*P))
- continue;
+ continue;
if(CurrentSet.count(*P))
- if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), *P) == FinalNodeOrder.end())
- IntersectResult.insert(*P);
+ if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), *P) == FinalNodeOrder.end())
+ IntersectResult.insert(*P);
}
}
}
//sort top-down
if(IntersectCurrent.size() != 0) {
- DEBUG(std::cerr << "Final Node Order Successors and Current Set interesection is NOT empty\n");
- order = TOP_DOWN;
+ DEBUG(std::cerr << "Final Node Order Successors and Current Set interesection is NOT empty\n");
+ order = TOP_DOWN;
}
else {
- DEBUG(std::cerr << "Final Node Order Successors and Current Set interesection is empty\n");
- //Find node with max ASAP in current Set
- MSchedGraphNode *node;
- int maxASAP = 0;
- DEBUG(std::cerr << "Using current set of size " << CurrentSet->size() << "to find max ASAP\n");
- for(std::set<MSchedGraphNode*>::iterator J = CurrentSet->begin(), JE = CurrentSet->end(); J != JE; ++J) {
- //Get node attributes
- MSNodeAttributes nodeAttr= nodeToAttributesMap.find(*J)->second;
- //assert(nodeAttr != nodeToAttributesMap.end() && "Node not in attributes map!");
-
- if(maxASAP <= nodeAttr.ASAP) {
- maxASAP = nodeAttr.ASAP;
- node = *J;
- }
- }
- assert(node != 0 && "In node ordering node should not be null");
- IntersectCurrent.insert(node);
- order = BOTTOM_UP;
+ DEBUG(std::cerr << "Final Node Order Successors and Current Set interesection is empty\n");
+ //Find node with max ASAP in current Set
+ MSchedGraphNode *node;
+ int maxASAP = 0;
+ DEBUG(std::cerr << "Using current set of size " << CurrentSet->size() << "to find max ASAP\n");
+ for(std::set<MSchedGraphNode*>::iterator J = CurrentSet->begin(), JE = CurrentSet->end(); J != JE; ++J) {
+ //Get node attributes
+ MSNodeAttributes nodeAttr= nodeToAttributesMap.find(*J)->second;
+ //assert(nodeAttr != nodeToAttributesMap.end() && "Node not in attributes map!");
+
+ if(maxASAP <= nodeAttr.ASAP) {
+ maxASAP = nodeAttr.ASAP;
+ node = *J;
+ }
+ }
+ assert(node != 0 && "In node ordering node should not be null");
+ IntersectCurrent.insert(node);
+ order = BOTTOM_UP;
}
}
while(IntersectCurrent.size() > 0) {
if(order == TOP_DOWN) {
- DEBUG(std::cerr << "Order is TOP DOWN\n");
-
- while(IntersectCurrent.size() > 0) {
- DEBUG(std::cerr << "Intersection is not empty, so find heighest height\n");
-
- int MOB = 0;
- int height = 0;
- MSchedGraphNode *highestHeightNode = *(IntersectCurrent.begin());
-
- //Find node in intersection with highest heigh and lowest MOB
- for(std::set<MSchedGraphNode*>::iterator I = IntersectCurrent.begin(),
- E = IntersectCurrent.end(); I != E; ++I) {
-
- //Get current nodes properties
- MSNodeAttributes nodeAttr= nodeToAttributesMap.find(*I)->second;
-
- if(height < nodeAttr.height) {
- highestHeightNode = *I;
- height = nodeAttr.height;
- MOB = nodeAttr.MOB;
- }
- else if(height == nodeAttr.height) {
- if(MOB > nodeAttr.height) {
- highestHeightNode = *I;
- height = nodeAttr.height;
- MOB = nodeAttr.MOB;
- }
- }
- }
-
- //Append our node with greatest height to the NodeOrder
- if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), highestHeightNode) == FinalNodeOrder.end()) {
- DEBUG(std::cerr << "Adding node to Final Order: " << *highestHeightNode << "\n");
- FinalNodeOrder.push_back(highestHeightNode);
- }
-
- //Remove V from IntersectOrder
- IntersectCurrent.erase(std::find(IntersectCurrent.begin(),
- IntersectCurrent.end(), highestHeightNode));
-
-
- //Intersect V's successors with CurrentSet
- for(MSchedGraphNode::succ_iterator P = highestHeightNode->succ_begin(),
- E = highestHeightNode->succ_end(); P != E; ++P) {
- //if(lower_bound(CurrentSet->begin(),
- // CurrentSet->end(), *P) != CurrentSet->end()) {
- if(std::find(CurrentSet->begin(), CurrentSet->end(), *P) != CurrentSet->end()) {
- if(ignoreEdge(highestHeightNode, *P))
- continue;
- //If not already in Intersect, add
- if(!IntersectCurrent.count(*P))
- IntersectCurrent.insert(*P);
- }
- }
- } //End while loop over Intersect Size
-
- //Change direction
- order = BOTTOM_UP;
-
- //Reset Intersect to reflect changes in OrderNodes
- IntersectCurrent.clear();
- predIntersect(*CurrentSet, IntersectCurrent);
-
+ DEBUG(std::cerr << "Order is TOP DOWN\n");
+
+ while(IntersectCurrent.size() > 0) {
+ DEBUG(std::cerr << "Intersection is not empty, so find heighest height\n");
+
+ int MOB = 0;
+ int height = 0;
+ MSchedGraphNode *highestHeightNode = *(IntersectCurrent.begin());
+
+ //Find node in intersection with highest heigh and lowest MOB
+ for(std::set<MSchedGraphNode*>::iterator I = IntersectCurrent.begin(),
+ E = IntersectCurrent.end(); I != E; ++I) {
+
+ //Get current nodes properties
+ MSNodeAttributes nodeAttr= nodeToAttributesMap.find(*I)->second;
+
+ if(height < nodeAttr.height) {
+ highestHeightNode = *I;
+ height = nodeAttr.height;
+ MOB = nodeAttr.MOB;
+ }
+ else if(height == nodeAttr.height) {
+ if(MOB > nodeAttr.height) {
+ highestHeightNode = *I;
+ height = nodeAttr.height;
+ MOB = nodeAttr.MOB;
+ }
+ }
+ }
+
+ //Append our node with greatest height to the NodeOrder
+ if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), highestHeightNode) == FinalNodeOrder.end()) {
+ DEBUG(std::cerr << "Adding node to Final Order: " << *highestHeightNode << "\n");
+ FinalNodeOrder.push_back(highestHeightNode);
+ }
+
+ //Remove V from IntersectOrder
+ IntersectCurrent.erase(std::find(IntersectCurrent.begin(),
+ IntersectCurrent.end(), highestHeightNode));
+
+
+ //Intersect V's successors with CurrentSet
+ for(MSchedGraphNode::succ_iterator P = highestHeightNode->succ_begin(),
+ E = highestHeightNode->succ_end(); P != E; ++P) {
+ //if(lower_bound(CurrentSet->begin(),
+ // CurrentSet->end(), *P) != CurrentSet->end()) {
+ if(std::find(CurrentSet->begin(), CurrentSet->end(), *P) != CurrentSet->end()) {
+ if(ignoreEdge(highestHeightNode, *P))
+ continue;
+ //If not already in Intersect, add
+ if(!IntersectCurrent.count(*P))
+ IntersectCurrent.insert(*P);
+ }
+ }
+ } //End while loop over Intersect Size
+
+ //Change direction
+ order = BOTTOM_UP;
+
+ //Reset Intersect to reflect changes in OrderNodes
+ IntersectCurrent.clear();
+ predIntersect(*CurrentSet, IntersectCurrent);
+
} //End If TOP_DOWN
-
- //Begin if BOTTOM_UP
+
+ //Begin if BOTTOM_UP
else {
- DEBUG(std::cerr << "Order is BOTTOM UP\n");
- while(IntersectCurrent.size() > 0) {
- DEBUG(std::cerr << "Intersection of size " << IntersectCurrent.size() << ", finding highest depth\n");
-
- //dump intersection
- DEBUG(dumpIntersection(IntersectCurrent));
- //Get node with highest depth, if a tie, use one with lowest
- //MOB
- int MOB = 0;
- int depth = 0;
- MSchedGraphNode *highestDepthNode = *(IntersectCurrent.begin());
-
- for(std::set<MSchedGraphNode*>::iterator I = IntersectCurrent.begin(),
- E = IntersectCurrent.end(); I != E; ++I) {
- //Find node attribute in graph
- MSNodeAttributes nodeAttr= nodeToAttributesMap.find(*I)->second;
-
- if(depth < nodeAttr.depth) {
- highestDepthNode = *I;
- depth = nodeAttr.depth;
- MOB = nodeAttr.MOB;
- }
- else if(depth == nodeAttr.depth) {
- if(MOB > nodeAttr.MOB) {
- highestDepthNode = *I;
- depth = nodeAttr.depth;
- MOB = nodeAttr.MOB;
- }
- }
- }
-
-
-
- //Append highest depth node to the NodeOrder
- if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), highestDepthNode) == FinalNodeOrder.end()) {
- DEBUG(std::cerr << "Adding node to Final Order: " << *highestDepthNode << "\n");
- FinalNodeOrder.push_back(highestDepthNode);
- }
- //Remove heightestDepthNode from IntersectOrder
- IntersectCurrent.erase(highestDepthNode);
-
-
- //Intersect heightDepthNode's pred with CurrentSet
- for(MSchedGraphNode::pred_iterator P = highestDepthNode->pred_begin(),
- E = highestDepthNode->pred_end(); P != E; ++P) {
- if(CurrentSet->count(*P)) {
- if(ignoreEdge(*P, highestDepthNode))
- continue;
-
- //If not already in Intersect, add
- if(!IntersectCurrent.count(*P))
- IntersectCurrent.insert(*P);
- }
- }
-
- } //End while loop over Intersect Size
-
- //Change order
- order = TOP_DOWN;
-
- //Reset IntersectCurrent to reflect changes in OrderNodes
- IntersectCurrent.clear();
- succIntersect(*CurrentSet, IntersectCurrent);
- } //End if BOTTOM_DOWN
-
+ DEBUG(std::cerr << "Order is BOTTOM UP\n");
+ while(IntersectCurrent.size() > 0) {
+ DEBUG(std::cerr << "Intersection of size " << IntersectCurrent.size() << ", finding highest depth\n");
+
+ //dump intersection
+ DEBUG(dumpIntersection(IntersectCurrent));
+ //Get node with highest depth, if a tie, use one with lowest
+ //MOB
+ int MOB = 0;
+ int depth = 0;
+ MSchedGraphNode *highestDepthNode = *(IntersectCurrent.begin());
+
+ for(std::set<MSchedGraphNode*>::iterator I = IntersectCurrent.begin(),
+ E = IntersectCurrent.end(); I != E; ++I) {
+ //Find node attribute in graph
+ MSNodeAttributes nodeAttr= nodeToAttributesMap.find(*I)->second;
+
+ if(depth < nodeAttr.depth) {
+ highestDepthNode = *I;
+ depth = nodeAttr.depth;
+ MOB = nodeAttr.MOB;
+ }
+ else if(depth == nodeAttr.depth) {
+ if(MOB > nodeAttr.MOB) {
+ highestDepthNode = *I;
+ depth = nodeAttr.depth;
+ MOB = nodeAttr.MOB;
+ }
+ }
+ }
+
+
+
+ //Append highest depth node to the NodeOrder
+ if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), highestDepthNode) == FinalNodeOrder.end()) {
+ DEBUG(std::cerr << "Adding node to Final Order: " << *highestDepthNode << "\n");
+ FinalNodeOrder.push_back(highestDepthNode);
+ }
+ //Remove heightestDepthNode from IntersectOrder
+ IntersectCurrent.erase(highestDepthNode);
+
+
+ //Intersect heightDepthNode's pred with CurrentSet
+ for(MSchedGraphNode::pred_iterator P = highestDepthNode->pred_begin(),
+ E = highestDepthNode->pred_end(); P != E; ++P) {
+ if(CurrentSet->count(*P)) {
+ if(ignoreEdge(*P, highestDepthNode))
+ continue;
+
+ //If not already in Intersect, add
+ if(!IntersectCurrent.count(*P))
+ IntersectCurrent.insert(*P);
+ }
+ }
+
+ } //End while loop over Intersect Size
+
+ //Change order
+ order = TOP_DOWN;
+
+ //Reset IntersectCurrent to reflect changes in OrderNodes
+ IntersectCurrent.clear();
+ succIntersect(*CurrentSet, IntersectCurrent);
+ } //End if BOTTOM_DOWN
+
DEBUG(std::cerr << "Current Intersection Size: " << IntersectCurrent.size() << "\n");
}
//End Wrapping while loop
//Loop over the final node order and process each node
for(std::vector<MSchedGraphNode*>::iterator I = FinalNodeOrder.begin(),
- E = FinalNodeOrder.end(); I != E; ++I) {
+ E = FinalNodeOrder.end(); I != E; ++I) {
//CalculateEarly and Late start
bool initialLSVal = false;
bool sched;
if((*I)->isBranch())
- if((*I)->hasPredecessors())
- sched = true;
- else
- sched = false;
+ if((*I)->hasPredecessors())
+ sched = true;
+ else
+ sched = false;
else
- sched = true;
+ sched = true;
if(sched) {
- //Loop over nodes in the schedule and determine if they are predecessors
- //or successors of the node we are trying to schedule
- for(MSSchedule::schedule_iterator nodesByCycle = schedule.begin(), nodesByCycleEnd = schedule.end();
- nodesByCycle != nodesByCycleEnd; ++nodesByCycle) {
-
- //For this cycle, get the vector of nodes schedule and loop over it
- for(std::vector<MSchedGraphNode*>::iterator schedNode = nodesByCycle->second.begin(), SNE = nodesByCycle->second.end(); schedNode != SNE; ++schedNode) {
-
- if((*I)->isPredecessor(*schedNode)) {
- int diff = (*I)->getInEdge(*schedNode).getIteDiff();
- int ES_Temp = nodesByCycle->first + (*schedNode)->getLatency() - diff * II;
- DEBUG(std::cerr << "Diff: " << diff << " Cycle: " << nodesByCycle->first << "\n");
- DEBUG(std::cerr << "Temp EarlyStart: " << ES_Temp << " Prev EarlyStart: " << EarlyStart << "\n");
- if(initialESVal)
- EarlyStart = std::max(EarlyStart, ES_Temp);
- else {
- EarlyStart = ES_Temp;
- initialESVal = true;
- }
- hasPred = true;
- }
- if((*I)->isSuccessor(*schedNode)) {
- int diff = (*schedNode)->getInEdge(*I).getIteDiff();
- int LS_Temp = nodesByCycle->first - (*I)->getLatency() + diff * II;
- DEBUG(std::cerr << "Diff: " << diff << " Cycle: " << nodesByCycle->first << "\n");
- DEBUG(std::cerr << "Temp LateStart: " << LS_Temp << " Prev LateStart: " << LateStart << "\n");
- if(initialLSVal)
- LateStart = std::min(LateStart, LS_Temp);
- else {
- LateStart = LS_Temp;
- initialLSVal = true;
- }
- hasSucc = true;
- }
- }
- }
+ //Loop over nodes in the schedule and determine if they are predecessors
+ //or successors of the node we are trying to schedule
+ for(MSSchedule::schedule_iterator nodesByCycle = schedule.begin(), nodesByCycleEnd = schedule.end();
+ nodesByCycle != nodesByCycleEnd; ++nodesByCycle) {
+
+ //For this cycle, get the vector of nodes schedule and loop over it
+ for(std::vector<MSchedGraphNode*>::iterator schedNode = nodesByCycle->second.begin(), SNE = nodesByCycle->second.end(); schedNode != SNE; ++schedNode) {
+
+ if((*I)->isPredecessor(*schedNode)) {
+ int diff = (*I)->getInEdge(*schedNode).getIteDiff();
+ int ES_Temp = nodesByCycle->first + (*schedNode)->getLatency() - diff * II;
+ DEBUG(std::cerr << "Diff: " << diff << " Cycle: " << nodesByCycle->first << "\n");
+ DEBUG(std::cerr << "Temp EarlyStart: " << ES_Temp << " Prev EarlyStart: " << EarlyStart << "\n");
+ if(initialESVal)
+ EarlyStart = std::max(EarlyStart, ES_Temp);
+ else {
+ EarlyStart = ES_Temp;
+ initialESVal = true;
+ }
+ hasPred = true;
+ }
+ if((*I)->isSuccessor(*schedNode)) {
+ int diff = (*schedNode)->getInEdge(*I).getIteDiff();
+ int LS_Temp = nodesByCycle->first - (*I)->getLatency() + diff * II;
+ DEBUG(std::cerr << "Diff: " << diff << " Cycle: " << nodesByCycle->first << "\n");
+ DEBUG(std::cerr << "Temp LateStart: " << LS_Temp << " Prev LateStart: " << LateStart << "\n");
+ if(initialLSVal)
+ LateStart = std::min(LateStart, LS_Temp);
+ else {
+ LateStart = LS_Temp;
+ initialLSVal = true;
+ }
+ hasSucc = true;
+ }
+ }
+ }
}
else {
- branches.push_back(*I);
- continue;
+ branches.push_back(*I);
+ continue;
}
//Check if this node is a pred or succ to a branch, and restrict its placement
//even though the branch is not in the schedule
/*int count = branches.size();
for(std::vector<MSchedGraphNode*>::iterator B = branches.begin(), BE = branches.end();
- B != BE; ++B) {
- if((*I)->isPredecessor(*B)) {
- int diff = (*I)->getInEdge(*B).getIteDiff();
- int ES_Temp = (II+count-1) + (*B)->getLatency() - diff * II;
- DEBUG(std::cerr << "Diff: " << diff << " Cycle: " << (II+count)-1 << "\n");
- DEBUG(std::cerr << "Temp EarlyStart: " << ES_Temp << " Prev EarlyStart: " << EarlyStart << "\n");
- EarlyStart = std::max(EarlyStart, ES_Temp);
- hasPred = true;
- }
-
- if((*I)->isSuccessor(*B)) {
- int diff = (*B)->getInEdge(*I).getIteDiff();
- int LS_Temp = (II+count-1) - (*I)->getLatency() + diff * II;
- DEBUG(std::cerr << "Diff: " << diff << " Cycle: " << (II+count-1) << "\n");
- DEBUG(std::cerr << "Temp LateStart: " << LS_Temp << " Prev LateStart: " << LateStart << "\n");
- LateStart = std::min(LateStart, LS_Temp);
- hasSucc = true;
- }
-
- count--;
+ B != BE; ++B) {
+ if((*I)->isPredecessor(*B)) {
+ int diff = (*I)->getInEdge(*B).getIteDiff();
+ int ES_Temp = (II+count-1) + (*B)->getLatency() - diff * II;
+ DEBUG(std::cerr << "Diff: " << diff << " Cycle: " << (II+count)-1 << "\n");
+ DEBUG(std::cerr << "Temp EarlyStart: " << ES_Temp << " Prev EarlyStart: " << EarlyStart << "\n");
+ EarlyStart = std::max(EarlyStart, ES_Temp);
+ hasPred = true;
+ }
+
+ if((*I)->isSuccessor(*B)) {
+ int diff = (*B)->getInEdge(*I).getIteDiff();
+ int LS_Temp = (II+count-1) - (*I)->getLatency() + diff * II;
+ DEBUG(std::cerr << "Diff: " << diff << " Cycle: " << (II+count-1) << "\n");
+ DEBUG(std::cerr << "Temp LateStart: " << LS_Temp << " Prev LateStart: " << LateStart << "\n");
+ LateStart = std::min(LateStart, LS_Temp);
+ hasSucc = true;
+ }
+
+ count--;
}*/
//Check if the node has no pred or successors and set Early Start to its ASAP
if(!hasSucc && !hasPred)
- EarlyStart = nodeToAttributesMap.find(*I)->second.ASAP;
+ EarlyStart = nodeToAttributesMap.find(*I)->second.ASAP;
DEBUG(std::cerr << "Has Successors: " << hasSucc << ", Has Pred: " << hasPred << "\n");
DEBUG(std::cerr << "EarlyStart: " << EarlyStart << ", LateStart: " << LateStart << "\n");
//Now, try to schedule this node depending upon its pred and successor in the schedule
//already
if(!hasSucc && hasPred)
- success = scheduleNode(*I, EarlyStart, (EarlyStart + II -1));
+ success = scheduleNode(*I, EarlyStart, (EarlyStart + II -1));
else if(!hasPred && hasSucc)
- success = scheduleNode(*I, LateStart, (LateStart - II +1));
+ success = scheduleNode(*I, LateStart, (LateStart - II +1));
else if(hasPred && hasSucc) {
- if(EarlyStart > LateStart) {
- success = false;
- //LateStart = EarlyStart;
- DEBUG(std::cerr << "Early Start can not be later then the late start cycle, schedule fails\n");
- }
- else
- success = scheduleNode(*I, EarlyStart, std::min(LateStart, (EarlyStart + II -1)));
+ if(EarlyStart > LateStart) {
+ success = false;
+ //LateStart = EarlyStart;
+ DEBUG(std::cerr << "Early Start can not be later then the late start cycle, schedule fails\n");
+ }
+ else
+ success = scheduleNode(*I, EarlyStart, std::min(LateStart, (EarlyStart + II -1)));
}
else
- success = scheduleNode(*I, EarlyStart, EarlyStart + II - 1);
+ success = scheduleNode(*I, EarlyStart, EarlyStart + II - 1);
if(!success) {
- ++II;
- schedule.clear();
- break;
+ ++II;
+ schedule.clear();
+ break;
}
}
success = schedule.constructKernel(II, branches, indVarInstrs[BB]);
DEBUG(std::cerr << "Done Constructing Schedule Kernel\n");
if(!success) {
- ++II;
- schedule.clear();
+ ++II;
+ schedule.clear();
}
DEBUG(std::cerr << "Final II: " << II << "\n");
}
bool ModuloSchedulingPass::scheduleNode(MSchedGraphNode *node,
- int start, int end) {
+ int start, int end) {
bool success = false;
DEBUG(std::cerr << *node << " (Start Cycle: " << start << ", End Cycle: " << end << ")\n");
++cycle;
DEBUG(std::cerr << "Increase cycle: " << cycle << "\n");
if(cycle > end)
- return false;
+ return false;
}
else {
--cycle;
DEBUG(std::cerr << "Decrease cycle: " << cycle << "\n");
if(cycle < end)
- return false;
+ return false;
}
}
DEBUG(std::cerr << "i=" << i << "\n");
for(int j = i; j >= 0; --j) {
for(MachineBasicBlock::const_iterator MI = origBB->begin(), ME = origBB->end(); ME != MI; ++MI) {
- if(inKernel[j].count(&*MI)) {
- MachineInstr *instClone = MI->clone();
- machineBB->push_back(instClone);
-
- //If its a branch, insert a nop
- if(mii->isBranch(instClone->getOpcode()))
- BuildMI(machineBB, V9::NOP, 0);
-
-
- DEBUG(std::cerr << "Cloning: " << *MI << "\n");
-
- //After cloning, we may need to save the value that this instruction defines
- for(unsigned opNum=0; opNum < MI->getNumOperands(); ++opNum) {
- Instruction *tmp;
-
- //get machine operand
- MachineOperand &mOp = instClone->getOperand(opNum);
- if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef()) {
-
- //Check if this is a value we should save
- if(valuesToSave.count(mOp.getVRegValue())) {
- //Save copy in tmpInstruction
- tmp = new TmpInstruction(mOp.getVRegValue());
-
- //Add TmpInstruction to safe LLVM Instruction MCFI
- MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst);
- tempMvec.addTemp((Value*) tmp);
-
- DEBUG(std::cerr << "Value: " << *(mOp.getVRegValue()) << " New Value: " << *tmp << " Stage: " << i << "\n");
-
- newValues[mOp.getVRegValue()][i]= tmp;
- newValLocation[tmp] = machineBB;
-
- DEBUG(std::cerr << "Machine Instr Operands: " << *(mOp.getVRegValue()) << ", 0, " << *tmp << "\n");
-
- //Create machine instruction and put int machineBB
- MachineInstr *saveValue;
- if(mOp.getVRegValue()->getType() == Type::FloatTy)
- saveValue = BuildMI(machineBB, V9::FMOVS, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
- else if(mOp.getVRegValue()->getType() == Type::DoubleTy)
- saveValue = BuildMI(machineBB, V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
- else
- saveValue = BuildMI(machineBB, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp);
-
-
- DEBUG(std::cerr << "Created new machine instr: " << *saveValue << "\n");
- }
- }
-
- //We may also need to update the value that we use if its from an earlier prologue
- if(j != 0) {
- if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isUse()) {
- if(newValues.count(mOp.getVRegValue())) {
- if(newValues[mOp.getVRegValue()].count(i-1)) {
- Value *oldV = mOp.getVRegValue();
- DEBUG(std::cerr << "Replaced this value: " << mOp.getVRegValue() << " With:" << (newValues[mOp.getVRegValue()][i-1]) << "\n");
- //Update the operand with the right value
- mOp.setValueReg(newValues[mOp.getVRegValue()][i-1]);
-
- //Remove this value since we have consumed it
- //NOTE: Should this only be done if j != maxStage?
- consumedValues[oldV][i-1] = (newValues[oldV][i-1]);
- DEBUG(std::cerr << "Deleted value: " << consumedValues[oldV][i-1] << "\n");
- newValues[oldV].erase(i-1);
- }
- }
- else
- if(consumedValues.count(mOp.getVRegValue()))
- assert(!consumedValues[mOp.getVRegValue()].count(i-1) && "Found a case where we need the value");
- }
- }
- }
- }
+ if(inKernel[j].count(&*MI)) {
+ MachineInstr *instClone = MI->clone();
+ machineBB->push_back(instClone);
+
+ //If its a branch, insert a nop
+ if(mii->isBranch(instClone->getOpcode()))
+ BuildMI(machineBB, V9::NOP, 0);
+
+
+ DEBUG(std::cerr << "Cloning: " << *MI << "\n");
+
+ //After cloning, we may need to save the value that this instruction defines
+ for(unsigned opNum=0; opNum < MI->getNumOperands(); ++opNum) {
+ Instruction *tmp;
+
+ //get machine operand
+ MachineOperand &mOp = instClone->getOperand(opNum);
+ if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef()) {
+
+ //Check if this is a value we should save
+ if(valuesToSave.count(mOp.getVRegValue())) {
+ //Save copy in tmpInstruction
+ tmp = new TmpInstruction(mOp.getVRegValue());
+
+ //Add TmpInstruction to safe LLVM Instruction MCFI
+ MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst);
+ tempMvec.addTemp((Value*) tmp);
+
+ DEBUG(std::cerr << "Value: " << *(mOp.getVRegValue()) << " New Value: " << *tmp << " Stage: " << i << "\n");
+
+ newValues[mOp.getVRegValue()][i]= tmp;
+ newValLocation[tmp] = machineBB;
+
+ DEBUG(std::cerr << "Machine Instr Operands: " << *(mOp.getVRegValue()) << ", 0, " << *tmp << "\n");
+
+ //Create machine instruction and put int machineBB
+ MachineInstr *saveValue;
+ if(mOp.getVRegValue()->getType() == Type::FloatTy)
+ saveValue = BuildMI(machineBB, V9::FMOVS, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
+ else if(mOp.getVRegValue()->getType() == Type::DoubleTy)
+ saveValue = BuildMI(machineBB, V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
+ else
+ saveValue = BuildMI(machineBB, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp);
+
+
+ DEBUG(std::cerr << "Created new machine instr: " << *saveValue << "\n");
+ }
+ }
+
+ //We may also need to update the value that we use if its from an earlier prologue
+ if(j != 0) {
+ if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isUse()) {
+ if(newValues.count(mOp.getVRegValue())) {
+ if(newValues[mOp.getVRegValue()].count(i-1)) {
+ Value *oldV = mOp.getVRegValue();
+ DEBUG(std::cerr << "Replaced this value: " << mOp.getVRegValue() << " With:" << (newValues[mOp.getVRegValue()][i-1]) << "\n");
+ //Update the operand with the right value
+ mOp.setValueReg(newValues[mOp.getVRegValue()][i-1]);
+
+ //Remove this value since we have consumed it
+ //NOTE: Should this only be done if j != maxStage?
+ consumedValues[oldV][i-1] = (newValues[oldV][i-1]);
+ DEBUG(std::cerr << "Deleted value: " << consumedValues[oldV][i-1] << "\n");
+ newValues[oldV].erase(i-1);
+ }
+ }
+ else
+ if(consumedValues.count(mOp.getVRegValue()))
+ assert(!consumedValues[mOp.getVRegValue()].count(i-1) && "Found a case where we need the value");
+ }
+ }
+ }
+ }
}
}
for(MachineBasicBlock::const_iterator MI = origBB->begin(), ME = origBB->end(); ME != MI; ++MI) {
for(int j=schedule.getMaxStage(); j > i; --j) {
- if(inKernel[j].count(&*MI)) {
- DEBUG(std::cerr << "Cloning instruction " << *MI << "\n");
- MachineInstr *clone = MI->clone();
-
- //Update operands that need to use the result from the phi
- for(unsigned opNum=0; opNum < clone->getNumOperands(); ++opNum) {
- //get machine operand
- const MachineOperand &mOp = clone->getOperand(opNum);
-
- if((mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isUse())) {
-
- DEBUG(std::cerr << "Writing PHI for " << (mOp.getVRegValue()) << "\n");
-
- //If this is the last instructions for the max iterations ago, don't update operands
- if(inEpilogue.count(mOp.getVRegValue()))
- if(inEpilogue[mOp.getVRegValue()] == i)
- continue;
-
- //Quickly write appropriate phis for this operand
- if(newValues.count(mOp.getVRegValue())) {
- if(newValues[mOp.getVRegValue()].count(i)) {
- Instruction *tmp = new TmpInstruction(newValues[mOp.getVRegValue()][i]);
-
- //Get machine code for this instruction
- MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst);
- tempMvec.addTemp((Value*) tmp);
-
- //assert of no kernelPHI for this value
- assert(kernelPHIs[mOp.getVRegValue()][i] !=0 && "Must have final kernel phi to construct epilogue phi");
-
- MachineInstr *saveValue = BuildMI(machineBB, V9::PHI, 3).addReg(newValues[mOp.getVRegValue()][i]).addReg(kernelPHIs[mOp.getVRegValue()][i]).addRegDef(tmp);
- DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n");
- valPHIs[mOp.getVRegValue()] = tmp;
- }
- }
-
- if(valPHIs.count(mOp.getVRegValue())) {
- //Update the operand in the cloned instruction
- clone->getOperand(opNum).setValueReg(valPHIs[mOp.getVRegValue()]);
- }
- }
- else if((mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef())) {
- inEpilogue[mOp.getVRegValue()] = i;
- }
- }
- machineBB->push_back(clone);
- }
+ if(inKernel[j].count(&*MI)) {
+ DEBUG(std::cerr << "Cloning instruction " << *MI << "\n");
+ MachineInstr *clone = MI->clone();
+
+ //Update operands that need to use the result from the phi
+ for(unsigned opNum=0; opNum < clone->getNumOperands(); ++opNum) {
+ //get machine operand
+ const MachineOperand &mOp = clone->getOperand(opNum);
+
+ if((mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isUse())) {
+
+ DEBUG(std::cerr << "Writing PHI for " << (mOp.getVRegValue()) << "\n");
+
+ //If this is the last instructions for the max iterations ago, don't update operands
+ if(inEpilogue.count(mOp.getVRegValue()))
+ if(inEpilogue[mOp.getVRegValue()] == i)
+ continue;
+
+ //Quickly write appropriate phis for this operand
+ if(newValues.count(mOp.getVRegValue())) {
+ if(newValues[mOp.getVRegValue()].count(i)) {
+ Instruction *tmp = new TmpInstruction(newValues[mOp.getVRegValue()][i]);
+
+ //Get machine code for this instruction
+ MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst);
+ tempMvec.addTemp((Value*) tmp);
+
+ //assert of no kernelPHI for this value
+ assert(kernelPHIs[mOp.getVRegValue()][i] !=0 && "Must have final kernel phi to construct epilogue phi");
+
+ MachineInstr *saveValue = BuildMI(machineBB, V9::PHI, 3).addReg(newValues[mOp.getVRegValue()][i]).addReg(kernelPHIs[mOp.getVRegValue()][i]).addRegDef(tmp);
+ DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n");
+ valPHIs[mOp.getVRegValue()] = tmp;
+ }
+ }
+
+ if(valPHIs.count(mOp.getVRegValue())) {
+ //Update the operand in the cloned instruction
+ clone->getOperand(opNum).setValueReg(valPHIs[mOp.getVRegValue()]);
+ }
+ }
+ else if((mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef())) {
+ inEpilogue[mOp.getVRegValue()] = i;
+ }
+ }
+ machineBB->push_back(clone);
+ }
}
}
if(I->second != 0) {
if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isUse()) {
- //Check to see where this operand is defined if this instruction is from max stage
- if(I->second == schedule.getMaxStage()) {
- DEBUG(std::cerr << "VREG: " << *(mOp.getVRegValue()) << "\n");
- }
-
- //If its in the value saved, we need to create a temp instruction and use that instead
- if(valuesToSave.count(mOp.getVRegValue())) {
-
- //Check if we already have a final PHI value for this
- if(!finalPHIValue.count(mOp.getVRegValue())) {
- //Only create phi if the operand def is from a stage before this one
- if(schedule.defPreviousStage(mOp.getVRegValue(), I->second)) {
- TmpInstruction *tmp = new TmpInstruction(mOp.getVRegValue());
-
- //Get machine code for this instruction
- MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst);
- tempMvec.addTemp((Value*) tmp);
-
- //Update the operand in the cloned instruction
- instClone->getOperand(i).setValueReg(tmp);
-
- //save this as our final phi
- finalPHIValue[mOp.getVRegValue()] = tmp;
- newValLocation[tmp] = machineBB;
- }
- }
- else {
- //Use the previous final phi value
- instClone->getOperand(i).setValueReg(finalPHIValue[mOp.getVRegValue()]);
- }
- }
+ //Check to see where this operand is defined if this instruction is from max stage
+ if(I->second == schedule.getMaxStage()) {
+ DEBUG(std::cerr << "VREG: " << *(mOp.getVRegValue()) << "\n");
+ }
+
+ //If its in the value saved, we need to create a temp instruction and use that instead
+ if(valuesToSave.count(mOp.getVRegValue())) {
+
+ //Check if we already have a final PHI value for this
+ if(!finalPHIValue.count(mOp.getVRegValue())) {
+ //Only create phi if the operand def is from a stage before this one
+ if(schedule.defPreviousStage(mOp.getVRegValue(), I->second)) {
+ TmpInstruction *tmp = new TmpInstruction(mOp.getVRegValue());
+
+ //Get machine code for this instruction
+ MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst);
+ tempMvec.addTemp((Value*) tmp);
+
+ //Update the operand in the cloned instruction
+ instClone->getOperand(i).setValueReg(tmp);
+
+ //save this as our final phi
+ finalPHIValue[mOp.getVRegValue()] = tmp;
+ newValLocation[tmp] = machineBB;
+ }
+ }
+ else {
+ //Use the previous final phi value
+ instClone->getOperand(i).setValueReg(finalPHIValue[mOp.getVRegValue()]);
+ }
+ }
}
}
if(I->second != schedule.getMaxStage()) {
if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef()) {
- if(valuesToSave.count(mOp.getVRegValue())) {
-
- TmpInstruction *tmp = new TmpInstruction(mOp.getVRegValue());
-
- //Get machine code for this instruction
- MachineCodeForInstruction & tempVec = MachineCodeForInstruction::get(defaultInst);
- tempVec.addTemp((Value*) tmp);
-
- //Create new machine instr and put in MBB
- MachineInstr *saveValue;
- if(mOp.getVRegValue()->getType() == Type::FloatTy)
- saveValue = BuildMI(machineBB, V9::FMOVS, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
- else if(mOp.getVRegValue()->getType() == Type::DoubleTy)
- saveValue = BuildMI(machineBB, V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
- else
- saveValue = BuildMI(machineBB, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp);
-
-
- //Save for future cleanup
- kernelValue[mOp.getVRegValue()] = tmp;
- newValLocation[tmp] = machineBB;
- kernelPHIs[mOp.getVRegValue()][schedule.getMaxStage()-1] = tmp;
- }
+ if(valuesToSave.count(mOp.getVRegValue())) {
+
+ TmpInstruction *tmp = new TmpInstruction(mOp.getVRegValue());
+
+ //Get machine code for this instruction
+ MachineCodeForInstruction & tempVec = MachineCodeForInstruction::get(defaultInst);
+ tempVec.addTemp((Value*) tmp);
+
+ //Create new machine instr and put in MBB
+ MachineInstr *saveValue;
+ if(mOp.getVRegValue()->getType() == Type::FloatTy)
+ saveValue = BuildMI(machineBB, V9::FMOVS, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
+ else if(mOp.getVRegValue()->getType() == Type::DoubleTy)
+ saveValue = BuildMI(machineBB, V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
+ else
+ saveValue = BuildMI(machineBB, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp);
+
+
+ //Save for future cleanup
+ kernelValue[mOp.getVRegValue()] = tmp;
+ newValLocation[tmp] = machineBB;
+ kernelPHIs[mOp.getVRegValue()][schedule.getMaxStage()-1] = tmp;
+ }
}
}
}
DEBUG(std::cerr << "Writing phi for" << *(V->first));
DEBUG(std::cerr << "\nMap of Value* for this phi\n");
DEBUG(for(std::map<int, Value*>::iterator I = V->second.begin(),
- IE = V->second.end(); I != IE; ++I) {
+ IE = V->second.end(); I != IE; ++I) {
std::cerr << "Stage: " << I->first;
std::cerr << " Value: " << *(I->second) << "\n";
});
unsigned count = 1;
//Loop over the the map backwards to generate phis
for(std::map<int, Value*>::reverse_iterator I = V->second.rbegin(), IE = V->second.rend();
- I != IE; ++I) {
+ I != IE; ++I) {
if(count < (V->second).size()) {
- if(lastPhi == 0) {
- lastPhi = new TmpInstruction(I->second);
-
- //Get machine code for this instruction
- MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst);
- tempMvec.addTemp((Value*) lastPhi);
-
- MachineInstr *saveValue = BuildMI(*machineBB, machineBB->begin(), V9::PHI, 3).addReg(kernelValue[V->first]).addReg(I->second).addRegDef(lastPhi);
- DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n");
- newValLocation[lastPhi] = machineBB;
- }
- else {
- Instruction *tmp = new TmpInstruction(I->second);
-
- //Get machine code for this instruction
- MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst);
- tempMvec.addTemp((Value*) tmp);
-
-
- MachineInstr *saveValue = BuildMI(*machineBB, machineBB->begin(), V9::PHI, 3).addReg(lastPhi).addReg(I->second).addRegDef(tmp);
- DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n");
- lastPhi = tmp;
- kernelPHIs[V->first][I->first] = lastPhi;
- newValLocation[lastPhi] = machineBB;
- }
+ if(lastPhi == 0) {
+ lastPhi = new TmpInstruction(I->second);
+
+ //Get machine code for this instruction
+ MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst);
+ tempMvec.addTemp((Value*) lastPhi);
+
+ MachineInstr *saveValue = BuildMI(*machineBB, machineBB->begin(), V9::PHI, 3).addReg(kernelValue[V->first]).addReg(I->second).addRegDef(lastPhi);
+ DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n");
+ newValLocation[lastPhi] = machineBB;
+ }
+ else {
+ Instruction *tmp = new TmpInstruction(I->second);
+
+ //Get machine code for this instruction
+ MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst);
+ tempMvec.addTemp((Value*) tmp);
+
+
+ MachineInstr *saveValue = BuildMI(*machineBB, machineBB->begin(), V9::PHI, 3).addReg(lastPhi).addReg(I->second).addRegDef(tmp);
+ DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n");
+ lastPhi = tmp;
+ kernelPHIs[V->first][I->first] = lastPhi;
+ newValLocation[lastPhi] = machineBB;
+ }
}
//Final phi value
else {
- //The resulting value must be the Value* we created earlier
- assert(lastPhi != 0 && "Last phi is NULL!\n");
- MachineInstr *saveValue = BuildMI(*machineBB, machineBB->begin(), V9::PHI, 3).addReg(lastPhi).addReg(I->second).addRegDef(finalPHIValue[V->first]);
- DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n");
- kernelPHIs[V->first][I->first] = finalPHIValue[V->first];
+ //The resulting value must be the Value* we created earlier
+ assert(lastPhi != 0 && "Last phi is NULL!\n");
+ MachineInstr *saveValue = BuildMI(*machineBB, machineBB->begin(), V9::PHI, 3).addReg(lastPhi).addReg(I->second).addRegDef(finalPHIValue[V->first]);
+ DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n");
+ kernelPHIs[V->first][I->first] = finalPHIValue[V->first];
}
++count;
Instruction *tmp = 0;
for(unsigned i = 0; i < I->getNumOperands(); ++i) {
- //Get Operand
- const MachineOperand &mOp = I->getOperand(i);
- assert(mOp.getType() == MachineOperand::MO_VirtualRegister && "Should be a Value*\n");
-
- if(!tmp) {
- tmp = new TmpInstruction(mOp.getVRegValue());
- addToMCFI.push_back(tmp);
- }
-
- //Now for all our arguments we read, OR to the new TmpInstruction that we created
- if(mOp.isUse()) {
- DEBUG(std::cerr << "Use: " << mOp << "\n");
- //Place a copy at the end of its BB but before the branches
- assert(newValLocation.count(mOp.getVRegValue()) && "We must know where this value is located\n");
- //Reverse iterate to find the branches, we can safely assume no instructions have been
- //put in the nop positions
- for(MachineBasicBlock::iterator inst = --(newValLocation[mOp.getVRegValue()])->end(), endBB = (newValLocation[mOp.getVRegValue()])->begin(); inst != endBB; --inst) {
- MachineOpCode opc = inst->getOpcode();
- if(TMI->isBranch(opc) || TMI->isNop(opc))
- continue;
- else {
- if(mOp.getVRegValue()->getType() == Type::FloatTy)
- BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVS, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
- else if(mOp.getVRegValue()->getType() == Type::DoubleTy)
- BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
- else
- BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp);
-
- break;
- }
-
- }
-
- }
- else {
- //Remove the phi and replace it with an OR
- DEBUG(std::cerr << "Def: " << mOp << "\n");
- //newORs.push_back(std::make_pair(tmp, mOp.getVRegValue()));
- if(tmp->getType() == Type::FloatTy)
- BuildMI(*kernelBB, I, V9::FMOVS, 3).addReg(tmp).addRegDef(mOp.getVRegValue());
- else if(tmp->getType() == Type::DoubleTy)
- BuildMI(*kernelBB, I, V9::FMOVD, 3).addReg(tmp).addRegDef(mOp.getVRegValue());
- else
- BuildMI(*kernelBB, I, V9::ORr, 3).addReg(tmp).addImm(0).addRegDef(mOp.getVRegValue());
-
-
- worklist.push_back(std::make_pair(kernelBB, I));
- }
-
+ //Get Operand
+ const MachineOperand &mOp = I->getOperand(i);
+ assert(mOp.getType() == MachineOperand::MO_VirtualRegister && "Should be a Value*\n");
+
+ if(!tmp) {
+ tmp = new TmpInstruction(mOp.getVRegValue());
+ addToMCFI.push_back(tmp);
+ }
+
+ //Now for all our arguments we read, OR to the new TmpInstruction that we created
+ if(mOp.isUse()) {
+ DEBUG(std::cerr << "Use: " << mOp << "\n");
+ //Place a copy at the end of its BB but before the branches
+ assert(newValLocation.count(mOp.getVRegValue()) && "We must know where this value is located\n");
+ //Reverse iterate to find the branches, we can safely assume no instructions have been
+ //put in the nop positions
+ for(MachineBasicBlock::iterator inst = --(newValLocation[mOp.getVRegValue()])->end(), endBB = (newValLocation[mOp.getVRegValue()])->begin(); inst != endBB; --inst) {
+ MachineOpCode opc = inst->getOpcode();
+ if(TMI->isBranch(opc) || TMI->isNop(opc))
+ continue;
+ else {
+ if(mOp.getVRegValue()->getType() == Type::FloatTy)
+ BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVS, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
+ else if(mOp.getVRegValue()->getType() == Type::DoubleTy)
+ BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
+ else
+ BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp);
+
+ break;
+ }
+
+ }
+
+ }
+ else {
+ //Remove the phi and replace it with an OR
+ DEBUG(std::cerr << "Def: " << mOp << "\n");
+ //newORs.push_back(std::make_pair(tmp, mOp.getVRegValue()));
+ if(tmp->getType() == Type::FloatTy)
+ BuildMI(*kernelBB, I, V9::FMOVS, 3).addReg(tmp).addRegDef(mOp.getVRegValue());
+ else if(tmp->getType() == Type::DoubleTy)
+ BuildMI(*kernelBB, I, V9::FMOVD, 3).addReg(tmp).addRegDef(mOp.getVRegValue());
+ else
+ BuildMI(*kernelBB, I, V9::ORr, 3).addReg(tmp).addImm(0).addRegDef(mOp.getVRegValue());
+
+
+ worklist.push_back(std::make_pair(kernelBB, I));
+ }
+
}
}
DEBUG(std::cerr << "Looking at Instr: " << *I << "\n");
//Get op code and check if its a phi
if(I->getOpcode() == V9::PHI) {
- Instruction *tmp = 0;
-
- for(unsigned i = 0; i < I->getNumOperands(); ++i) {
- //Get Operand
- const MachineOperand &mOp = I->getOperand(i);
- assert(mOp.getType() == MachineOperand::MO_VirtualRegister && "Should be a Value*\n");
-
- if(!tmp) {
- tmp = new TmpInstruction(mOp.getVRegValue());
- addToMCFI.push_back(tmp);
- }
-
- //Now for all our arguments we read, OR to the new TmpInstruction that we created
- if(mOp.isUse()) {
- DEBUG(std::cerr << "Use: " << mOp << "\n");
- //Place a copy at the end of its BB but before the branches
- assert(newValLocation.count(mOp.getVRegValue()) && "We must know where this value is located\n");
- //Reverse iterate to find the branches, we can safely assume no instructions have been
- //put in the nop positions
- for(MachineBasicBlock::iterator inst = --(newValLocation[mOp.getVRegValue()])->end(), endBB = (newValLocation[mOp.getVRegValue()])->begin(); inst != endBB; --inst) {
- MachineOpCode opc = inst->getOpcode();
- if(TMI->isBranch(opc) || TMI->isNop(opc))
- continue;
- else {
- if(mOp.getVRegValue()->getType() == Type::FloatTy)
- BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVS, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
- else if(mOp.getVRegValue()->getType() == Type::DoubleTy)
- BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
- else
- BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp);
-
-
- break;
- }
-
- }
-
- }
- else {
- //Remove the phi and replace it with an OR
- DEBUG(std::cerr << "Def: " << mOp << "\n");
- if(tmp->getType() == Type::FloatTy)
- BuildMI(**MB, I, V9::FMOVS, 3).addReg(tmp).addRegDef(mOp.getVRegValue());
- else if(tmp->getType() == Type::DoubleTy)
- BuildMI(**MB, I, V9::FMOVD, 3).addReg(tmp).addRegDef(mOp.getVRegValue());
- else
- BuildMI(**MB, I, V9::ORr, 3).addReg(tmp).addImm(0).addRegDef(mOp.getVRegValue());
-
- worklist.push_back(std::make_pair(*MB,I));
- }
-
- }
+ Instruction *tmp = 0;
+
+ for(unsigned i = 0; i < I->getNumOperands(); ++i) {
+ //Get Operand
+ const MachineOperand &mOp = I->getOperand(i);
+ assert(mOp.getType() == MachineOperand::MO_VirtualRegister && "Should be a Value*\n");
+
+ if(!tmp) {
+ tmp = new TmpInstruction(mOp.getVRegValue());
+ addToMCFI.push_back(tmp);
+ }
+
+ //Now for all our arguments we read, OR to the new TmpInstruction that we created
+ if(mOp.isUse()) {
+ DEBUG(std::cerr << "Use: " << mOp << "\n");
+ //Place a copy at the end of its BB but before the branches
+ assert(newValLocation.count(mOp.getVRegValue()) && "We must know where this value is located\n");
+ //Reverse iterate to find the branches, we can safely assume no instructions have been
+ //put in the nop positions
+ for(MachineBasicBlock::iterator inst = --(newValLocation[mOp.getVRegValue()])->end(), endBB = (newValLocation[mOp.getVRegValue()])->begin(); inst != endBB; --inst) {
+ MachineOpCode opc = inst->getOpcode();
+ if(TMI->isBranch(opc) || TMI->isNop(opc))
+ continue;
+ else {
+ if(mOp.getVRegValue()->getType() == Type::FloatTy)
+ BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVS, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
+ else if(mOp.getVRegValue()->getType() == Type::DoubleTy)
+ BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
+ else
+ BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp);
+
+
+ break;
+ }
+
+ }
+
+ }
+ else {
+ //Remove the phi and replace it with an OR
+ DEBUG(std::cerr << "Def: " << mOp << "\n");
+ if(tmp->getType() == Type::FloatTy)
+ BuildMI(**MB, I, V9::FMOVS, 3).addReg(tmp).addRegDef(mOp.getVRegValue());
+ else if(tmp->getType() == Type::DoubleTy)
+ BuildMI(**MB, I, V9::FMOVD, 3).addReg(tmp).addRegDef(mOp.getVRegValue());
+ else
+ BuildMI(**MB, I, V9::ORr, 3).addReg(tmp).addImm(0).addRegDef(mOp.getVRegValue());
+
+ worklist.push_back(std::make_pair(*MB,I));
+ }
+
+ }
}
DEBUG(std::cerr << "Deleting PHI " << *I->second << "\n");
I->first->erase(I->second);
-
+
}
lastInstrs[inst] = I->second;
for(unsigned i=0; i < inst->getNumOperands(); ++i) {
- //get machine operand
- const MachineOperand &mOp = inst->getOperand(i);
-
- if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isUse()) {
- //find the value in the map
- if (const Value* srcI = mOp.getVRegValue()) {
-
- if(isa<Constant>(srcI) || isa<Argument>(srcI))
- continue;
-
- //Before we declare this Value* one that we should save
- //make sure its def is not of the same stage as this instruction
- //because it will be consumed before its used
- Instruction *defInst = (Instruction*) srcI;
-
- //Should we save this value?
- bool save = true;
-
- //Continue if not in the def map, loop invariant code does not need to be saved
- if(!defMap.count(srcI))
- continue;
-
- MachineInstr *defInstr = defMap[srcI];
-
-
- if(lastInstrs.count(defInstr)) {
- if(lastInstrs[defInstr] == I->second) {
- save = false;
-
- }
- }
-
- if(save) {
- assert(!phiUses.count(srcI) && "Did not expect to see phi use twice");
- if(isa<PHINode>(srcI))
- phiUses[srcI] = I->second;
-
- valuesToSave[srcI] = std::make_pair(I->first, i);
-
- }
- }
- }
- else if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef()) {
- if (const Value* destI = mOp.getVRegValue()) {
- if(!isa<PHINode>(destI))
- continue;
- if(phiUses.count(destI)) {
- if(phiUses[destI] == I->second) {
- //remove from save list
- valuesToSave.erase(destI);
- }
- }
- }
- }
-
- if(mOp.getType() != MachineOperand::MO_VirtualRegister && mOp.isUse()) {
- assert("Our assumption is wrong. We have another type of register that needs to be saved\n");
- }
+ //get machine operand
+ const MachineOperand &mOp = inst->getOperand(i);
+
+ if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isUse()) {
+ //find the value in the map
+ if (const Value* srcI = mOp.getVRegValue()) {
+
+
if(isa<Constant>(srcI) || isa<Argument>(srcI))
+ continue;
+
+ //Before we declare this Value* one that we should save
+ //make sure its def is not of the same stage as this instruction
+ //because it will be consumed before its used
+ Instruction *defInst = (Instruction*) srcI;
+
+ //Should we save this value?
+ bool save = true;
+
+ //Continue if not in the def map, loop invariant code does not need to be saved
+ if(!defMap.count(srcI))
+ continue;
+
+ MachineInstr *defInstr = defMap[srcI];
+
+
+ if(lastInstrs.count(defInstr)) {
+ if(lastInstrs[defInstr] == I->second) {
+ save = false;
+
+ }
+ }
+
+ if(save) {
+ assert(!phiUses.count(srcI) && "Did not expect to see phi use twice");
+ phiUses[srcI] = I->second;
+
+ valuesToSave[srcI] = std::make_pair(I->first, i);
+
+ }
+ }
+ }
+ else if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef()) {
+ if (const Value* destI = mOp.getVRegValue()) {
+
if(!isa<PHINode>(destI))
+ continue;
+ if(phiUses.count(destI)) {
+ if(phiUses[destI] == I->second) {
+ //remove from save list
+ valuesToSave.erase(destI);
+ }
+ }
+ }
+ }
+
+ if(mOp.getType() != MachineOperand::MO_VirtualRegister && mOp.isUse()) {
+ assert("Our assumption is wrong. We have another type of register that needs to be saved\n");
+ }
}
}
}
//Find terminator since getFirstTerminator does not work!
for(MachineBasicBlock::reverse_iterator mInst = prologues[I]->rbegin(), mInstEnd = prologues[I]->rend(); mInst != mInstEnd; ++mInst) {
- MachineOpCode OC = mInst->getOpcode();
- //If its a branch update its branchto
- if(TMI->isBranch(OC)) {
- for(unsigned opNum = 0; opNum < mInst->getNumOperands(); ++opNum) {
- MachineOperand &mOp = mInst->getOperand(opNum);
- if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
- //Check if we are branching to the kernel, if not branch to epilogue
- if(mOp.getVRegValue() == BB->getBasicBlock()) {
- if(I == prologues.size()-1)
- mOp.setValueReg(llvmKernelBB);
- else
- mOp.setValueReg(llvm_prologues[I+1]);
- }
- else {
- mOp.setValueReg(llvm_epilogues[(llvm_epilogues.size()-1-I)]);
- }
- }
- }
-
- DEBUG(std::cerr << "New Prologue Branch: " << *mInst << "\n");
- }
+ MachineOpCode OC = mInst->getOpcode();
+ //If its a branch update its branchto
+ if(TMI->isBranch(OC)) {
+ for(unsigned opNum = 0; opNum < mInst->getNumOperands(); ++opNum) {
+ MachineOperand &mOp = mInst->getOperand(opNum);
+ if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
+ //Check if we are branching to the kernel, if not branch to epilogue
+ if(mOp.getVRegValue() == BB->getBasicBlock()) {
+ if(I == prologues.size()-1)
+ mOp.setValueReg(llvmKernelBB);
+ else
+ mOp.setValueReg(llvm_prologues[I+1]);
+ }
+ else {
+ mOp.setValueReg(llvm_epilogues[(llvm_epilogues.size()-1-I)]);
+ }
+ }
+ }
+
+ DEBUG(std::cerr << "New Prologue Branch: " << *mInst << "\n");
+ }
}
const BranchInst *branchVal = dyn_cast<BranchInst>(BB->getBasicBlock()->getTerminator());
if(I == prologues.size()-1) {
- TerminatorInst *newBranch = new BranchInst(llvmKernelBB,
- llvm_epilogues[(llvm_epilogues.size()-1-I)],
- branchVal->getCondition(),
- llvm_prologues[I]);
+ TerminatorInst *newBranch = new BranchInst(llvmKernelBB,
+ llvm_epilogues[(llvm_epilogues.size()-1-I)],
+ branchVal->getCondition(),
+ llvm_prologues[I]);
}
else
- TerminatorInst *newBranch = new BranchInst(llvm_prologues[I+1],
- llvm_epilogues[(llvm_epilogues.size()-1-I)],
- branchVal->getCondition(),
- llvm_prologues[I]);
+ TerminatorInst *newBranch = new BranchInst(llvm_prologues[I+1],
+ llvm_epilogues[(llvm_epilogues.size()-1-I)],
+ branchVal->getCondition(),
+ llvm_prologues[I]);
}
}
MachineOpCode OC = mInst->getOpcode();
if(TMI->isBranch(OC)) {
for(unsigned opNum = 0; opNum < mInst->getNumOperands(); ++opNum) {
- MachineOperand &mOp = mInst->getOperand(opNum);
-
- if(mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
- if(mOp.getVRegValue() == BB->getBasicBlock())
- mOp.setValueReg(llvmKernelBB);
- else
- if(llvm_epilogues.size() > 0) {
- assert(origBranchExit == 0 && "There should only be one branch out of the loop");
-
- origBranchExit = mOp.getVRegValue();
- mOp.setValueReg(llvm_epilogues[0]);
- }
- else
- origBranchExit = mOp.getVRegValue();
- }
+ MachineOperand &mOp = mInst->getOperand(opNum);
+
+ if(mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
+ if(mOp.getVRegValue() == BB->getBasicBlock())
+ mOp.setValueReg(llvmKernelBB);
+ else
+ if(llvm_epilogues.size() > 0) {
+ assert(origBranchExit == 0 && "There should only be one branch out of the loop");
+
+ origBranchExit = mOp.getVRegValue();
+ mOp.setValueReg(llvm_epilogues[0]);
+ }
+ else
+ origBranchExit = mOp.getVRegValue();
+ }
}
}
}
if(epilogues.size() > 0) {
TerminatorInst *newBranch = new BranchInst(llvmKernelBB,
- llvm_epilogues[0],
- branchVal->getCondition(),
- llvmKernelBB);
+ llvm_epilogues[0],
+ branchVal->getCondition(),
+ llvmKernelBB);
}
else {
BasicBlock *origBBExit = dyn_cast<BasicBlock>(origBranchExit);
assert(origBBExit !=0 && "Original exit basic block must be set");
TerminatorInst *newBranch = new BranchInst(llvmKernelBB,
- origBBExit,
- branchVal->getCondition(),
- llvmKernelBB);
+ origBBExit,
+ branchVal->getCondition(),
+ llvmKernelBB);
}
if(schedule.getMaxStage() != 0) {
BuildMI(epilogues[I], V9::BA, 1).addPCDisp(llvm_epilogues[I+1]);
//Add unconditional branch to end of epilogue
TerminatorInst *newBranch = new BranchInst(llvm_epilogues[I+1],
- llvm_epilogues[I]);
+ llvm_epilogues[I]);
}
else {
//Find where we are supposed to branch to
BasicBlock *nextBlock = 0;
for(unsigned j=0; j <branchVal->getNumSuccessors(); ++j) {
- if(branchVal->getSuccessor(j) != BB->getBasicBlock())
- nextBlock = branchVal->getSuccessor(j);
+ if(branchVal->getSuccessor(j) != BB->getBasicBlock())
+ nextBlock = branchVal->getSuccessor(j);
}
assert((nextBlock != 0) && "Next block should not be null!");
//Update the terminator
TerminatorInst *term = ((BasicBlock*)*P)->getTerminator();
for(unsigned i=0; i < term->getNumSuccessors(); ++i) {
- if(term->getSuccessor(i) == llvmBB) {
- DEBUG(std::cerr << "Replacing successor bb\n");
- if(llvm_prologues.size() > 0) {
- term->setSuccessor(i, llvm_prologues[0]);
- //Also update its corresponding machine instruction
- MachineCodeForInstruction & tempMvec =
- MachineCodeForInstruction::get(term);
- for (unsigned j = 0; j < tempMvec.size(); j++) {
- MachineInstr *temp = tempMvec[j];
- MachineOpCode opc = temp->getOpcode();
- if(TMI->isBranch(opc)) {
- DEBUG(std::cerr << *temp << "\n");
- //Update branch
- for(unsigned opNum = 0; opNum < temp->getNumOperands(); ++opNum) {
- MachineOperand &mOp = temp->getOperand(opNum);
- if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
- if(mOp.getVRegValue() == llvmBB)
- mOp.setValueReg(llvm_prologues[0]);
- }
- }
- }
- }
- }
- else {
- term->setSuccessor(i, llvmKernelBB);
- //Also update its corresponding machine instruction
- MachineCodeForInstruction & tempMvec =
- MachineCodeForInstruction::get(term);
- for (unsigned j = 0; j < tempMvec.size(); j++) {
- MachineInstr *temp = tempMvec[j];
- MachineOpCode opc = temp->getOpcode();
- if(TMI->isBranch(opc)) {
- DEBUG(std::cerr << *temp << "\n");
- //Update branch
- for(unsigned opNum = 0; opNum < temp->getNumOperands(); ++opNum) {
- MachineOperand &mOp = temp->getOperand(opNum);
- if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
- if(mOp.getVRegValue() == llvmBB)
- mOp.setValueReg(llvmKernelBB);
- }
- }
- }
- }
- }
- }
+ if(term->getSuccessor(i) == llvmBB) {
+ DEBUG(std::cerr << "Replacing successor bb\n");
+ if(llvm_prologues.size() > 0) {
+ term->setSuccessor(i, llvm_prologues[0]);
+ //Also update its corresponding machine instruction
+ MachineCodeForInstruction & tempMvec =
+ MachineCodeForInstruction::get(term);
+ for (unsigned j = 0; j < tempMvec.size(); j++) {
+ MachineInstr *temp = tempMvec[j];
+ MachineOpCode opc = temp->getOpcode();
+ if(TMI->isBranch(opc)) {
+ DEBUG(std::cerr << *temp << "\n");
+ //Update branch
+ for(unsigned opNum = 0; opNum < temp->getNumOperands(); ++opNum) {
+ MachineOperand &mOp = temp->getOperand(opNum);
+ if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
+ if(mOp.getVRegValue() == llvmBB)
+ mOp.setValueReg(llvm_prologues[0]);
+ }
+ }
+ }
+ }
+ }
+ else {
+ term->setSuccessor(i, llvmKernelBB);
+ //Also update its corresponding machine instruction
+ MachineCodeForInstruction & tempMvec =
+ MachineCodeForInstruction::get(term);
+ for (unsigned j = 0; j < tempMvec.size(); j++) {
+ MachineInstr *temp = tempMvec[j];
+ MachineOpCode opc = temp->getOpcode();
+ if(TMI->isBranch(opc)) {
+ DEBUG(std::cerr << *temp << "\n");
+ //Update branch
+ for(unsigned opNum = 0; opNum < temp->getNumOperands(); ++opNum) {
+ MachineOperand &mOp = temp->getOperand(opNum);
+ if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
+ if(mOp.getVRegValue() == llvmBB)
+ mOp.setValueReg(llvmKernelBB);
+ }
+ }
+ }
+ }
+ }
+ }
}
break;
}
int depth;
int height;
MSNodeAttributes(int asap=-1, int alap=-1, int mob=-1,
- int d=-1, int h=-1) : ASAP(asap), ALAP(alap),
- MOB(mob), depth(d),
- height(h) {}
+ int d=-1, int h=-1) : ASAP(asap), ALAP(alap),
+ MOB(mob), depth(d),
+ height(h) {}
};
bool CreateDefMap(MachineBasicBlock *BI);
bool MachineBBisValid(const MachineBasicBlock *BI);
bool assocIndVar(Instruction *I, std::set<Instruction*> &indVar,
- std::vector<Instruction*> &stack, BasicBlock *BB);
+ std::vector<Instruction*> &stack, BasicBlock *BB);
int calculateResMII(const MachineBasicBlock *BI);
int calculateRecMII(MSchedGraph *graph, int MII);
void calculateNodeAttributes(MSchedGraph *graph, int MII);
int findMaxASAP();
void orderNodes();
void findAllReccurrences(MSchedGraphNode *node,
- std::vector<MSchedGraphNode*> &visitedNodes, int II);
+ std::vector<MSchedGraphNode*> &visitedNodes, int II);
void addReccurrence(std::vector<MSchedGraphNode*> &recurrence, int II, MSchedGraphNode*, MSchedGraphNode*);
void addSCC(std::vector<MSchedGraphNode*> &SCC, std::map<MSchedGraphNode*, MSchedGraphNode*> &newNodes);
void findAllCircuits(MSchedGraph *MSG, int II);
bool circuit(MSchedGraphNode *v, std::vector<MSchedGraphNode*> &stack,
- std::set<MSchedGraphNode*> &blocked,
- std::vector<MSchedGraphNode*> &SCC, MSchedGraphNode *s,
- std::map<MSchedGraphNode*, std::set<MSchedGraphNode*> > &B, int II,
- std::map<MSchedGraphNode*, MSchedGraphNode*> &newNodes);
+ std::set<MSchedGraphNode*> &blocked,
+ std::vector<MSchedGraphNode*> &SCC, MSchedGraphNode *s,
+ std::map<MSchedGraphNode*, std::set<MSchedGraphNode*> > &B, int II,
+ std::map<MSchedGraphNode*, MSchedGraphNode*> &newNodes);
void unblock(MSchedGraphNode *u, std::set<MSchedGraphNode*> &blocked,
- std::map<MSchedGraphNode*, std::set<MSchedGraphNode*> > &B);
+ std::map<MSchedGraphNode*, std::set<MSchedGraphNode*> > &B);
void addRecc(std::vector<MSchedGraphNode*> &stack, std::map<MSchedGraphNode*, MSchedGraphNode*> &newNodes);
- void searchPath(MSchedGraphNode *node,
- std::vector<MSchedGraphNode*> &path,
- std::set<MSchedGraphNode*> &nodesToAdd,
- std::set<MSchedGraphNode*> &new_reccurence);
+ void searchPath(MSchedGraphNode *node,
+ std::vector<MSchedGraphNode*> &path,
+ std::set<MSchedGraphNode*> &nodesToAdd,
+ std::set<MSchedGraphNode*> &new_reccurence);
void pathToRecc(MSchedGraphNode *node,
- std::vector<MSchedGraphNode*> &path,
- std::set<MSchedGraphNode*> &poSet, std::set<MSchedGraphNode*> &lastNodes);
+ std::vector<MSchedGraphNode*> &path,
+ std::set<MSchedGraphNode*> &poSet, std::set<MSchedGraphNode*> &lastNodes);
void computePartialOrder();
bool computeSchedule(const MachineBasicBlock *BB, MSchedGraph *MSG);
- bool scheduleNode(MSchedGraphNode *node,
- int start, int end);
+ bool scheduleNode(MSchedGraphNode *node,
+ int start, int end);
void predIntersect(std::set<MSchedGraphNode*> &CurrentSet, std::set<MSchedGraphNode*> &IntersectResult);
void succIntersect(std::set<MSchedGraphNode*> &CurrentSet, std::set<MSchedGraphNode*> &IntersectResult);
/// before we run.
AU.addRequired<LoopInfo>();
AU.addRequired<ScalarEvolution>();
-
+
AU.addRequired<DependenceAnalyzer>();
}
Statistic<> NumSB("moduloschedSB-numSuperBlocks", "Total Number of SuperBlocks");
Statistic<> BBWithCalls("modulosched-BBCalls", "Basic Blocks rejected due to calls");
Statistic<> BBWithCondMov("modulosched-loopCondMov",
- "Basic Blocks rejected due to conditional moves");
+ "Basic Blocks rejected due to conditional moves");
Statistic<> SBResourceConstraint("modulosched-resourceConstraint",
- "Loops constrained by resources");
+ "Loops constrained by resources");
Statistic<> SBRecurrenceConstraint("modulosched-recurrenceConstraint",
- "Loops constrained by recurrences");
+ "Loops constrained by recurrences");
Statistic<> SBFinalIISum("modulosched-finalIISum", "Sum of all final II");
Statistic<> SBIISum("modulosched-IISum", "Sum of all theoretical II");
Statistic<> SBMSLoops("modulosched-schedLoops", "Number of loops successfully modulo-scheduled");
static std::string getNodeLabel(MSchedGraphSBNode *Node, MSchedGraphSB *Graph) {
if(!Node->isPredicate()) {
- if (Node->getInst()) {
- std::stringstream ss;
- ss << *(Node->getInst());
- return ss.str(); //((MachineInstr*)Node->getInst());
- }
- else
- return "No Inst";
+ if (Node->getInst()) {
+ std::stringstream ss;
+ ss << *(Node->getInst());
+ return ss.str(); //((MachineInstr*)Node->getInst());
+ }
+ else
+ return "No Inst";
}
else
- return "Pred Node";
+ return "Pred Node";
}
static std::string getEdgeSourceLabel(MSchedGraphSBNode *Node,
- MSchedGraphSBNode::succ_iterator I) {
+ MSchedGraphSBNode::succ_iterator I) {
//Label each edge with the type of dependence
std::string edgelabel = "";
switch (I.getEdge().getDepOrderType()) {
-
+
case MSchedGraphSBEdge::TrueDep:
- edgelabel = "True";
- break;
+ edgelabel = "True";
+ break;
case MSchedGraphSBEdge::AntiDep:
- edgelabel = "Anti";
- break;
-
+ edgelabel = "Anti";
+ break;
+
case MSchedGraphSBEdge::OutputDep:
- edgelabel = "Output";
- break;
-
+ edgelabel = "Output";
+ break;
+
case MSchedGraphSBEdge::NonDataDep:
- edgelabel = "Pred";
- break;
+ edgelabel = "Pred";
+ break;
default:
- edgelabel = "Unknown";
- break;
+ edgelabel = "Unknown";
+ break;
}
//FIXME
//Loop over worklist and ModuloSchedule each SuperBlock
for(std::vector<std::vector<const MachineBasicBlock*> >::iterator SB = Worklist.begin(),
- SBE = Worklist.end(); SB != SBE; ++SB) {
+ SBE = Worklist.end(); SB != SBE; ++SB) {
//Print out Superblock
DEBUG(std::cerr << "ModuloScheduling SB: \n";
- for(std::vector<const MachineBasicBlock*>::const_iterator BI = SB->begin(),
- BE = SB->end(); BI != BE; ++BI) {
- (*BI)->print(std::cerr);});
+ for(std::vector<const MachineBasicBlock*>::const_iterator BI = SB->begin(),
+ BE = SB->end(); BI != BE; ++BI) {
+ (*BI)->print(std::cerr);});
if(!CreateDefMap(*SB)) {
- defaultInst = 0;
- defMap.clear();
- continue;
+ defaultInst = 0;
+ defMap.clear();
+ continue;
}
MSchedGraphSB *MSG = new MSchedGraphSB(*SB, target, indVarInstrs[*SB], DA,
- machineTollvm[*SB]);
+ machineTollvm[*SB]);
//Write Graph out to file
DEBUG(WriteGraphToFileSB(std::cerr, F.getName(), MSG));
//Our starting initiation interval is the maximum of RecMII and ResMII
if(RecMII < ResMII)
- ++SBRecurrenceConstraint;
+ ++SBRecurrenceConstraint;
else
- ++SBResourceConstraint;
+ ++SBResourceConstraint;
II = std::max(RecMII, ResMII);
int mII = II;
//Dump node properties if in debug mode
DEBUG(for(std::map<MSchedGraphSBNode*, MSNodeSBAttributes>::iterator I = nodeToAttributesMap.begin(),
- E = nodeToAttributesMap.end(); I !=E; ++I) {
- std::cerr << "Node: " << *(I->first) << " ASAP: " << I->second.ASAP << " ALAP: "
- << I->second.ALAP << " MOB: " << I->second.MOB << " Depth: " << I->second.depth
- << " Height: " << I->second.height << "\n";
- });
+ E = nodeToAttributesMap.end(); I !=E; ++I) {
+ std::cerr << "Node: " << *(I->first) << " ASAP: " << I->second.ASAP << " ALAP: "
+ << I->second.ALAP << " MOB: " << I->second.MOB << " Depth: " << I->second.depth
+ << " Height: " << I->second.height << "\n";
+ });
//Put nodes in order to schedule them
//Dump out partial order
DEBUG(for(std::vector<std::set<MSchedGraphSBNode*> >::iterator I = partialOrder.begin(),
- E = partialOrder.end(); I !=E; ++I) {
- std::cerr << "Start set in PO\n";
- for(std::set<MSchedGraphSBNode*>::iterator J = I->begin(), JE = I->end(); J != JE; ++J)
- std::cerr << "PO:" << **J << "\n";
- });
+ E = partialOrder.end(); I !=E; ++I) {
+ std::cerr << "Start set in PO\n";
+ for(std::set<MSchedGraphSBNode*>::iterator J = I->begin(), JE = I->end(); J != JE; ++J)
+ std::cerr << "PO:" << **J << "\n";
+ });
//Place nodes in final order
orderNodes();
//Dump out order of nodes
DEBUG(for(std::vector<MSchedGraphSBNode*>::iterator I = FinalNodeOrder.begin(), E = FinalNodeOrder.end(); I != E; ++I) {
- std::cerr << "FO:" << **I << "\n";
- });
+ std::cerr << "FO:" << **I << "\n";
+ });
//Finally schedule nodes
//Final scheduling step is to reconstruct the loop only if we actual have
//stage > 0
if(haveSched) {
- //schedule.printSchedule(std::cerr);
- reconstructLoop(*SB);
- ++SBMSLoops;
- //Changed = true;
- SBIISum += mII;
- SBFinalIISum += II;
-
+ //schedule.printSchedule(std::cerr);
+ reconstructLoop(*SB);
+ ++SBMSLoops;
+ //Changed = true;
+ SBIISum += mII;
+ SBFinalIISum += II;
+
if(schedule.getMaxStage() == 0)
- ++SBSameStage;
+ ++SBSameStage;
}
else
- ++SBNoSched;
+ ++SBNoSched;
//Clear out our maps for the next basic block that is processed
nodeToAttributesMap.clear();
}
void ModuloSchedulingSBPass::FindSuperBlocks(Function &F, LoopInfo &LI,
- std::vector<std::vector<const MachineBasicBlock*> > &Worklist) {
+ std::vector<std::vector<const MachineBasicBlock*> > &Worklist) {
//Get MachineFunction
MachineFunction &MF = MachineFunction::get(&F);
//If loop is not single entry, try the next one
if(!L->getLoopPreheader())
- continue;
+ continue;
//Check size of this loop, we don't want SBB loops
if(L->getBlocks().size() == 1)
- continue;
+ continue;
//Check if this loop contains no sub loops
if(L->getSubLoops().size() == 0) {
-
- std::vector<const MachineBasicBlock*> superBlock;
-
- //Get Loop Headers
- BasicBlock *header = L->getHeader();
-
- //Follow the header and make sure each BB only has one entry and is valid
- BasicBlock *current = header;
- assert(bbMap.count(current) && "LLVM BB must have corresponding Machine BB\n");
- MachineBasicBlock *currentMBB = bbMap[header];
- bool done = false;
- bool success = true;
- unsigned offset = 0;
- std::map<const MachineInstr*, unsigned> indexMap;
-
- while(!done) {
- //Loop over successors of this BB, they should be in the
- //loop block and be valid
- BasicBlock *next = 0;
- for(succ_iterator I = succ_begin(current), E = succ_end(current);
- I != E; ++I) {
- if(L->contains(*I)) {
- if(!next)
- next = *I;
- else {
- done = true;
- success = false;
- break;
- }
- }
- }
-
- if(success) {
- superBlock.push_back(currentMBB);
- if(next == header)
- done = true;
- else if(!next->getSinglePredecessor()) {
- done = true;
- success = false;
- }
- else {
- //Check that the next BB only has one entry
- current = next;
- assert(bbMap.count(current) && "LLVM BB must have corresponding Machine BB");
- currentMBB = bbMap[current];
- }
- }
- }
-
-
-
-
-
- if(success) {
- ++NumSB;
-
- //Loop over all the blocks in the superblock
- for(std::vector<const MachineBasicBlock*>::iterator currentMBB = superBlock.begin(), MBBEnd = superBlock.end(); currentMBB != MBBEnd; ++currentMBB) {
- if(!MachineBBisValid(*currentMBB, indexMap, offset)) {
- success = false;
- break;
- }
- }
- }
-
- if(success) {
- if(getIndVar(superBlock, bbMap, indexMap)) {
- ++SBValid;
- Worklist.push_back(superBlock);
- SBSize += superBlock.size();
- }
- else
- ++SBInvalid;
- }
+
+ std::vector<const MachineBasicBlock*> superBlock;
+
+ //Get Loop Headers
+ BasicBlock *header = L->getHeader();
+
+ //Follow the header and make sure each BB only has one entry and is valid
+ BasicBlock *current = header;
+ assert(bbMap.count(current) && "LLVM BB must have corresponding Machine BB\n");
+ MachineBasicBlock *currentMBB = bbMap[header];
+ bool done = false;
+ bool success = true;
+ unsigned offset = 0;
+ std::map<const MachineInstr*, unsigned> indexMap;
+
+ while(!done) {
+ //Loop over successors of this BB, they should be in the
+ //loop block and be valid
+ BasicBlock *next = 0;
+ for(succ_iterator I = succ_begin(current), E = succ_end(current);
+ I != E; ++I) {
+ if(L->contains(*I)) {
+ if(!next)
+ next = *I;
+ else {
+ done = true;
+ success = false;
+ break;
+ }
+ }
+ }
+
+ if(success) {
+ superBlock.push_back(currentMBB);
+ if(next == header)
+ done = true;
+ else if(!next->getSinglePredecessor()) {
+ done = true;
+ success = false;
+ }
+ else {
+ //Check that the next BB only has one entry
+ current = next;
+ assert(bbMap.count(current) && "LLVM BB must have corresponding Machine BB");
+ currentMBB = bbMap[current];
+ }
+ }
+ }
+
+
+
+
+
+ if(success) {
+ ++NumSB;
+
+ //Loop over all the blocks in the superblock
+ for(std::vector<const MachineBasicBlock*>::iterator currentMBB = superBlock.begin(), MBBEnd = superBlock.end(); currentMBB != MBBEnd; ++currentMBB) {
+ if(!MachineBBisValid(*currentMBB, indexMap, offset)) {
+ success = false;
+ break;
+ }
+ }
+ }
+
+ if(success) {
+ if(getIndVar(superBlock, bbMap, indexMap)) {
+ ++SBValid;
+ Worklist.push_back(superBlock);
+ SBSize += superBlock.size();
+ }
+ else
+ ++SBInvalid;
+ }
}
}
}
bool ModuloSchedulingSBPass::getIndVar(std::vector<const MachineBasicBlock*> &superBlock, std::map<BasicBlock*, MachineBasicBlock*> &bbMap,
- std::map<const MachineInstr*, unsigned> &indexMap) {
+ std::map<const MachineInstr*, unsigned> &indexMap) {
//See if we can get induction var instructions
std::set<const BasicBlock*> llvmSuperBlock;
indVar.insert(b);
if(Instruction *I = dyn_cast<Instruction>(cond))
- if(bbMap.count(I->getParent())) {
- if (!assocIndVar(I, indVar, stack, bbMap, superBlock[(superBlock.size()-1)]->getBasicBlock(), llvmSuperBlock))
- return false;
- }
- else
- return false;
+ if(bbMap.count(I->getParent())) {
+ if (!assocIndVar(I, indVar, stack, bbMap, superBlock[(superBlock.size()-1)]->getBasicBlock(), llvmSuperBlock))
+ return false;
+ }
+ else
+ return false;
else
- return false;
+ return false;
}
else {
indVar.insert(b);
//Dump out instructions associate with indvar for debug reasons
DEBUG(for(std::set<Instruction*>::iterator N = indVar.begin(), NE = indVar.end();
- N != NE; ++N) {
- std::cerr << **N << "\n";
- });
+ N != NE; ++N) {
+ std::cerr << **N << "\n";
+ });
//Create map of machine instr to llvm instr
std::map<MachineInstr*, Instruction*> mllvm;
for(std::vector<const MachineBasicBlock*>::iterator MBB = superBlock.begin(), MBE = superBlock.end(); MBB != MBE; ++MBB) {
BasicBlock *BB = (BasicBlock*) (*MBB)->getBasicBlock();
for(BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) {
- MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(I);
- for (unsigned j = 0; j < tempMvec.size(); j++) {
- mllvm[tempMvec[j]] = I;
- }
+ MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(I);
+ for (unsigned j = 0; j < tempMvec.size(); j++) {
+ mllvm[tempMvec[j]] = I;
+ }
}
}
//Convert list of LLVM Instructions to list of Machine instructions
std::map<const MachineInstr*, unsigned> mIndVar;
for(std::set<Instruction*>::iterator N = indVar.begin(),
- NE = indVar.end(); N != NE; ++N) {
-
- //If we have a load, we can't handle this loop because
- //there is no way to preserve dependences between loads
- //and stores
- if(isa<LoadInst>(*N))
- return false;
-
- MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(*N);
- for (unsigned j = 0; j < tempMvec.size(); j++) {
- MachineOpCode OC = (tempMvec[j])->getOpcode();
- if(TMI->isNop(OC))
- continue;
- if(!indexMap.count(tempMvec[j]))
- continue;
- mIndVar[(MachineInstr*) tempMvec[j]] = indexMap[(MachineInstr*) tempMvec[j]];
- DEBUG(std::cerr << *(tempMvec[j]) << " at index " << indexMap[(MachineInstr*) tempMvec[j]] << "\n");
- }
+ NE = indVar.end(); N != NE; ++N) {
+
+ //If we have a load, we can't handle this loop because
+ //there is no way to preserve dependences between loads
+ //and stores
+ if(isa<LoadInst>(*N))
+ return false;
+
+ MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(*N);
+ for (unsigned j = 0; j < tempMvec.size(); j++) {
+ MachineOpCode OC = (tempMvec[j])->getOpcode();
+ if(TMI->isNop(OC))
+ continue;
+ if(!indexMap.count(tempMvec[j]))
+ continue;
+ mIndVar[(MachineInstr*) tempMvec[j]] = indexMap[(MachineInstr*) tempMvec[j]];
+ DEBUG(std::cerr << *(tempMvec[j]) << " at index " << indexMap[(MachineInstr*) tempMvec[j]] << "\n");
+ }
}
//Put into a map for future access
}
bool ModuloSchedulingSBPass::assocIndVar(Instruction *I,
- std::set<Instruction*> &indVar,
- std::vector<Instruction*> &stack,
- std::map<BasicBlock*, MachineBasicBlock*> &bbMap,
- const BasicBlock *last, std::set<const BasicBlock*> &llvmSuperBlock) {
+ std::set<Instruction*> &indVar,
+ std::vector<Instruction*> &stack,
+ std::map<BasicBlock*, MachineBasicBlock*> &bbMap,
+ const BasicBlock *last, std::set<const BasicBlock*> &llvmSuperBlock) {
stack.push_back(I);
//If this is a phi node, check if its the canonical indvar
if(PHINode *PN = dyn_cast<PHINode>(I)) {
if(llvmSuperBlock.count(PN->getParent())) {
- if (Instruction *Inc =
- dyn_cast<Instruction>(PN->getIncomingValueForBlock(last)))
- if (Inc->getOpcode() == Instruction::Add && Inc->getOperand(0) == PN)
- if (ConstantInt *CI = dyn_cast<ConstantInt>(Inc->getOperand(1)))
- if (CI->equalsInt(1)) {
- //We have found the indvar, so add the stack, and inc instruction to the set
- indVar.insert(stack.begin(), stack.end());
- indVar.insert(Inc);
- stack.pop_back();
- return true;
- }
- return false;
+ if (Instruction *Inc =
+ dyn_cast<Instruction>(PN->getIncomingValueForBlock(last)))
+ if (Inc->getOpcode() == Instruction::Add && Inc->getOperand(0) == PN)
+ if (ConstantInt *CI = dyn_cast<ConstantInt>(Inc->getOperand(1)))
+ if (CI->equalsInt(1)) {
+ //We have found the indvar, so add the stack, and inc instruction to the set
+ indVar.insert(stack.begin(), stack.end());
+ indVar.insert(Inc);
+ stack.pop_back();
+ return true;
+ }
+ return false;
}
}
else {
//Loop over each of the instructions operands, check if they are an instruction and in this BB
for(unsigned i = 0; i < I->getNumOperands(); ++i) {
- if(Instruction *N = dyn_cast<Instruction>(I->getOperand(i))) {
- if(bbMap.count(N->getParent()))
- if(!assocIndVar(N, indVar, stack, bbMap, last, llvmSuperBlock))
- return false;
- }
+ if(Instruction *N = dyn_cast<Instruction>(I->getOperand(i))) {
+ if(bbMap.count(N->getParent()))
+ if(!assocIndVar(N, indVar, stack, bbMap, last, llvmSuperBlock))
+ return false;
+ }
}
}
/// calls) in the block. Currently ModuloScheduling only works on
/// single basic block loops.
bool ModuloSchedulingSBPass::MachineBBisValid(const MachineBasicBlock *BI,
- std::map<const MachineInstr*, unsigned> &indexMap,
- unsigned &offset) {
+ std::map<const MachineInstr*, unsigned> &indexMap,
+ unsigned &offset) {
//Check size of our basic block.. make sure we have more then just the terminator in it
if(BI->getBasicBlock()->size() == 1)
//Look for calls
if(TMI->isCall(OC)) {
- ++BBWithCalls;
- return false;
+ ++BBWithCalls;
+ return false;
}
//Look for conditional move
if(OC == V9::MOVRZr || OC == V9::MOVRZi || OC == V9::MOVRLEZr || OC == V9::MOVRLEZi
- || OC == V9::MOVRLZr || OC == V9::MOVRLZi || OC == V9::MOVRNZr || OC == V9::MOVRNZi
- || OC == V9::MOVRGZr || OC == V9::MOVRGZi || OC == V9::MOVRGEZr
- || OC == V9::MOVRGEZi || OC == V9::MOVLEr || OC == V9::MOVLEi || OC == V9::MOVLEUr
- || OC == V9::MOVLEUi || OC == V9::MOVFLEr || OC == V9::MOVFLEi
- || OC == V9::MOVNEr || OC == V9::MOVNEi || OC == V9::MOVNEGr || OC == V9::MOVNEGi
- || OC == V9::MOVFNEr || OC == V9::MOVFNEi) {
- ++BBWithCondMov;
- return false;
+ || OC == V9::MOVRLZr || OC == V9::MOVRLZi || OC == V9::MOVRNZr || OC == V9::MOVRNZi
+ || OC == V9::MOVRGZr || OC == V9::MOVRGZi || OC == V9::MOVRGEZr
+ || OC == V9::MOVRGEZi || OC == V9::MOVLEr || OC == V9::MOVLEi || OC == V9::MOVLEUr
+ || OC == V9::MOVLEUi || OC == V9::MOVFLEr || OC == V9::MOVFLEi
+ || OC == V9::MOVNEr || OC == V9::MOVNEi || OC == V9::MOVNEGr || OC == V9::MOVNEGi
+ || OC == V9::MOVFNEr || OC == V9::MOVFNEi) {
+ ++BBWithCondMov;
+ return false;
}
indexMap[I] = count + offset;
if(TMI->isNop(OC))
- continue;
+ continue;
++count;
}
defaultInst = 0;
for(std::vector<const MachineBasicBlock*>::iterator BI = SB.begin(),
- BE = SB.end(); BI != BE; ++BI) {
+ BE = SB.end(); BI != BE; ++BI) {
for(MachineBasicBlock::const_iterator I = (*BI)->begin(), E = (*BI)->end(); I != E; ++I) {
for(unsigned opNum = 0; opNum < I->getNumOperands(); ++opNum) {
- const MachineOperand &mOp = I->getOperand(opNum);
- if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef()) {
- Value *V = mOp.getVRegValue();
- //assert if this is the second def we have seen
- if(defMap.count(V) && isa<PHINode>(V))
- DEBUG(std::cerr << "FIXME: Dup def for phi!\n");
- else {
- //assert(!defMap.count(V) && "Def already in the map");
- if(defMap.count(V))
- return false;
- defMap[V] = (MachineInstr*) &*I;
- }
- }
-
- //See if we can use this Value* as our defaultInst
- if(!defaultInst && mOp.getType() == MachineOperand::MO_VirtualRegister) {
- Value *V = mOp.getVRegValue();
- if(!isa<TmpInstruction>(V) && !isa<Argument>(V) && !isa<Constant>(V) && !isa<PHINode>(V))
- defaultInst = (Instruction*) V;
- }
+ const MachineOperand &mOp = I->getOperand(opNum);
+ if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef()) {
+ Value *V = mOp.getVRegValue();
+ //assert if this is the second def we have seen
+
if(defMap.count(V) && isa<PHINode>(V))
+ DEBUG(std::cerr << "FIXME: Dup def for phi!\n");
+ else {
+ //assert(!defMap.count(V) && "Def already in the map");
+ if(defMap.count(V))
+ return false;
+ defMap[V] = (MachineInstr*) &*I;
+ }
+ }
+
+ //See if we can use this Value* as our defaultInst
+ if(!defaultInst && mOp.getType() == MachineOperand::MO_VirtualRegister) {
+ Value *V = mOp.getVRegValue();
+
if(!isa<TmpInstruction>(V) && !isa<Argument>(V) && !isa<Constant>(V) && !isa<PHINode>(V))
+ defaultInst = (Instruction*) V;
+ }
}
}
}
//Loop over resources in each cycle and increments their usage count
for(unsigned i=0; i < resources.size(); ++i)
- for(unsigned j=0; j < resources[i].size(); ++j) {
- if(!resourceUsageCount.count(resources[i][j])) {
- resourceUsageCount[resources[i][j]] = 1;
- }
- else {
- resourceUsageCount[resources[i][j]] = resourceUsageCount[resources[i][j]] + 1;
- }
- }
+ for(unsigned j=0; j < resources[i].size(); ++j) {
+ if(!resourceUsageCount.count(resources[i][j])) {
+ resourceUsageCount[resources[i][j]] = 1;
+ }
+ else {
+ resourceUsageCount[resources[i][j]] = resourceUsageCount[resources[i][j]] + 1;
+ }
+ }
}
}
int CircCountSB;
void ModuloSchedulingSBPass::unblock(MSchedGraphSBNode *u, std::set<MSchedGraphSBNode*> &blocked,
- std::map<MSchedGraphSBNode*, std::set<MSchedGraphSBNode*> > &B) {
+ std::map<MSchedGraphSBNode*, std::set<MSchedGraphSBNode*> > &B) {
//Unblock u
DEBUG(std::cerr << "Unblocking: " << *u << "\n");
for(unsigned i = 0; i < (*N)->succ_size(); ++i) {
MSchedGraphSBEdge *edge = (*N)->getSuccessor(i);
if(find(SCC.begin(), SCC.end(), edge->getDest()) != SCC.end()) {
- totalDistance += edge->getIteDiff();
- if(edge->getIteDiff() > 0)
- if(!start && !end) {
- start = *N;
- end = edge->getDest();
- }
-
+ totalDistance += edge->getIteDiff();
+ if(edge->getIteDiff() > 0)
+ if(!start && !end) {
+ start = *N;
+ end = edge->getDest();
+ }
+
}
}
assert( (start && end) && "Must have start and end node to ignore edge for SCC");
- if(start && end) {
+ if(start && end) {
//Insert reccurrence into the list
DEBUG(std::cerr << "Ignore Edge from!!: " << *start << " to " << *end << "\n");
edgesToIgnore.insert(std::make_pair(newNodes[start], (newNodes[end])->getInEdgeNum(newNodes[start])));
}
bool ModuloSchedulingSBPass::circuit(MSchedGraphSBNode *v, std::vector<MSchedGraphSBNode*> &stack,
- std::set<MSchedGraphSBNode*> &blocked, std::vector<MSchedGraphSBNode*> &SCC,
- MSchedGraphSBNode *s, std::map<MSchedGraphSBNode*, std::set<MSchedGraphSBNode*> > &B,
- int II, std::map<MSchedGraphSBNode*, MSchedGraphSBNode*> &newNodes) {
+ std::set<MSchedGraphSBNode*> &blocked, std::vector<MSchedGraphSBNode*> &SCC,
+ MSchedGraphSBNode *s, std::map<MSchedGraphSBNode*, std::set<MSchedGraphSBNode*> > &B,
+ int II, std::map<MSchedGraphSBNode*, MSchedGraphSBNode*> &newNodes) {
bool f = false;
DEBUG(std::cerr << "Finding Circuits Starting with: ( " << v << ")"<< *v << "\n");
}
else if(!blocked.count(*I)) {
if(circuit(*I, stack, blocked, SCC, s, B, II, newNodes))
- f = true;
+ f = true;
}
else
DEBUG(std::cerr << "Blocked: " << **I << "\n");
std::vector<MSchedGraphSBNode*> recc;
//Dump recurrence for now
DEBUG(std::cerr << "Starting Recc\n");
-
+
int totalDelay = 0;
int totalDistance = 0;
MSchedGraphSBNode *lastN = 0;
totalDistance += iteDiff;
if(iteDiff > 0) {
- start = lastN;
- end = *N;
+ start = lastN;
+ end = *N;
}
}
//Get the original node
DEBUG(std::cerr << "End Recc\n");
CircCountSB++;
- if(start && end) {
+ if(start && end) {
//Insert reccurrence into the list
DEBUG(std::cerr << "Ignore Edge from!!: " << *start << " to " << *end << "\n");
edgesToIgnore.insert(std::make_pair(newNodes[start], (newNodes[end])->getInEdgeNum(newNodes[start])));
int value = totalDelay-(RecMII * totalDistance);
int lastII = II;
while(value < 0) {
-
+
lastII = RecMII;
RecMII--;
value = totalDelay-(RecMII * totalDistance);
//Find scc with the least vertex
for (MSchedGraphSB::iterator GI = MSG->begin(), E = MSG->end(); GI != E; ++GI)
if (Visited.insert(GI->second).second) {
- for (scc_iterator<MSchedGraphSBNode*> SCCI = scc_begin(GI->second),
- E = scc_end(GI->second); SCCI != E; ++SCCI) {
- std::vector<MSchedGraphSBNode*> &nextSCC = *SCCI;
-
- if (Visited.insert(nextSCC[0]).second) {
- Visited.insert(nextSCC.begin()+1, nextSCC.end());
-
- if(nextSCC.size() > 1) {
- DEBUG(std::cerr << "SCC size: " << nextSCC.size() << "\n");
-
- for(unsigned i = 0; i < nextSCC.size(); ++i) {
- //Loop over successor and see if in scc, then count edge
- MSchedGraphSBNode *node = nextSCC[i];
- for(MSchedGraphSBNode::succ_iterator S = node->succ_begin(), SE = node->succ_end(); S != SE; ++S) {
- if(find(nextSCC.begin(), nextSCC.end(), *S) != nextSCC.end())
- numEdges++;
- }
- }
- DEBUG(std::cerr << "Num Edges: " << numEdges << "\n");
- }
-
- //Ignore self loops
- if(nextSCC.size() > 1) {
-
- //Get least vertex in Vk
- if(!s) {
- s = nextSCC[0];
- Vk = nextSCC;
- }
-
- for(unsigned i = 0; i < nextSCC.size(); ++i) {
- if(nextSCC[i] < s) {
- s = nextSCC[i];
- Vk = nextSCC;
- }
- }
- }
- }
- }
+ for (scc_iterator<MSchedGraphSBNode*> SCCI = scc_begin(GI->second),
+ E = scc_end(GI->second); SCCI != E; ++SCCI) {
+ std::vector<MSchedGraphSBNode*> &nextSCC = *SCCI;
+
+ if (Visited.insert(nextSCC[0]).second) {
+ Visited.insert(nextSCC.begin()+1, nextSCC.end());
+
+ if(nextSCC.size() > 1) {
+ DEBUG(std::cerr << "SCC size: " << nextSCC.size() << "\n");
+
+ for(unsigned i = 0; i < nextSCC.size(); ++i) {
+ //Loop over successor and see if in scc, then count edge
+ MSchedGraphSBNode *node = nextSCC[i];
+ for(MSchedGraphSBNode::succ_iterator S = node->succ_begin(), SE = node->succ_end(); S != SE; ++S) {
+ if(find(nextSCC.begin(), nextSCC.end(), *S) != nextSCC.end())
+ numEdges++;
+ }
+ }
+ DEBUG(std::cerr << "Num Edges: " << numEdges << "\n");
+ }
+
+ //Ignore self loops
+ if(nextSCC.size() > 1) {
+
+ //Get least vertex in Vk
+ if(!s) {
+ s = nextSCC[0];
+ Vk = nextSCC;
+ }
+
+ for(unsigned i = 0; i < nextSCC.size(); ++i) {
+ if(nextSCC[i] < s) {
+ s = nextSCC[i];
+ Vk = nextSCC;
+ }
+ }
+ }
+ }
+ }
}
//Process SCC
DEBUG(for(std::vector<MSchedGraphSBNode*>::iterator N = Vk.begin(), NE = Vk.end();
- N != NE; ++N) { std::cerr << *((*N)->getInst()); });
+ N != NE; ++N) { std::cerr << *((*N)->getInst()); });
//Iterate over all nodes in this scc
for(std::vector<MSchedGraphSBNode*>::iterator N = Vk.begin(), NE = Vk.end();
- N != NE; ++N) {
+ N != NE; ++N) {
blocked.erase(*N);
B[*N].clear();
}
if(Vk.size() > 1) {
if(numEdges < 98)
- circuit(s, stack, blocked, Vk, s, B, II, newNodes);
+ circuit(s, stack, blocked, Vk, s, B, II, newNodes);
else
- addSCC(Vk, newNodes);
+ addSCC(Vk, newNodes);
//Delete nodes from the graph
std::vector<MSchedGraphSBNode*> nodesToRemove;
nodesToRemove.push_back(s);
for(MSchedGraphSB::iterator N = MSG->begin(), NE = MSG->end(); N != NE; ++N) {
- if(N->second < s )
- nodesToRemove.push_back(N->second);
+ if(N->second < s )
+ nodesToRemove.push_back(N->second);
}
for(std::vector<MSchedGraphSBNode*>::iterator N = nodesToRemove.begin(), NE = nodesToRemove.end(); N != NE; ++N) {
- DEBUG(std::cerr << "Deleting Node: " << **N << "\n");
- MSG->deleteNode(*N);
+ DEBUG(std::cerr << "Deleting Node: " << **N << "\n");
+ MSG->deleteNode(*N);
}
}
else
//Assert if its already in the map
assert(nodeToAttributesMap.count(I->second) == 0 &&
- "Node attributes are already in the map");
+ "Node attributes are already in the map");
//Put into the map with default attribute values
nodeToAttributesMap[I->second] = MSNodeSBAttributes();
int ModuloSchedulingSBPass::calculateALAP(MSchedGraphSBNode *node, int MII,
- int maxASAP, MSchedGraphSBNode *srcNode) {
+ int maxASAP, MSchedGraphSBNode *srcNode) {
DEBUG(std::cerr << "Calculating ALAP for " << *node << "\n");
//Iterate over all of the predecessors and fine max
for(MSchedGraphSBNode::succ_iterator P = node->succ_begin(),
- E = node->succ_end(); P != E; ++P) {
+ E = node->succ_end(); P != E; ++P) {
//Only process if we are not ignoring the edge
if(!ignoreEdge(node, *P)) {
- processedOneEdge = true;
- int succALAP = -1;
- succALAP = calculateALAP(*P, MII, maxASAP, node);
-
- assert(succALAP != -1 && "Successors ALAP should have been caclulated");
-
- int iteDiff = P.getEdge().getIteDiff();
-
- int currentSuccValue = succALAP - node->getLatency() + iteDiff * MII;
-
- DEBUG(std::cerr << "succ ALAP: " << succALAP << ", iteDiff: " << iteDiff << ", SuccLatency: " << (*P)->getLatency() << ", Current ALAP succ: " << currentSuccValue << "\n");
-
- minSuccValue = std::min(minSuccValue, currentSuccValue);
+ processedOneEdge = true;
+ int succALAP = -1;
+ succALAP = calculateALAP(*P, MII, maxASAP, node);
+
+ assert(succALAP != -1 && "Successors ALAP should have been caclulated");
+
+ int iteDiff = P.getEdge().getIteDiff();
+
+ int currentSuccValue = succALAP - node->getLatency() + iteDiff * MII;
+
+ DEBUG(std::cerr << "succ ALAP: " << succALAP << ", iteDiff: " << iteDiff << ", SuccLatency: " << (*P)->getLatency() << ", Current ALAP succ: " << currentSuccValue << "\n");
+
+ minSuccValue = std::min(minSuccValue, currentSuccValue);
}
}
if(processedOneEdge)
- attributes.ALAP = minSuccValue;
+ attributes.ALAP = minSuccValue;
else
attributes.ALAP = maxASAP;
int maxASAP = 0;
for(std::map<MSchedGraphSBNode*, MSNodeSBAttributes>::iterator I = nodeToAttributesMap.begin(),
- E = nodeToAttributesMap.end(); I != E; ++I)
+ E = nodeToAttributesMap.end(); I != E; ++I)
maxASAP = std::max(maxASAP, I->second.ASAP);
return maxASAP;
}
//Iterate over all of the predecessors and find max
for(MSchedGraphSBNode::succ_iterator P = node->succ_begin(),
- E = node->succ_end(); P != E; ++P) {
+ E = node->succ_end(); P != E; ++P) {
if(!ignoreEdge(node, *P)) {
int ModuloSchedulingSBPass::calculateDepth(MSchedGraphSBNode *node,
- MSchedGraphSBNode *destNode) {
+ MSchedGraphSBNode *destNode) {
MSNodeSBAttributes &attributes = nodeToAttributesMap.find(node)->second;
//along with any nodes that connect this recurrence to recurrences
//already in the partial order
for(std::set<std::pair<int, std::vector<MSchedGraphSBNode*> > >::reverse_iterator
- I = recurrenceList.rbegin(), E=recurrenceList.rend(); I !=E; ++I) {
+ I = recurrenceList.rbegin(), E=recurrenceList.rend(); I !=E; ++I) {
std::set<MSchedGraphSBNode*> new_recurrence;
//Loop through recurrence and remove any nodes already in the partial order
for(std::vector<MSchedGraphSBNode*>::const_iterator N = I->second.begin(),
- NE = I->second.end(); N != NE; ++N) {
+ NE = I->second.end(); N != NE; ++N) {
bool found = false;
for(std::vector<std::set<MSchedGraphSBNode*> >::iterator PO = partialOrder.begin(),
- PE = partialOrder.end(); PO != PE; ++PO) {
- if(PO->count(*N))
- found = true;
+ PE = partialOrder.end(); PO != PE; ++PO) {
+ if(PO->count(*N))
+ found = true;
}
//Check if its a branch, and remove to handle special
if(!found) {
- new_recurrence.insert(*N);
+ new_recurrence.insert(*N);
}
}
//Add nodes that connect this recurrence to recurrences in the partial path
for(std::set<MSchedGraphSBNode*>::iterator N = new_recurrence.begin(),
NE = new_recurrence.end(); N != NE; ++N)
- searchPath(*N, path, nodesToAdd, new_recurrence);
+ searchPath(*N, path, nodesToAdd, new_recurrence);
//Add nodes to this recurrence if they are not already in the partial order
for(std::set<MSchedGraphSBNode*>::iterator N = nodesToAdd.begin(), NE = nodesToAdd.end();
- N != NE; ++N) {
- bool found = false;
- for(std::vector<std::set<MSchedGraphSBNode*> >::iterator PO = partialOrder.begin(),
- PE = partialOrder.end(); PO != PE; ++PO) {
- if(PO->count(*N))
- found = true;
- }
- if(!found) {
- assert("FOUND CONNECTOR");
- new_recurrence.insert(*N);
- }
+ N != NE; ++N) {
+ bool found = false;
+ for(std::vector<std::set<MSchedGraphSBNode*> >::iterator PO = partialOrder.begin(),
+ PE = partialOrder.end(); PO != PE; ++PO) {
+ if(PO->count(*N))
+ found = true;
+ }
+ if(!found) {
+ assert("FOUND CONNECTOR");
+ new_recurrence.insert(*N);
+ }
}
partialOrder.push_back(new_recurrence);
std::set<MSchedGraphSBNode*> lastNodes;
std::set<MSchedGraphSBNode*> noPredNodes;
for(std::map<MSchedGraphSBNode*, MSNodeSBAttributes>::iterator I = nodeToAttributesMap.begin(),
- E = nodeToAttributesMap.end(); I != E; ++I) {
+ E = nodeToAttributesMap.end(); I != E; ++I) {
bool found = false;
//Check if its already in our partial order, if not add it to the final vector
for(std::vector<std::set<MSchedGraphSBNode*> >::iterator PO = partialOrder.begin(),
- PE = partialOrder.end(); PO != PE; ++PO) {
+ PE = partialOrder.end(); PO != PE; ++PO) {
if(PO->count(I->first))
- found = true;
+ found = true;
}
if(!found)
lastNodes.insert(I->first);
N != NE; ++N) {
DEBUG(std::cerr << "No Pred Path from: " << **N << "\n");
for(std::vector<std::set<MSchedGraphSBNode*> >::iterator PO = partialOrder.begin(),
- PE = partialOrder.end(); PO != PE; ++PO) {
+ PE = partialOrder.end(); PO != PE; ++PO) {
std::vector<MSchedGraphSBNode*> path;
pathToRecc(*N, path, *PO, lastNodes);
}
std::set<MSchedGraphSBNode*> ccSet;
connectedComponentSet(*(lastNodes.begin()),ccSet, lastNodes);
if(ccSet.size() > 0)
- partialOrder.push_back(ccSet);
+ partialOrder.push_back(ccSet);
}
}
}
void ModuloSchedulingSBPass::searchPath(MSchedGraphSBNode *node,
- std::vector<MSchedGraphSBNode*> &path,
- std::set<MSchedGraphSBNode*> &nodesToAdd,
- std::set<MSchedGraphSBNode*> &new_reccurrence) {
+ std::vector<MSchedGraphSBNode*> &path,
+ std::set<MSchedGraphSBNode*> &nodesToAdd,
+ std::set<MSchedGraphSBNode*> &new_reccurrence) {
//Push node onto the path
path.push_back(node);
//final vector
bool found = false;
for(std::vector<std::set<MSchedGraphSBNode*> >::iterator PO = partialOrder.begin(),
- PE = partialOrder.end(); PO != PE; ++PO) {
+ PE = partialOrder.end(); PO != PE; ++PO) {
if(PO->count(*S)) {
- found = true;
- break;
+ found = true;
+ break;
}
}
/*for(std::vector<std::set<MSchedGraphSBNode*> >::iterator CurrentSet = partialOrder.begin(), E= partialOrder.end(); CurrentSet != E; ++CurrentSet) {
for(std::set<MSchedGraphSBNode*>::iterator N = CurrentSet->begin(), NE = CurrentSet->end(); N != NE; ++N)
if((*N)->isPredicate()) {
- FinalNodeOrder.push_back(*N);
- CurrentSet->erase(*N);
+ FinalNodeOrder.push_back(*N);
+ CurrentSet->erase(*N);
}
}*/
//sort top-down
if(IntersectCurrent.size() != 0) {
- DEBUG(std::cerr << "Final Node Order Successors and Current Set interesection is NOT empty\n");
- order = TOP_DOWN;
+ DEBUG(std::cerr << "Final Node Order Successors and Current Set interesection is NOT empty\n");
+ order = TOP_DOWN;
}
else {
- DEBUG(std::cerr << "Final Node Order Successors and Current Set interesection is empty\n");
- //Find node with max ASAP in current Set
- MSchedGraphSBNode *node;
- int maxASAP = 0;
- DEBUG(std::cerr << "Using current set of size " << CurrentSet->size() << "to find max ASAP\n");
- for(std::set<MSchedGraphSBNode*>::iterator J = CurrentSet->begin(), JE = CurrentSet->end(); J != JE; ++J) {
- //Get node attributes
- MSNodeSBAttributes nodeAttr= nodeToAttributesMap.find(*J)->second;
- //assert(nodeAttr != nodeToAttributesMap.end() && "Node not in attributes map!");
-
- if(maxASAP <= nodeAttr.ASAP) {
- maxASAP = nodeAttr.ASAP;
- node = *J;
- }
- }
- assert(node != 0 && "In node ordering node should not be null");
- IntersectCurrent.insert(node);
- order = BOTTOM_UP;
+ DEBUG(std::cerr << "Final Node Order Successors and Current Set interesection is empty\n");
+ //Find node with max ASAP in current Set
+ MSchedGraphSBNode *node;
+ int maxASAP = 0;
+ DEBUG(std::cerr << "Using current set of size " << CurrentSet->size() << "to find max ASAP\n");
+ for(std::set<MSchedGraphSBNode*>::iterator J = CurrentSet->begin(), JE = CurrentSet->end(); J != JE; ++J) {
+ //Get node attributes
+ MSNodeSBAttributes nodeAttr= nodeToAttributesMap.find(*J)->second;
+ //assert(nodeAttr != nodeToAttributesMap.end() && "Node not in attributes map!");
+
+ if(maxASAP <= nodeAttr.ASAP) {
+ maxASAP = nodeAttr.ASAP;
+ node = *J;
+ }
+ }
+ assert(node != 0 && "In node ordering node should not be null");
+ IntersectCurrent.insert(node);
+ order = BOTTOM_UP;
}
}
while(IntersectCurrent.size() > 0) {
if(order == TOP_DOWN) {
- DEBUG(std::cerr << "Order is TOP DOWN\n");
-
- while(IntersectCurrent.size() > 0) {
- DEBUG(std::cerr << "Intersection is not empty, so find heighest height\n");
-
- int MOB = 0;
- int height = 0;
- MSchedGraphSBNode *highestHeightNode = *(IntersectCurrent.begin());
-
- //Find node in intersection with highest heigh and lowest MOB
- for(std::set<MSchedGraphSBNode*>::iterator I = IntersectCurrent.begin(),
- E = IntersectCurrent.end(); I != E; ++I) {
-
- //Get current nodes properties
- MSNodeSBAttributes nodeAttr= nodeToAttributesMap.find(*I)->second;
-
- if(height < nodeAttr.height) {
- highestHeightNode = *I;
- height = nodeAttr.height;
- MOB = nodeAttr.MOB;
- }
- else if(height == nodeAttr.height) {
- if(MOB > nodeAttr.height) {
- highestHeightNode = *I;
- height = nodeAttr.height;
- MOB = nodeAttr.MOB;
- }
- }
- }
-
- //Append our node with greatest height to the NodeOrder
- if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), highestHeightNode) == FinalNodeOrder.end()) {
- DEBUG(std::cerr << "Adding node to Final Order: " << *highestHeightNode << "\n");
- FinalNodeOrder.push_back(highestHeightNode);
- }
-
- //Remove V from IntersectOrder
- IntersectCurrent.erase(std::find(IntersectCurrent.begin(),
- IntersectCurrent.end(), highestHeightNode));
-
-
- //Intersect V's successors with CurrentSet
- for(MSchedGraphSBNode::succ_iterator P = highestHeightNode->succ_begin(),
- E = highestHeightNode->succ_end(); P != E; ++P) {
- //if(lower_bound(CurrentSet->begin(),
- // CurrentSet->end(), *P) != CurrentSet->end()) {
- if(std::find(CurrentSet->begin(), CurrentSet->end(), *P) != CurrentSet->end()) {
- if(ignoreEdge(highestHeightNode, *P))
- continue;
- //If not already in Intersect, add
- if(!IntersectCurrent.count(*P))
- IntersectCurrent.insert(*P);
- }
- }
- } //End while loop over Intersect Size
-
- //Change direction
- order = BOTTOM_UP;
-
- //Reset Intersect to reflect changes in OrderNodes
- IntersectCurrent.clear();
- predIntersect(*CurrentSet, IntersectCurrent);
-
+ DEBUG(std::cerr << "Order is TOP DOWN\n");
+
+ while(IntersectCurrent.size() > 0) {
+ DEBUG(std::cerr << "Intersection is not empty, so find heighest height\n");
+
+ int MOB = 0;
+ int height = 0;
+ MSchedGraphSBNode *highestHeightNode = *(IntersectCurrent.begin());
+
+ //Find node in intersection with highest heigh and lowest MOB
+ for(std::set<MSchedGraphSBNode*>::iterator I = IntersectCurrent.begin(),
+ E = IntersectCurrent.end(); I != E; ++I) {
+
+ //Get current nodes properties
+ MSNodeSBAttributes nodeAttr= nodeToAttributesMap.find(*I)->second;
+
+ if(height < nodeAttr.height) {
+ highestHeightNode = *I;
+ height = nodeAttr.height;
+ MOB = nodeAttr.MOB;
+ }
+ else if(height == nodeAttr.height) {
+ if(MOB > nodeAttr.height) {
+ highestHeightNode = *I;
+ height = nodeAttr.height;
+ MOB = nodeAttr.MOB;
+ }
+ }
+ }
+
+ //Append our node with greatest height to the NodeOrder
+ if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), highestHeightNode) == FinalNodeOrder.end()) {
+ DEBUG(std::cerr << "Adding node to Final Order: " << *highestHeightNode << "\n");
+ FinalNodeOrder.push_back(highestHeightNode);
+ }
+
+ //Remove V from IntersectOrder
+ IntersectCurrent.erase(std::find(IntersectCurrent.begin(),
+ IntersectCurrent.end(), highestHeightNode));
+
+
+ //Intersect V's successors with CurrentSet
+ for(MSchedGraphSBNode::succ_iterator P = highestHeightNode->succ_begin(),
+ E = highestHeightNode->succ_end(); P != E; ++P) {
+ //if(lower_bound(CurrentSet->begin(),
+ // CurrentSet->end(), *P) != CurrentSet->end()) {
+ if(std::find(CurrentSet->begin(), CurrentSet->end(), *P) != CurrentSet->end()) {
+ if(ignoreEdge(highestHeightNode, *P))
+ continue;
+ //If not already in Intersect, add
+ if(!IntersectCurrent.count(*P))
+ IntersectCurrent.insert(*P);
+ }
+ }
+ } //End while loop over Intersect Size
+
+ //Change direction
+ order = BOTTOM_UP;
+
+ //Reset Intersect to reflect changes in OrderNodes
+ IntersectCurrent.clear();
+ predIntersect(*CurrentSet, IntersectCurrent);
+
} //End If TOP_DOWN
-
- //Begin if BOTTOM_UP
+
+ //Begin if BOTTOM_UP
else {
- DEBUG(std::cerr << "Order is BOTTOM UP\n");
- while(IntersectCurrent.size() > 0) {
- DEBUG(std::cerr << "Intersection of size " << IntersectCurrent.size() << ", finding highest depth\n");
-
- //dump intersection
- DEBUG(dumpIntersection(IntersectCurrent));
- //Get node with highest depth, if a tie, use one with lowest
- //MOB
- int MOB = 0;
- int depth = 0;
- MSchedGraphSBNode *highestDepthNode = *(IntersectCurrent.begin());
-
- for(std::set<MSchedGraphSBNode*>::iterator I = IntersectCurrent.begin(),
- E = IntersectCurrent.end(); I != E; ++I) {
- //Find node attribute in graph
- MSNodeSBAttributes nodeAttr= nodeToAttributesMap.find(*I)->second;
-
- if(depth < nodeAttr.depth) {
- highestDepthNode = *I;
- depth = nodeAttr.depth;
- MOB = nodeAttr.MOB;
- }
- else if(depth == nodeAttr.depth) {
- if(MOB > nodeAttr.MOB) {
- highestDepthNode = *I;
- depth = nodeAttr.depth;
- MOB = nodeAttr.MOB;
- }
- }
- }
-
-
-
- //Append highest depth node to the NodeOrder
- if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), highestDepthNode) == FinalNodeOrder.end()) {
- DEBUG(std::cerr << "Adding node to Final Order: " << *highestDepthNode << "\n");
- FinalNodeOrder.push_back(highestDepthNode);
- }
- //Remove heightestDepthNode from IntersectOrder
- IntersectCurrent.erase(highestDepthNode);
-
-
- //Intersect heightDepthNode's pred with CurrentSet
- for(MSchedGraphSBNode::pred_iterator P = highestDepthNode->pred_begin(),
- E = highestDepthNode->pred_end(); P != E; ++P) {
- if(CurrentSet->count(*P)) {
- if(ignoreEdge(*P, highestDepthNode))
- continue;
-
- //If not already in Intersect, add
- if(!IntersectCurrent.count(*P))
- IntersectCurrent.insert(*P);
- }
- }
-
- } //End while loop over Intersect Size
-
- //Change order
- order = TOP_DOWN;
-
- //Reset IntersectCurrent to reflect changes in OrderNodes
- IntersectCurrent.clear();
- succIntersect(*CurrentSet, IntersectCurrent);
- } //End if BOTTOM_DOWN
-
+ DEBUG(std::cerr << "Order is BOTTOM UP\n");
+ while(IntersectCurrent.size() > 0) {
+ DEBUG(std::cerr << "Intersection of size " << IntersectCurrent.size() << ", finding highest depth\n");
+
+ //dump intersection
+ DEBUG(dumpIntersection(IntersectCurrent));
+ //Get node with highest depth, if a tie, use one with lowest
+ //MOB
+ int MOB = 0;
+ int depth = 0;
+ MSchedGraphSBNode *highestDepthNode = *(IntersectCurrent.begin());
+
+ for(std::set<MSchedGraphSBNode*>::iterator I = IntersectCurrent.begin(),
+ E = IntersectCurrent.end(); I != E; ++I) {
+ //Find node attribute in graph
+ MSNodeSBAttributes nodeAttr= nodeToAttributesMap.find(*I)->second;
+
+ if(depth < nodeAttr.depth) {
+ highestDepthNode = *I;
+ depth = nodeAttr.depth;
+ MOB = nodeAttr.MOB;
+ }
+ else if(depth == nodeAttr.depth) {
+ if(MOB > nodeAttr.MOB) {
+ highestDepthNode = *I;
+ depth = nodeAttr.depth;
+ MOB = nodeAttr.MOB;
+ }
+ }
+ }
+
+
+
+ //Append highest depth node to the NodeOrder
+ if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), highestDepthNode) == FinalNodeOrder.end()) {
+ DEBUG(std::cerr << "Adding node to Final Order: " << *highestDepthNode << "\n");
+ FinalNodeOrder.push_back(highestDepthNode);
+ }
+ //Remove heightestDepthNode from IntersectOrder
+ IntersectCurrent.erase(highestDepthNode);
+
+
+ //Intersect heightDepthNode's pred with CurrentSet
+ for(MSchedGraphSBNode::pred_iterator P = highestDepthNode->pred_begin(),
+ E = highestDepthNode->pred_end(); P != E; ++P) {
+ if(CurrentSet->count(*P)) {
+ if(ignoreEdge(*P, highestDepthNode))
+ continue;
+
+ //If not already in Intersect, add
+ if(!IntersectCurrent.count(*P))
+ IntersectCurrent.insert(*P);
+ }
+ }
+
+ } //End while loop over Intersect Size
+
+ //Change order
+ order = TOP_DOWN;
+
+ //Reset IntersectCurrent to reflect changes in OrderNodes
+ IntersectCurrent.clear();
+ succIntersect(*CurrentSet, IntersectCurrent);
+ } //End if BOTTOM_DOWN
+
DEBUG(std::cerr << "Current Intersection Size: " << IntersectCurrent.size() << "\n");
}
//End Wrapping while loop
for(unsigned j=0; j < FinalNodeOrder.size(); ++j) {
for(MSchedGraphSBNode::pred_iterator P = FinalNodeOrder[j]->pred_begin(),
- E = FinalNodeOrder[j]->pred_end(); P != E; ++P) {
+ E = FinalNodeOrder[j]->pred_end(); P != E; ++P) {
//Check if we are supposed to ignore this edge or not
if(ignoreEdge(*P,FinalNodeOrder[j]))
- continue;
-
+ continue;
+
if(CurrentSet.count(*P))
- if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), *P) == FinalNodeOrder.end())
- IntersectResult.insert(*P);
+ if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), *P) == FinalNodeOrder.end())
+ IntersectResult.insert(*P);
}
}
}
for(unsigned j=0; j < FinalNodeOrder.size(); ++j) {
for(MSchedGraphSBNode::succ_iterator P = FinalNodeOrder[j]->succ_begin(),
- E = FinalNodeOrder[j]->succ_end(); P != E; ++P) {
+ E = FinalNodeOrder[j]->succ_end(); P != E; ++P) {
//Check if we are supposed to ignore this edge or not
if(ignoreEdge(FinalNodeOrder[j],*P))
- continue;
+ continue;
if(CurrentSet.count(*P))
- if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), *P) == FinalNodeOrder.end())
- IntersectResult.insert(*P);
+ if(std::find(FinalNodeOrder.begin(), FinalNodeOrder.end(), *P) == FinalNodeOrder.end())
+ IntersectResult.insert(*P);
}
}
}
//Loop over the final node order and process each node
for(std::vector<MSchedGraphSBNode*>::iterator I = FinalNodeOrder.begin(),
- E = FinalNodeOrder.end(); I != E; ++I) {
+ E = FinalNodeOrder.end(); I != E; ++I) {
//CalculateEarly and Late start
bool initialLSVal = false;
bool sched;
if((*I)->isBranch())
- if((*I)->hasPredecessors())
- sched = true;
- else
- sched = false;
+ if((*I)->hasPredecessors())
+ sched = true;
+ else
+ sched = false;
else
- sched = true;
+ sched = true;
if(sched) {
- //Loop over nodes in the schedule and determine if they are predecessors
- //or successors of the node we are trying to schedule
- for(MSScheduleSB::schedule_iterator nodesByCycle = schedule.begin(), nodesByCycleEnd = schedule.end();
- nodesByCycle != nodesByCycleEnd; ++nodesByCycle) {
-
- //For this cycle, get the vector of nodes schedule and loop over it
- for(std::vector<MSchedGraphSBNode*>::iterator schedNode = nodesByCycle->second.begin(), SNE = nodesByCycle->second.end(); schedNode != SNE; ++schedNode) {
-
- if((*I)->isPredecessor(*schedNode)) {
- int diff = (*I)->getInEdge(*schedNode).getIteDiff();
- int ES_Temp = nodesByCycle->first + (*schedNode)->getLatency() - diff * II;
- DEBUG(std::cerr << "Diff: " << diff << " Cycle: " << nodesByCycle->first << "\n");
- DEBUG(std::cerr << "Temp EarlyStart: " << ES_Temp << " Prev EarlyStart: " << EarlyStart << "\n");
- if(initialESVal)
- EarlyStart = std::max(EarlyStart, ES_Temp);
- else {
- EarlyStart = ES_Temp;
- initialESVal = true;
- }
- hasPred = true;
- }
- if((*I)->isSuccessor(*schedNode)) {
- int diff = (*schedNode)->getInEdge(*I).getIteDiff();
- int LS_Temp = nodesByCycle->first - (*I)->getLatency() + diff * II;
- DEBUG(std::cerr << "Diff: " << diff << " Cycle: " << nodesByCycle->first << "\n");
- DEBUG(std::cerr << "Temp LateStart: " << LS_Temp << " Prev LateStart: " << LateStart << "\n");
- if(initialLSVal)
- LateStart = std::min(LateStart, LS_Temp);
- else {
- LateStart = LS_Temp;
- initialLSVal = true;
- }
- hasSucc = true;
- }
- }
- }
+ //Loop over nodes in the schedule and determine if they are predecessors
+ //or successors of the node we are trying to schedule
+ for(MSScheduleSB::schedule_iterator nodesByCycle = schedule.begin(), nodesByCycleEnd = schedule.end();
+ nodesByCycle != nodesByCycleEnd; ++nodesByCycle) {
+
+ //For this cycle, get the vector of nodes schedule and loop over it
+ for(std::vector<MSchedGraphSBNode*>::iterator schedNode = nodesByCycle->second.begin(), SNE = nodesByCycle->second.end(); schedNode != SNE; ++schedNode) {
+
+ if((*I)->isPredecessor(*schedNode)) {
+ int diff = (*I)->getInEdge(*schedNode).getIteDiff();
+ int ES_Temp = nodesByCycle->first + (*schedNode)->getLatency() - diff * II;
+ DEBUG(std::cerr << "Diff: " << diff << " Cycle: " << nodesByCycle->first << "\n");
+ DEBUG(std::cerr << "Temp EarlyStart: " << ES_Temp << " Prev EarlyStart: " << EarlyStart << "\n");
+ if(initialESVal)
+ EarlyStart = std::max(EarlyStart, ES_Temp);
+ else {
+ EarlyStart = ES_Temp;
+ initialESVal = true;
+ }
+ hasPred = true;
+ }
+ if((*I)->isSuccessor(*schedNode)) {
+ int diff = (*schedNode)->getInEdge(*I).getIteDiff();
+ int LS_Temp = nodesByCycle->first - (*I)->getLatency() + diff * II;
+ DEBUG(std::cerr << "Diff: " << diff << " Cycle: " << nodesByCycle->first << "\n");
+ DEBUG(std::cerr << "Temp LateStart: " << LS_Temp << " Prev LateStart: " << LateStart << "\n");
+ if(initialLSVal)
+ LateStart = std::min(LateStart, LS_Temp);
+ else {
+ LateStart = LS_Temp;
+ initialLSVal = true;
+ }
+ hasSucc = true;
+ }
+ }
+ }
}
else {
- branches.push_back(*I);
- continue;
+ branches.push_back(*I);
+ continue;
}
//Check if the node has no pred or successors and set Early Start to its ASAP
if(!hasSucc && !hasPred)
- EarlyStart = nodeToAttributesMap.find(*I)->second.ASAP;
+ EarlyStart = nodeToAttributesMap.find(*I)->second.ASAP;
DEBUG(std::cerr << "Has Successors: " << hasSucc << ", Has Pred: " << hasPred << "\n");
DEBUG(std::cerr << "EarlyStart: " << EarlyStart << ", LateStart: " << LateStart << "\n");
//Now, try to schedule this node depending upon its pred and successor in the schedule
//already
if(!hasSucc && hasPred)
- success = scheduleNode(*I, EarlyStart, (EarlyStart + II -1));
+ success = scheduleNode(*I, EarlyStart, (EarlyStart + II -1));
else if(!hasPred && hasSucc)
- success = scheduleNode(*I, LateStart, (LateStart - II +1));
+ success = scheduleNode(*I, LateStart, (LateStart - II +1));
else if(hasPred && hasSucc) {
- if(EarlyStart > LateStart) {
- success = false;
- //LateStart = EarlyStart;
- DEBUG(std::cerr << "Early Start can not be later then the late start cycle, schedule fails\n");
- }
- else
- success = scheduleNode(*I, EarlyStart, std::min(LateStart, (EarlyStart + II -1)));
+ if(EarlyStart > LateStart) {
+ success = false;
+ //LateStart = EarlyStart;
+ DEBUG(std::cerr << "Early Start can not be later then the late start cycle, schedule fails\n");
+ }
+ else
+ success = scheduleNode(*I, EarlyStart, std::min(LateStart, (EarlyStart + II -1)));
}
else
- success = scheduleNode(*I, EarlyStart, EarlyStart + II - 1);
+ success = scheduleNode(*I, EarlyStart, EarlyStart + II - 1);
if(!success) {
- ++II;
- schedule.clear();
- break;
+ ++II;
+ schedule.clear();
+ break;
}
}
success = schedule.constructKernel(II, branches, indVarInstrs[SB]);
DEBUG(std::cerr << "Done Constructing Schedule Kernel\n");
if(!success) {
- ++II;
- schedule.clear();
+ ++II;
+ schedule.clear();
}
DEBUG(std::cerr << "Final II: " << II << "\n");
bool ModuloSchedulingSBPass::scheduleNode(MSchedGraphSBNode *node,
- int start, int end) {
+ int start, int end) {
bool success = false;
DEBUG(std::cerr << *node << " (Start Cycle: " << start << ", End Cycle: " << end << ")\n");
++cycle;
DEBUG(std::cerr << "Increase cycle: " << cycle << "\n");
if(cycle > end)
- return false;
+ return false;
}
else {
--cycle;
DEBUG(std::cerr << "Decrease cycle: " << cycle << "\n");
if(cycle < end)
- return false;
+ return false;
}
}
lastInstrs[inst] = I->second;
for(unsigned i=0; i < inst->getNumOperands(); ++i) {
- //get machine operand
- const MachineOperand &mOp = inst->getOperand(i);
-
- if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isUse()) {
- //find the value in the map
- if (const Value* srcI = mOp.getVRegValue()) {
-
- if(isa<Constant>(srcI) || isa<Argument>(srcI))
- continue;
-
- //Before we declare this Value* one that we should save
- //make sure its def is not of the same stage as this instruction
- //because it will be consumed before its used
- Instruction *defInst = (Instruction*) srcI;
-
- //Should we save this value?
- bool save = true;
-
- //Continue if not in the def map, loop invariant code does not need to be saved
- if(!defMap.count(srcI))
- continue;
-
- MachineInstr *defInstr = defMap[srcI];
-
-
- if(lastInstrs.count(defInstr)) {
- if(lastInstrs[defInstr] == I->second) {
- save = false;
-
- }
- }
-
- if(save)
- valuesToSave[srcI] = std::make_pair(I->first, i);
- }
- }
-
- if(mOp.getType() != MachineOperand::MO_VirtualRegister && mOp.isUse()) {
- assert("Our assumption is wrong. We have another type of register that needs to be saved\n");
- }
+ //get machine operand
+ const MachineOperand &mOp = inst->getOperand(i);
+
+ if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isUse()) {
+ //find the value in the map
+ if (const Value* srcI = mOp.getVRegValue()) {
+
+
if(isa<Constant>(srcI) || isa<Argument>(srcI))
+ continue;
+
+ //Before we declare this Value* one that we should save
+ //make sure its def is not of the same stage as this instruction
+ //because it will be consumed before its used
+ Instruction *defInst = (Instruction*) srcI;
+
+ //Should we save this value?
+ bool save = true;
+
+ //Continue if not in the def map, loop invariant code does not need to be saved
+ if(!defMap.count(srcI))
+ continue;
+
+ MachineInstr *defInstr = defMap[srcI];
+
+
+ if(lastInstrs.count(defInstr)) {
+ if(lastInstrs[defInstr] == I->second) {
+ save = false;
+
+ }
+ }
+
+ if(save)
+ valuesToSave[srcI] = std::make_pair(I->first, i);
+ }
+ }
+
+ if(mOp.getType() != MachineOperand::MO_VirtualRegister && mOp.isUse()) {
+ assert("Our assumption is wrong. We have another type of register that needs to be saved\n");
+ }
}
}
//Print out epilogues and prologue
DEBUG(for(std::vector<std::vector<MachineBasicBlock*> >::iterator PI = prologues.begin(), PE = prologues.end();
PI != PE; ++PI) {
- std::cerr << "PROLOGUE\n";
- for(std::vector<MachineBasicBlock*>::iterator I = PI->begin(), E = PI->end(); I != E; ++I)
- (*I)->print(std::cerr);
- });
+ std::cerr << "PROLOGUE\n";
+ for(std::vector<MachineBasicBlock*>::iterator I = PI->begin(), E = PI->end(); I != E; ++I)
+ (*I)->print(std::cerr);
+ });
DEBUG(std::cerr << "KERNEL\n");
DEBUG(for(std::vector<MachineBasicBlock*>::iterator I = machineKernelBBs.begin(), E = machineKernelBBs.end(); I != E; ++I) { (*I)->print(std::cerr);});
//Print out epilogues and prologue
DEBUG(for(std::vector<std::vector<MachineBasicBlock*> >::iterator PI = prologues.begin(), PE = prologues.end();
PI != PE; ++PI) {
- std::cerr << "PROLOGUE\n";
- for(std::vector<MachineBasicBlock*>::iterator I = PI->begin(), E = PI->end(); I != E; ++I)
- (*I)->print(std::cerr);
- });
+ std::cerr << "PROLOGUE\n";
+ for(std::vector<MachineBasicBlock*>::iterator I = PI->begin(), E = PI->end(); I != E; ++I)
+ (*I)->print(std::cerr);
+ });
DEBUG(std::cerr << "KERNEL\n");
DEBUG(for(std::vector<MachineBasicBlock*>::iterator I = machineKernelBBs.begin(), E = machineKernelBBs.end(); I != E; ++I) { (*I)->print(std::cerr);});
bool sawFirst = false;
for(succ_iterator I = succ_begin(last),
- E = succ_end(last); I != E; ++I) {
+ E = succ_end(last); I != E; ++I) {
if (*I != SB[0]->getBasicBlock()) {
kernel_exit = *I;
break;
for(unsigned j = 0; j < prologues[i].size(); ++j) {
- MachineBasicBlock *currentMBB = prologues[i][j];
+ MachineBasicBlock *currentMBB = prologues[i][j];
- //Find terminator since getFirstTerminator does not work!
- for(MachineBasicBlock::reverse_iterator mInst = currentMBB->rbegin(), mInstEnd = currentMBB->rend(); mInst != mInstEnd; ++mInst) {
- MachineOpCode OC = mInst->getOpcode();
- //If its a branch update its branchto
- if(TMI->isBranch(OC)) {
- for(unsigned opNum = 0; opNum < mInst->getNumOperands(); ++opNum) {
- MachineOperand &mOp = mInst->getOperand(opNum);
- if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
- //Check if we are branching to the kernel, if not branch to epilogue
- if(mOp.getVRegValue() == SB[0]->getBasicBlock()) {
- if(i >= prologues.size()-1)
- mOp.setValueReg(llvmKernelBB[0]);
- else
- mOp.setValueReg(llvm_prologues[i+1][0]);
- }
- else if( (mOp.getVRegValue() == kernel_exit) && (j == prologues[i].size()-1)) {
- mOp.setValueReg(llvm_epilogues[i][0]);
- }
- else if(mOp.getVRegValue() == SB[j+1]->getBasicBlock()) {
- mOp.setValueReg(llvm_prologues[i][j+1]);
- }
-
- }
- }
-
- DEBUG(std::cerr << "New Prologue Branch: " << *mInst << "\n");
- }
- }
-
- //Update llvm basic block with our new branch instr
- DEBUG(std::cerr << SB[i]->getBasicBlock()->getTerminator() << "\n");
-
- const BranchInst *branchVal = dyn_cast<BranchInst>(SB[i]->getBasicBlock()->getTerminator());
-
- //Check for inner branch
- if(j < prologues[i].size()-1) {
- //Find our side exit LLVM basic block
- BasicBlock *sideExit = 0;
- for(unsigned s = 0; s < branchVal->getNumSuccessors(); ++s) {
- if(branchVal->getSuccessor(s) != SB[i+1]->getBasicBlock())
- sideExit = branchVal->getSuccessor(s);
- }
- assert(sideExit && "Must have side exit llvm basic block");
- TerminatorInst *newBranch = new BranchInst(sideExit,
- llvm_prologues[i][j+1],
- branchVal->getCondition(),
- llvm_prologues[i][j]);
- }
- else {
- //If last prologue
- if(i == prologues.size()-1) {
- TerminatorInst *newBranch = new BranchInst(llvmKernelBB[0],
- llvm_epilogues[i][0],
- branchVal->getCondition(),
- llvm_prologues[i][j]);
- }
- else {
- TerminatorInst *newBranch = new BranchInst(llvm_prologues[i+1][0],
- llvm_epilogues[i][0],
- branchVal->getCondition(),
- llvm_prologues[i][j]);
- }
- }
+ //Find terminator since getFirstTerminator does not work!
+ for(MachineBasicBlock::reverse_iterator mInst = currentMBB->rbegin(), mInstEnd = currentMBB->rend(); mInst != mInstEnd; ++mInst) {
+ MachineOpCode OC = mInst->getOpcode();
+ //If its a branch update its branchto
+ if(TMI->isBranch(OC)) {
+ for(unsigned opNum = 0; opNum < mInst->getNumOperands(); ++opNum) {
+ MachineOperand &mOp = mInst->getOperand(opNum);
+ if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
+ //Check if we are branching to the kernel, if not branch to epilogue
+ if(mOp.getVRegValue() == SB[0]->getBasicBlock()) {
+ if(i >= prologues.size()-1)
+ mOp.setValueReg(llvmKernelBB[0]);
+ else
+ mOp.setValueReg(llvm_prologues[i+1][0]);
+ }
+ else if( (mOp.getVRegValue() == kernel_exit) && (j == prologues[i].size()-1)) {
+ mOp.setValueReg(llvm_epilogues[i][0]);
+ }
+ else if(mOp.getVRegValue() == SB[j+1]->getBasicBlock()) {
+ mOp.setValueReg(llvm_prologues[i][j+1]);
+ }
+
+ }
+ }
+
+ DEBUG(std::cerr << "New Prologue Branch: " << *mInst << "\n");
+ }
+ }
+
+ //Update llvm basic block with our new branch instr
+ DEBUG(std::cerr << SB[i]->getBasicBlock()->getTerminator() << "\n");
+
+ const BranchInst *branchVal = dyn_cast<BranchInst>(SB[i]->getBasicBlock()->getTerminator());
+
+ //Check for inner branch
+ if(j < prologues[i].size()-1) {
+ //Find our side exit LLVM basic block
+ BasicBlock *sideExit = 0;
+ for(unsigned s = 0; s < branchVal->getNumSuccessors(); ++s) {
+ if(branchVal->getSuccessor(s) != SB[i+1]->getBasicBlock())
+ sideExit = branchVal->getSuccessor(s);
+ }
+ assert(sideExit && "Must have side exit llvm basic block");
+ TerminatorInst *newBranch = new BranchInst(sideExit,
+ llvm_prologues[i][j+1],
+ branchVal->getCondition(),
+ llvm_prologues[i][j]);
+ }
+ else {
+ //If last prologue
+ if(i == prologues.size()-1) {
+ TerminatorInst *newBranch = new BranchInst(llvmKernelBB[0],
+ llvm_epilogues[i][0],
+ branchVal->getCondition(),
+ llvm_prologues[i][j]);
+ }
+ else {
+ TerminatorInst *newBranch = new BranchInst(llvm_prologues[i+1][0],
+ llvm_epilogues[i][0],
+ branchVal->getCondition(),
+ llvm_prologues[i][j]);
+ }
+ }
}
}
}
for(MachineBasicBlock::reverse_iterator mInst = currentMBB->rbegin(), mInstEnd = currentMBB->rend(); mInst != mInstEnd; ++mInst) {
MachineOpCode OC = mInst->getOpcode();
if(TMI->isBranch(OC)) {
- for(unsigned opNum = 0; opNum < mInst->getNumOperands(); ++opNum) {
- MachineOperand &mOp = mInst->getOperand(opNum);
-
- if(mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
- //Deal with inner kernel branches
- if(i < machineKernelBB.size()-1) {
- if(mOp.getVRegValue() == SB[i+1]->getBasicBlock())
- mOp.setValueReg(llvmKernelBB[i+1]);
- //Side exit!
- else {
- sideExits[SB[i]] = mOp.getVRegValue();
- }
- }
- else {
- if(mOp.getVRegValue() == SB[0]->getBasicBlock())
- mOp.setValueReg(llvmKernelBB[0]);
- else {
- if(llvm_epilogues.size() > 0)
- mOp.setValueReg(llvm_epilogues[0][0]);
- }
- }
- }
- }
+ for(unsigned opNum = 0; opNum < mInst->getNumOperands(); ++opNum) {
+ MachineOperand &mOp = mInst->getOperand(opNum);
+
+ if(mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
+ //Deal with inner kernel branches
+ if(i < machineKernelBB.size()-1) {
+ if(mOp.getVRegValue() == SB[i+1]->getBasicBlock())
+ mOp.setValueReg(llvmKernelBB[i+1]);
+ //Side exit!
+ else {
+ sideExits[SB[i]] = mOp.getVRegValue();
+ }
+ }
+ else {
+ if(mOp.getVRegValue() == SB[0]->getBasicBlock())
+ mOp.setValueReg(llvmKernelBB[0]);
+ else {
+ if(llvm_epilogues.size() > 0)
+ mOp.setValueReg(llvm_epilogues[0][0]);
+ }
+ }
+ }
+ }
}
}
//Find our side exit LLVM basic block
BasicBlock *sideExit = 0;
for(unsigned s = 0; s < branchVal->getNumSuccessors(); ++s) {
- if(branchVal->getSuccessor(s) != SB[i+1]->getBasicBlock())
- sideExit = branchVal->getSuccessor(s);
+ if(branchVal->getSuccessor(s) != SB[i+1]->getBasicBlock())
+ sideExit = branchVal->getSuccessor(s);
}
assert(sideExit && "Must have side exit llvm basic block");
TerminatorInst *newBranch = new BranchInst(sideExit,
- llvmKernelBB[i+1],
- branchVal->getCondition(),
- llvmKernelBB[i]);
+ llvmKernelBB[i+1],
+ branchVal->getCondition(),
+ llvmKernelBB[i]);
}
else {
//Deal with outter branches
if(epilogues.size() > 0) {
- TerminatorInst *newBranch = new BranchInst(llvmKernelBB[0],
- llvm_epilogues[0][0],
- branchVal->getCondition(),
- llvmKernelBB[i]);
+ TerminatorInst *newBranch = new BranchInst(llvmKernelBB[0],
+ llvm_epilogues[0][0],
+ branchVal->getCondition(),
+ llvmKernelBB[i]);
}
else {
- TerminatorInst *newBranch = new BranchInst(llvmKernelBB[0],
- kernel_exit,
- branchVal->getCondition(),
- llvmKernelBB[i]);
+ TerminatorInst *newBranch = new BranchInst(llvmKernelBB[0],
+ kernel_exit,
+ branchVal->getCondition(),
+ llvmKernelBB[i]);
}
}
}
for(unsigned i = 0; i < epilogues.size(); ++i) {
for(unsigned j=0; j < epilogues[i].size(); ++j) {
- //Now since we don't have fall throughs, add a unconditional
- //branch to the next prologue
-
- //Before adding these, we need to check if the epilogue already has
- //a branch in it
- bool hasBranch = false;
- /*if(j < epilogues[i].size()-1) {
- MachineBasicBlock *currentMBB = epilogues[i][j];
- for(MachineBasicBlock::reverse_iterator mInst = currentMBB->rbegin(), mInstEnd = currentMBB->rend(); mInst != mInstEnd; ++mInst) {
-
- MachineOpCode OC = mInst->getOpcode();
-
- //If its a branch update its branchto
- if(TMI->isBranch(OC)) {
- hasBranch = true;
- for(unsigned opNum = 0; opNum < mInst->getNumOperands(); ++opNum) {
- MachineOperand &mOp = mInst->getOperand(opNum);
- if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
-
- if(mOp.getVRegValue() != sideExits[SB[j]]) {
- mOp.setValueReg(llvm_epilogues[i][j+1]);
- }
-
- }
- }
-
-
- DEBUG(std::cerr << "New Epilogue Branch: " << *mInst << "\n");
- }
- }
- if(hasBranch) {
- const BranchInst *branchVal = dyn_cast<BranchInst>(SB[j]->getBasicBlock()->getTerminator());
- TerminatorInst *newBranch = new BranchInst((BasicBlock*)sideExits[SB[j]],
- llvm_epilogues[i][j+1],
- branchVal->getCondition(),
- llvm_epilogues[i][j]);
- }
- }*/
-
- if(!hasBranch) {
-
- //Handle inner branches
- if(j < epilogues[i].size()-1) {
- BuildMI(epilogues[i][j], V9::BA, 1).addPCDisp(llvm_epilogues[i][j+1]);
- TerminatorInst *newBranch = new BranchInst(llvm_epilogues[i][j+1],
- llvm_epilogues[i][j]);
- }
- else {
-
- //Check if this is the last epilogue
- if(i != epilogues.size()-1) {
- BuildMI(epilogues[i][j], V9::BA, 1).addPCDisp(llvm_epilogues[i+1][0]);
- //Add unconditional branch to end of epilogue
- TerminatorInst *newBranch = new BranchInst(llvm_epilogues[i+1][0],
- llvm_epilogues[i][j]);
-
- }
- else {
- BuildMI(epilogues[i][j], V9::BA, 1).addPCDisp(kernel_exit);
- TerminatorInst *newBranch = new BranchInst(kernel_exit, llvm_epilogues[i][j]);
- }
- }
-
- //Add one more nop!
- BuildMI(epilogues[i][j], V9::NOP, 0);
-
- }
+ //Now since we don't have fall throughs, add a unconditional
+ //branch to the next prologue
+
+ //Before adding these, we need to check if the epilogue already has
+ //a branch in it
+ bool hasBranch = false;
+ /*if(j < epilogues[i].size()-1) {
+ MachineBasicBlock *currentMBB = epilogues[i][j];
+ for(MachineBasicBlock::reverse_iterator mInst = currentMBB->rbegin(), mInstEnd = currentMBB->rend(); mInst != mInstEnd; ++mInst) {
+
+ MachineOpCode OC = mInst->getOpcode();
+
+ //If its a branch update its branchto
+ if(TMI->isBranch(OC)) {
+ hasBranch = true;
+ for(unsigned opNum = 0; opNum < mInst->getNumOperands(); ++opNum) {
+ MachineOperand &mOp = mInst->getOperand(opNum);
+ if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
+
+ if(mOp.getVRegValue() != sideExits[SB[j]]) {
+ mOp.setValueReg(llvm_epilogues[i][j+1]);
+ }
+
+ }
+ }
+
+
+ DEBUG(std::cerr << "New Epilogue Branch: " << *mInst << "\n");
+ }
+ }
+ if(hasBranch) {
+ const BranchInst *branchVal = dyn_cast<BranchInst>(SB[j]->getBasicBlock()->getTerminator());
+ TerminatorInst *newBranch = new BranchInst((BasicBlock*)sideExits[SB[j]],
+ llvm_epilogues[i][j+1],
+ branchVal->getCondition(),
+ llvm_epilogues[i][j]);
+ }
+ }*/
+
+ if(!hasBranch) {
+
+ //Handle inner branches
+ if(j < epilogues[i].size()-1) {
+ BuildMI(epilogues[i][j], V9::BA, 1).addPCDisp(llvm_epilogues[i][j+1]);
+ TerminatorInst *newBranch = new BranchInst(llvm_epilogues[i][j+1],
+ llvm_epilogues[i][j]);
+ }
+ else {
+
+ //Check if this is the last epilogue
+ if(i != epilogues.size()-1) {
+ BuildMI(epilogues[i][j], V9::BA, 1).addPCDisp(llvm_epilogues[i+1][0]);
+ //Add unconditional branch to end of epilogue
+ TerminatorInst *newBranch = new BranchInst(llvm_epilogues[i+1][0],
+ llvm_epilogues[i][j]);
+
+ }
+ else {
+ BuildMI(epilogues[i][j], V9::BA, 1).addPCDisp(kernel_exit);
+ TerminatorInst *newBranch = new BranchInst(kernel_exit, llvm_epilogues[i][j]);
+ }
+ }
+
+ //Add one more nop!
+ BuildMI(epilogues[i][j], V9::NOP, 0);
+
+ }
}
}
}
std::vector<const BasicBlock*>Preds (pred_begin(llvmBB), pred_end(llvmBB));
for(std::vector<const BasicBlock*>::iterator P = Preds.begin(),
- PE = Preds.end(); P != PE; ++P) {
+ PE = Preds.end(); P != PE; ++P) {
if(*P == SB[SB.size()-1]->getBasicBlock())
continue;
else {
//Update the terminator
TerminatorInst *term = ((BasicBlock*)*P)->getTerminator();
for(unsigned i=0; i < term->getNumSuccessors(); ++i) {
- if(term->getSuccessor(i) == llvmBB) {
- DEBUG(std::cerr << "Replacing successor bb\n");
- if(llvm_prologues.size() > 0) {
- term->setSuccessor(i, llvm_prologues[0][0]);
-
- DEBUG(std::cerr << "New Term" << *((*P)->getTerminator()) << "\n");
-
- //Also update its corresponding machine instruction
- MachineCodeForInstruction & tempMvec =
- MachineCodeForInstruction::get(term);
- for (unsigned j = 0; j < tempMvec.size(); j++) {
- MachineInstr *temp = tempMvec[j];
- MachineOpCode opc = temp->getOpcode();
- if(TMI->isBranch(opc)) {
- DEBUG(std::cerr << *temp << "\n");
- //Update branch
- for(unsigned opNum = 0; opNum < temp->getNumOperands(); ++opNum) {
- MachineOperand &mOp = temp->getOperand(opNum);
- if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
- if(mOp.getVRegValue() == llvmBB)
- mOp.setValueReg(llvm_prologues[0][0]);
- }
- }
- }
- }
- }
- else {
- term->setSuccessor(i, llvmKernelBB[0]);
-
- //Also update its corresponding machine instruction
- MachineCodeForInstruction & tempMvec =
- MachineCodeForInstruction::get(term);
- for(unsigned j = 0; j < tempMvec.size(); j++) {
- MachineInstr *temp = tempMvec[j];
- MachineOpCode opc = temp->getOpcode();
- if(TMI->isBranch(opc)) {
- DEBUG(std::cerr << *temp << "\n");
- //Update branch
- for(unsigned opNum = 0; opNum < temp->getNumOperands(); ++opNum) {
- MachineOperand &mOp = temp->getOperand(opNum);
- if(mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
- if(mOp.getVRegValue() == llvmBB)
- mOp.setValueReg(llvmKernelBB[0]);
- }
- }
- }
- }
- }
- }
+ if(term->getSuccessor(i) == llvmBB) {
+ DEBUG(std::cerr << "Replacing successor bb\n");
+ if(llvm_prologues.size() > 0) {
+ term->setSuccessor(i, llvm_prologues[0][0]);
+
+ DEBUG(std::cerr << "New Term" << *((*P)->getTerminator()) << "\n");
+
+ //Also update its corresponding machine instruction
+ MachineCodeForInstruction & tempMvec =
+ MachineCodeForInstruction::get(term);
+ for (unsigned j = 0; j < tempMvec.size(); j++) {
+ MachineInstr *temp = tempMvec[j];
+ MachineOpCode opc = temp->getOpcode();
+ if(TMI->isBranch(opc)) {
+ DEBUG(std::cerr << *temp << "\n");
+ //Update branch
+ for(unsigned opNum = 0; opNum < temp->getNumOperands(); ++opNum) {
+ MachineOperand &mOp = temp->getOperand(opNum);
+ if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
+ if(mOp.getVRegValue() == llvmBB)
+ mOp.setValueReg(llvm_prologues[0][0]);
+ }
+ }
+ }
+ }
+ }
+ else {
+ term->setSuccessor(i, llvmKernelBB[0]);
+
+ //Also update its corresponding machine instruction
+ MachineCodeForInstruction & tempMvec =
+ MachineCodeForInstruction::get(term);
+ for(unsigned j = 0; j < tempMvec.size(); j++) {
+ MachineInstr *temp = tempMvec[j];
+ MachineOpCode opc = temp->getOpcode();
+ if(TMI->isBranch(opc)) {
+ DEBUG(std::cerr << *temp << "\n");
+ //Update branch
+ for(unsigned opNum = 0; opNum < temp->getNumOperands(); ++opNum) {
+ MachineOperand &mOp = temp->getOperand(opNum);
+ if(mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
+ if(mOp.getVRegValue() == llvmBB)
+ mOp.setValueReg(llvmKernelBB[0]);
+ }
+ }
+ }
+ }
+ }
+ }
}
break;
}
std::vector<BasicBlock*> current_llvm_prologue;
for(std::vector<const MachineBasicBlock*>::iterator MB = origSB.begin(),
- MBE = origSB.end(); MB != MBE; ++MB) {
+ MBE = origSB.end(); MB != MBE; ++MB) {
const MachineBasicBlock *MBB = *MB;
//Create new llvm and machine bb
BasicBlock *llvmBB = new BasicBlock("PROLOGUE", (Function*) (MBB->getBasicBlock()->getParent()));
DEBUG(std::cerr << "i=" << i << "\n");
for(int j = i; j >= 0; --j) {
- //iterate over instructions in original bb
- for(MachineBasicBlock::const_iterator MI = MBB->begin(),
- ME = MBB->end(); ME != MI; ++MI) {
- if(inKernel[j].count(&*MI)) {
- MachineInstr *instClone = MI->clone();
- machineBB->push_back(instClone);
-
- //If its a branch, insert a nop
- if(mii->isBranch(instClone->getOpcode()))
- BuildMI(machineBB, V9::NOP, 0);
-
-
- DEBUG(std::cerr << "Cloning: " << *MI << "\n");
-
- //After cloning, we may need to save the value that this instruction defines
- for(unsigned opNum=0; opNum < MI->getNumOperands(); ++opNum) {
- Instruction *tmp;
-
- //get machine operand
- MachineOperand &mOp = instClone->getOperand(opNum);
- if(mOp.getType() == MachineOperand::MO_VirtualRegister
- && mOp.isDef()) {
-
- //Check if this is a value we should save
- if(valuesToSave.count(mOp.getVRegValue())) {
- //Save copy in tmpInstruction
- tmp = new TmpInstruction(mOp.getVRegValue());
-
- //Add TmpInstruction to safe LLVM Instruction MCFI
- MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst);
- tempMvec.addTemp((Value*) tmp);
-
- DEBUG(std::cerr << "Value: " << *(mOp.getVRegValue())
- << " New Value: " << *tmp << " Stage: " << i << "\n");
-
- newValues[mOp.getVRegValue()][i]= tmp;
- newValLocation[tmp] = machineBB;
-
- DEBUG(std::cerr << "Machine Instr Operands: "
- << *(mOp.getVRegValue()) << ", 0, " << *tmp << "\n");
-
- //Create machine instruction and put int machineBB
- MachineInstr *saveValue;
- if(mOp.getVRegValue()->getType() == Type::FloatTy)
- saveValue = BuildMI(machineBB, V9::FMOVS, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
- else if(mOp.getVRegValue()->getType() == Type::DoubleTy)
- saveValue = BuildMI(machineBB, V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
- else
- saveValue = BuildMI(machineBB, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp);
-
-
- DEBUG(std::cerr << "Created new machine instr: " << *saveValue << "\n");
- }
- }
-
- //We may also need to update the value that we use if
- //its from an earlier prologue
- if(j != 0) {
- if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isUse()) {
- if(newValues.count(mOp.getVRegValue())) {
- if(newValues[mOp.getVRegValue()].count(i-1)) {
- Value *oldV = mOp.getVRegValue();
- DEBUG(std::cerr << "Replaced this value: " << mOp.getVRegValue() << " With:" << (newValues[mOp.getVRegValue()][i-1]) << "\n");
- //Update the operand with the right value
- mOp.setValueReg(newValues[mOp.getVRegValue()][i-1]);
-
- //Remove this value since we have consumed it
- //NOTE: Should this only be done if j != maxStage?
- consumedValues[oldV][i-1] = (newValues[oldV][i-1]);
- DEBUG(std::cerr << "Deleted value: " << consumedValues[oldV][i-1] << "\n");
- newValues[oldV].erase(i-1);
- }
- }
- else
- if(consumedValues.count(mOp.getVRegValue()))
- assert(!consumedValues[mOp.getVRegValue()].count(i-1) && "Found a case where we need the value");
- }
- }
- }
- }
- }
+ //iterate over instructions in original bb
+ for(MachineBasicBlock::const_iterator MI = MBB->begin(),
+ ME = MBB->end(); ME != MI; ++MI) {
+ if(inKernel[j].count(&*MI)) {
+ MachineInstr *instClone = MI->clone();
+ machineBB->push_back(instClone);
+
+ //If its a branch, insert a nop
+ if(mii->isBranch(instClone->getOpcode()))
+ BuildMI(machineBB, V9::NOP, 0);
+
+
+ DEBUG(std::cerr << "Cloning: " << *MI << "\n");
+
+ //After cloning, we may need to save the value that this instruction defines
+ for(unsigned opNum=0; opNum < MI->getNumOperands(); ++opNum) {
+ Instruction *tmp;
+
+ //get machine operand
+ MachineOperand &mOp = instClone->getOperand(opNum);
+ if(mOp.getType() == MachineOperand::MO_VirtualRegister
+ && mOp.isDef()) {
+
+ //Check if this is a value we should save
+ if(valuesToSave.count(mOp.getVRegValue())) {
+ //Save copy in tmpInstruction
+ tmp = new TmpInstruction(mOp.getVRegValue());
+
+ //Add TmpInstruction to safe LLVM Instruction MCFI
+ MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst);
+ tempMvec.addTemp((Value*) tmp);
+
+ DEBUG(std::cerr << "Value: " << *(mOp.getVRegValue())
+ << " New Value: " << *tmp << " Stage: " << i << "\n");
+
+ newValues[mOp.getVRegValue()][i]= tmp;
+ newValLocation[tmp] = machineBB;
+
+ DEBUG(std::cerr << "Machine Instr Operands: "
+ << *(mOp.getVRegValue()) << ", 0, " << *tmp << "\n");
+
+ //Create machine instruction and put int machineBB
+ MachineInstr *saveValue;
+ if(mOp.getVRegValue()->getType() == Type::FloatTy)
+ saveValue = BuildMI(machineBB, V9::FMOVS, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
+ else if(mOp.getVRegValue()->getType() == Type::DoubleTy)
+ saveValue = BuildMI(machineBB, V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
+ else
+ saveValue = BuildMI(machineBB, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp);
+
+
+ DEBUG(std::cerr << "Created new machine instr: " << *saveValue << "\n");
+ }
+ }
+
+ //We may also need to update the value that we use if
+ //its from an earlier prologue
+ if(j != 0) {
+ if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isUse()) {
+ if(newValues.count(mOp.getVRegValue())) {
+ if(newValues[mOp.getVRegValue()].count(i-1)) {
+ Value *oldV = mOp.getVRegValue();
+ DEBUG(std::cerr << "Replaced this value: " << mOp.getVRegValue() << " With:" << (newValues[mOp.getVRegValue()][i-1]) << "\n");
+ //Update the operand with the right value
+ mOp.setValueReg(newValues[mOp.getVRegValue()][i-1]);
+
+ //Remove this value since we have consumed it
+ //NOTE: Should this only be done if j != maxStage?
+ consumedValues[oldV][i-1] = (newValues[oldV][i-1]);
+ DEBUG(std::cerr << "Deleted value: " << consumedValues[oldV][i-1] << "\n");
+ newValues[oldV].erase(i-1);
+ }
+ }
+ else
+ if(consumedValues.count(mOp.getVRegValue()))
+ assert(!consumedValues[mOp.getVRegValue()].count(i-1) && "Found a case where we need the value");
+ }
+ }
+ }
+ }
+ }
}
- (((MachineBasicBlock*)MBB)->getParent())->getBasicBlockList().push_back(machineBB);
- current_prologue.push_back(machineBB);
- current_llvm_prologue.push_back(llvmBB);
+ (((MachineBasicBlock*)MBB)->getParent())->getBasicBlockList().push_back(machineBB);
+ current_prologue.push_back(machineBB);
+ current_llvm_prologue.push_back(llvmBB);
}
prologues.push_back(current_prologue);
llvm_prologues.push_back(current_llvm_prologue);
std::map<Value*, int> inEpilogue;
for(MachineBasicBlock::const_iterator MI = MBB->begin(), ME = MBB->end(); ME != MI; ++MI) {
- for(int j=schedule.getMaxStage(); j > i; --j) {
- if(inKernel[j].count(&*MI)) {
- DEBUG(std::cerr << "Cloning instruction " << *MI << "\n");
- MachineInstr *clone = MI->clone();
-
- //Update operands that need to use the result from the phi
- for(unsigned opNum=0; opNum < clone->getNumOperands(); ++opNum) {
- //get machine operand
- const MachineOperand &mOp = clone->getOperand(opNum);
-
- if((mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isUse())) {
-
- DEBUG(std::cerr << "Writing PHI for " << (mOp.getVRegValue()) << "\n");
-
- //If this is the last instructions for the max iterations ago, don't update operands
- if(inEpilogue.count(mOp.getVRegValue()))
- if(inEpilogue[mOp.getVRegValue()] == i)
- continue;
-
- //Quickly write appropriate phis for this operand
- if(newValues.count(mOp.getVRegValue())) {
- if(newValues[mOp.getVRegValue()].count(i)) {
- Instruction *tmp = new TmpInstruction(newValues[mOp.getVRegValue()][i]);
-
- //Get machine code for this instruction
- MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst);
- tempMvec.addTemp((Value*) tmp);
-
- //assert of no kernelPHI for this value
- assert(kernelPHIs[mOp.getVRegValue()][i] !=0 && "Must have final kernel phi to construct epilogue phi");
-
- MachineInstr *saveValue = BuildMI(machineBB, V9::PHI, 3).addReg(newValues[mOp.getVRegValue()][i]).addReg(kernelPHIs[mOp.getVRegValue()][i]).addRegDef(tmp);
- DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n");
- valPHIs[mOp.getVRegValue()] = tmp;
- }
- }
-
- if(valPHIs.count(mOp.getVRegValue())) {
- //Update the operand in the cloned instruction
- clone->getOperand(opNum).setValueReg(valPHIs[mOp.getVRegValue()]);
- }
- }
- else if((mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef())) {
- inEpilogue[mOp.getVRegValue()] = i;
- }
-
- }
- machineBB->push_back(clone);
- //if(MTI->isBranch(clone->getOpcode()))
- //BuildMI(machineBB, V9::NOP, 0);
- }
- }
+ for(int j=schedule.getMaxStage(); j > i; --j) {
+ if(inKernel[j].count(&*MI)) {
+ DEBUG(std::cerr << "Cloning instruction " << *MI << "\n");
+ MachineInstr *clone = MI->clone();
+
+ //Update operands that need to use the result from the phi
+ for(unsigned opNum=0; opNum < clone->getNumOperands(); ++opNum) {
+ //get machine operand
+ const MachineOperand &mOp = clone->getOperand(opNum);
+
+ if((mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isUse())) {
+
+ DEBUG(std::cerr << "Writing PHI for " << (mOp.getVRegValue()) << "\n");
+
+ //If this is the last instructions for the max iterations ago, don't update operands
+ if(inEpilogue.count(mOp.getVRegValue()))
+ if(inEpilogue[mOp.getVRegValue()] == i)
+ continue;
+
+ //Quickly write appropriate phis for this operand
+ if(newValues.count(mOp.getVRegValue())) {
+ if(newValues[mOp.getVRegValue()].count(i)) {
+ Instruction *tmp = new TmpInstruction(newValues[mOp.getVRegValue()][i]);
+
+ //Get machine code for this instruction
+ MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst);
+ tempMvec.addTemp((Value*) tmp);
+
+ //assert of no kernelPHI for this value
+ assert(kernelPHIs[mOp.getVRegValue()][i] !=0 && "Must have final kernel phi to construct epilogue phi");
+
+ MachineInstr *saveValue = BuildMI(machineBB, V9::PHI, 3).addReg(newValues[mOp.getVRegValue()][i]).addReg(kernelPHIs[mOp.getVRegValue()][i]).addRegDef(tmp);
+ DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n");
+ valPHIs[mOp.getVRegValue()] = tmp;
+ }
+ }
+
+ if(valPHIs.count(mOp.getVRegValue())) {
+ //Update the operand in the cloned instruction
+ clone->getOperand(opNum).setValueReg(valPHIs[mOp.getVRegValue()]);
+ }
+ }
+ else if((mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef())) {
+ inEpilogue[mOp.getVRegValue()] = i;
+ }
+
+ }
+ machineBB->push_back(clone);
+ //if(MTI->isBranch(clone->getOpcode()))
+ //BuildMI(machineBB, V9::NOP, 0);
+ }
+ }
}
(((MachineBasicBlock*)MBB)->getParent())->getBasicBlockList().push_back(machineBB);
current_epilogue.push_back(machineBB);
DEBUG(std::cerr << "EPILOGUE #" << i << "\n");
DEBUG(for(std::vector<MachineBasicBlock*>::iterator B = current_epilogue.begin(), BE = current_epilogue.end(); B != BE; ++B) {
- (*B)->print(std::cerr);});
+ (*B)->print(std::cerr);});
epilogues.push_back(current_epilogue);
llvm_epilogues.push_back(current_llvm_epilogue);
if(I->second != 0) {
if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isUse()) {
- //Check to see where this operand is defined if this instruction is from max stage
- if(I->second == schedule.getMaxStage()) {
- DEBUG(std::cerr << "VREG: " << *(mOp.getVRegValue()) << "\n");
- }
-
- //If its in the value saved, we need to create a temp instruction and use that instead
- if(valuesToSave.count(mOp.getVRegValue())) {
-
- //Check if we already have a final PHI value for this
- if(!finalPHIValue.count(mOp.getVRegValue())) {
- //Only create phi if the operand def is from a stage before this one
- if(schedule.defPreviousStage(mOp.getVRegValue(), I->second)) {
- TmpInstruction *tmp = new TmpInstruction(mOp.getVRegValue());
-
- //Get machine code for this instruction
- MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst);
- tempMvec.addTemp((Value*) tmp);
-
- //Update the operand in the cloned instruction
- instClone->getOperand(i).setValueReg(tmp);
-
- //save this as our final phi
- finalPHIValue[mOp.getVRegValue()] = tmp;
- newValLocation[tmp] = machineBB[index];
- }
- }
- else {
- //Use the previous final phi value
- instClone->getOperand(i).setValueReg(finalPHIValue[mOp.getVRegValue()]);
- }
- }
+ //Check to see where this operand is defined if this instruction is from max stage
+ if(I->second == schedule.getMaxStage()) {
+ DEBUG(std::cerr << "VREG: " << *(mOp.getVRegValue()) << "\n");
+ }
+
+ //If its in the value saved, we need to create a temp instruction and use that instead
+ if(valuesToSave.count(mOp.getVRegValue())) {
+
+ //Check if we already have a final PHI value for this
+ if(!finalPHIValue.count(mOp.getVRegValue())) {
+ //Only create phi if the operand def is from a stage before this one
+ if(schedule.defPreviousStage(mOp.getVRegValue(), I->second)) {
+ TmpInstruction *tmp = new TmpInstruction(mOp.getVRegValue());
+
+ //Get machine code for this instruction
+ MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst);
+ tempMvec.addTemp((Value*) tmp);
+
+ //Update the operand in the cloned instruction
+ instClone->getOperand(i).setValueReg(tmp);
+
+ //save this as our final phi
+ finalPHIValue[mOp.getVRegValue()] = tmp;
+ newValLocation[tmp] = machineBB[index];
+ }
+ }
+ else {
+ //Use the previous final phi value
+ instClone->getOperand(i).setValueReg(finalPHIValue[mOp.getVRegValue()]);
+ }
+ }
}
}
if(I->second != schedule.getMaxStage()) {
if(mOp.getType() == MachineOperand::MO_VirtualRegister && mOp.isDef()) {
- if(valuesToSave.count(mOp.getVRegValue())) {
-
- TmpInstruction *tmp = new TmpInstruction(mOp.getVRegValue());
-
- //Get machine code for this instruction
- MachineCodeForInstruction & tempVec = MachineCodeForInstruction::get(defaultInst);
- tempVec.addTemp((Value*) tmp);
-
- //Create new machine instr and put in MBB
- MachineInstr *saveValue;
- if(mOp.getVRegValue()->getType() == Type::FloatTy)
- saveValue = BuildMI(machineBB[index], V9::FMOVS, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
- else if(mOp.getVRegValue()->getType() == Type::DoubleTy)
- saveValue = BuildMI(machineBB[index], V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
- else
- saveValue = BuildMI(machineBB[index], V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp);
-
-
- //Save for future cleanup
- kernelValue[mOp.getVRegValue()] = tmp;
- newValLocation[tmp] = machineBB[index];
- kernelPHIs[mOp.getVRegValue()][schedule.getMaxStage()-1] = tmp;
- }
+ if(valuesToSave.count(mOp.getVRegValue())) {
+
+ TmpInstruction *tmp = new TmpInstruction(mOp.getVRegValue());
+
+ //Get machine code for this instruction
+ MachineCodeForInstruction & tempVec = MachineCodeForInstruction::get(defaultInst);
+ tempVec.addTemp((Value*) tmp);
+
+ //Create new machine instr and put in MBB
+ MachineInstr *saveValue;
+ if(mOp.getVRegValue()->getType() == Type::FloatTy)
+ saveValue = BuildMI(machineBB[index], V9::FMOVS, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
+ else if(mOp.getVRegValue()->getType() == Type::DoubleTy)
+ saveValue = BuildMI(machineBB[index], V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
+ else
+ saveValue = BuildMI(machineBB[index], V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp);
+
+
+ //Save for future cleanup
+ kernelValue[mOp.getVRegValue()] = tmp;
+ newValLocation[tmp] = machineBB[index];
+ kernelPHIs[mOp.getVRegValue()][schedule.getMaxStage()-1] = tmp;
+ }
}
}
}
DEBUG(std::cerr << "Writing phi for" << *(V->first));
DEBUG(std::cerr << "\nMap of Value* for this phi\n");
DEBUG(for(std::map<int, Value*>::iterator I = V->second.begin(),
- IE = V->second.end(); I != IE; ++I) {
+ IE = V->second.end(); I != IE; ++I) {
std::cerr << "Stage: " << I->first;
std::cerr << " Value: " << *(I->second) << "\n";
});
unsigned count = 1;
//Loop over the the map backwards to generate phis
for(std::map<int, Value*>::reverse_iterator I = V->second.rbegin(), IE = V->second.rend();
- I != IE; ++I) {
+ I != IE; ++I) {
if(count < (V->second).size()) {
- if(lastPhi == 0) {
- lastPhi = new TmpInstruction(I->second);
-
- //Get machine code for this instruction
- MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst);
- tempMvec.addTemp((Value*) lastPhi);
-
- MachineInstr *saveValue = BuildMI(*machineBB[0], machineBB[0]->begin(), V9::PHI, 3).addReg(kernelValue[V->first]).addReg(I->second).addRegDef(lastPhi);
- DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n");
- newValLocation[lastPhi] = machineBB[0];
- }
- else {
- Instruction *tmp = new TmpInstruction(I->second);
-
- //Get machine code for this instruction
- MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst);
- tempMvec.addTemp((Value*) tmp);
-
-
- MachineInstr *saveValue = BuildMI(*machineBB[0], machineBB[0]->begin(), V9::PHI, 3).addReg(lastPhi).addReg(I->second).addRegDef(tmp);
- DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n");
- lastPhi = tmp;
- kernelPHIs[V->first][I->first] = lastPhi;
- newValLocation[lastPhi] = machineBB[0];
- }
+ if(lastPhi == 0) {
+ lastPhi = new TmpInstruction(I->second);
+
+ //Get machine code for this instruction
+ MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst);
+ tempMvec.addTemp((Value*) lastPhi);
+
+ MachineInstr *saveValue = BuildMI(*machineBB[0], machineBB[0]->begin(), V9::PHI, 3).addReg(kernelValue[V->first]).addReg(I->second).addRegDef(lastPhi);
+ DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n");
+ newValLocation[lastPhi] = machineBB[0];
+ }
+ else {
+ Instruction *tmp = new TmpInstruction(I->second);
+
+ //Get machine code for this instruction
+ MachineCodeForInstruction & tempMvec = MachineCodeForInstruction::get(defaultInst);
+ tempMvec.addTemp((Value*) tmp);
+
+
+ MachineInstr *saveValue = BuildMI(*machineBB[0], machineBB[0]->begin(), V9::PHI, 3).addReg(lastPhi).addReg(I->second).addRegDef(tmp);
+ DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n");
+ lastPhi = tmp;
+ kernelPHIs[V->first][I->first] = lastPhi;
+ newValLocation[lastPhi] = machineBB[0];
+ }
}
//Final phi value
else {
- //The resulting value must be the Value* we created earlier
- assert(lastPhi != 0 && "Last phi is NULL!\n");
- MachineInstr *saveValue = BuildMI(*machineBB[0], machineBB[0]->begin(), V9::PHI, 3).addReg(lastPhi).addReg(I->second).addRegDef(finalPHIValue[V->first]);
- DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n");
- kernelPHIs[V->first][I->first] = finalPHIValue[V->first];
+ //The resulting value must be the Value* we created earlier
+ assert(lastPhi != 0 && "Last phi is NULL!\n");
+ MachineInstr *saveValue = BuildMI(*machineBB[0], machineBB[0]->begin(), V9::PHI, 3).addReg(lastPhi).addReg(I->second).addRegDef(finalPHIValue[V->first]);
+ DEBUG(std::cerr << "Resulting PHI: " << *saveValue << "\n");
+ kernelPHIs[V->first][I->first] = finalPHIValue[V->first];
}
++count;
Instruction *tmp = 0;
for(unsigned i = 0; i < I->getNumOperands(); ++i) {
-
- //Get Operand
- const MachineOperand &mOp = I->getOperand(i);
- assert(mOp.getType() == MachineOperand::MO_VirtualRegister
- && "Should be a Value*\n");
-
- if(!tmp) {
- tmp = new TmpInstruction(mOp.getVRegValue());
- addToMCFI.push_back(tmp);
- }
-
- //Now for all our arguments we read, OR to the new
- //TmpInstruction that we created
- if(mOp.isUse()) {
- DEBUG(std::cerr << "Use: " << mOp << "\n");
- //Place a copy at the end of its BB but before the branches
- assert(newValLocation.count(mOp.getVRegValue()) && "We must know where this value is located\n");
- //Reverse iterate to find the branches, we can safely assume no instructions have been
- //put in the nop positions
- for(MachineBasicBlock::iterator inst = --(newValLocation[mOp.getVRegValue()])->end(), endBB = (newValLocation[mOp.getVRegValue()])->begin(); inst != endBB; --inst) {
- MachineOpCode opc = inst->getOpcode();
- if(TMI->isBranch(opc) || TMI->isNop(opc))
- continue;
- else {
- if(mOp.getVRegValue()->getType() == Type::FloatTy)
- BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVS, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
- else if(mOp.getVRegValue()->getType() == Type::DoubleTy)
- BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
- else
- BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp);
-
- break;
- }
-
- }
-
- }
- else {
- //Remove the phi and replace it with an OR
- DEBUG(std::cerr << "Def: " << mOp << "\n");
- //newORs.push_back(std::make_pair(tmp, mOp.getVRegValue()));
- if(tmp->getType() == Type::FloatTy)
- BuildMI(*kernelBB[0], I, V9::FMOVS, 3).addReg(tmp).addRegDef(mOp.getVRegValue());
- else if(tmp->getType() == Type::DoubleTy)
- BuildMI(*kernelBB[0], I, V9::FMOVD, 3).addReg(tmp).addRegDef(mOp.getVRegValue());
- else
- BuildMI(*kernelBB[0], I, V9::ORr, 3).addReg(tmp).addImm(0).addRegDef(mOp.getVRegValue());
-
-
- worklist.push_back(std::make_pair(kernelBB[0], I));
- }
-
+
+ //Get Operand
+ const MachineOperand &mOp = I->getOperand(i);
+ assert(mOp.getType() == MachineOperand::MO_VirtualRegister
+ && "Should be a Value*\n");
+
+ if(!tmp) {
+ tmp = new TmpInstruction(mOp.getVRegValue());
+ addToMCFI.push_back(tmp);
+ }
+
+ //Now for all our arguments we read, OR to the new
+ //TmpInstruction that we created
+ if(mOp.isUse()) {
+ DEBUG(std::cerr << "Use: " << mOp << "\n");
+ //Place a copy at the end of its BB but before the branches
+ assert(newValLocation.count(mOp.getVRegValue()) && "We must know where this value is located\n");
+ //Reverse iterate to find the branches, we can safely assume no instructions have been
+ //put in the nop positions
+ for(MachineBasicBlock::iterator inst = --(newValLocation[mOp.getVRegValue()])->end(), endBB = (newValLocation[mOp.getVRegValue()])->begin(); inst != endBB; --inst) {
+ MachineOpCode opc = inst->getOpcode();
+ if(TMI->isBranch(opc) || TMI->isNop(opc))
+ continue;
+ else {
+ if(mOp.getVRegValue()->getType() == Type::FloatTy)
+ BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVS, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
+ else if(mOp.getVRegValue()->getType() == Type::DoubleTy)
+ BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
+ else
+ BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp);
+
+ break;
+ }
+
+ }
+
+ }
+ else {
+ //Remove the phi and replace it with an OR
+ DEBUG(std::cerr << "Def: " << mOp << "\n");
+ //newORs.push_back(std::make_pair(tmp, mOp.getVRegValue()));
+ if(tmp->getType() == Type::FloatTy)
+ BuildMI(*kernelBB[0], I, V9::FMOVS, 3).addReg(tmp).addRegDef(mOp.getVRegValue());
+ else if(tmp->getType() == Type::DoubleTy)
+ BuildMI(*kernelBB[0], I, V9::FMOVD, 3).addReg(tmp).addRegDef(mOp.getVRegValue());
+ else
+ BuildMI(*kernelBB[0], I, V9::ORr, 3).addReg(tmp).addImm(0).addRegDef(mOp.getVRegValue());
+
+
+ worklist.push_back(std::make_pair(kernelBB[0], I));
+ }
+
}
}
//Remove phis from epilogue
for(std::vector<std::vector<MachineBasicBlock*> >::iterator MB = epilogues.begin(),
- ME = epilogues.end(); MB != ME; ++MB) {
+ ME = epilogues.end(); MB != ME; ++MB) {
for(std::vector<MachineBasicBlock*>::iterator currentMBB = MB->begin(), currentME = MB->end(); currentMBB != currentME; ++currentMBB) {
for(MachineBasicBlock::iterator I = (*currentMBB)->begin(),
- E = (*currentMBB)->end(); I != E; ++I) {
-
- DEBUG(std::cerr << "Looking at Instr: " << *I << "\n");
- //Get op code and check if its a phi
- if(I->getOpcode() == V9::PHI) {
- Instruction *tmp = 0;
-
- for(unsigned i = 0; i < I->getNumOperands(); ++i) {
- //Get Operand
- const MachineOperand &mOp = I->getOperand(i);
- assert(mOp.getType() == MachineOperand::MO_VirtualRegister && "Should be a Value*\n");
-
- if(!tmp) {
- tmp = new TmpInstruction(mOp.getVRegValue());
- addToMCFI.push_back(tmp);
- }
-
- //Now for all our arguments we read, OR to the new TmpInstruction that we created
- if(mOp.isUse()) {
- DEBUG(std::cerr << "Use: " << mOp << "\n");
- //Place a copy at the end of its BB but before the branches
- assert(newValLocation.count(mOp.getVRegValue()) && "We must know where this value is located\n");
- //Reverse iterate to find the branches, we can safely assume no instructions have been
- //put in the nop positions
- for(MachineBasicBlock::iterator inst = --(newValLocation[mOp.getVRegValue()])->end(), endBB = (newValLocation[mOp.getVRegValue()])->begin(); inst != endBB; --inst) {
- MachineOpCode opc = inst->getOpcode();
- if(TMI->isBranch(opc) || TMI->isNop(opc))
- continue;
- else {
- if(mOp.getVRegValue()->getType() == Type::FloatTy)
- BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVS, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
- else if(mOp.getVRegValue()->getType() == Type::DoubleTy)
- BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
- else
- BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp);
-
-
- break;
- }
-
- }
-
- }
- else {
- //Remove the phi and replace it with an OR
- DEBUG(std::cerr << "Def: " << mOp << "\n");
- if(tmp->getType() == Type::FloatTy)
- BuildMI(**currentMBB, I, V9::FMOVS, 3).addReg(tmp).addRegDef(mOp.getVRegValue());
- else if(tmp->getType() == Type::DoubleTy)
- BuildMI(**currentMBB, I, V9::FMOVD, 3).addReg(tmp).addRegDef(mOp.getVRegValue());
- else
- BuildMI(**currentMBB, I, V9::ORr, 3).addReg(tmp).addImm(0).addRegDef(mOp.getVRegValue());
-
- worklist.push_back(std::make_pair(*currentMBB,I));
- }
- }
- }
+ E = (*currentMBB)->end(); I != E; ++I) {
+
+ DEBUG(std::cerr << "Looking at Instr: " << *I << "\n");
+ //Get op code and check if its a phi
+ if(I->getOpcode() == V9::PHI) {
+ Instruction *tmp = 0;
+
+ for(unsigned i = 0; i < I->getNumOperands(); ++i) {
+ //Get Operand
+ const MachineOperand &mOp = I->getOperand(i);
+ assert(mOp.getType() == MachineOperand::MO_VirtualRegister && "Should be a Value*\n");
+
+ if(!tmp) {
+ tmp = new TmpInstruction(mOp.getVRegValue());
+ addToMCFI.push_back(tmp);
+ }
+
+ //Now for all our arguments we read, OR to the new TmpInstruction that we created
+ if(mOp.isUse()) {
+ DEBUG(std::cerr << "Use: " << mOp << "\n");
+ //Place a copy at the end of its BB but before the branches
+ assert(newValLocation.count(mOp.getVRegValue()) && "We must know where this value is located\n");
+ //Reverse iterate to find the branches, we can safely assume no instructions have been
+ //put in the nop positions
+ for(MachineBasicBlock::iterator inst = --(newValLocation[mOp.getVRegValue()])->end(), endBB = (newValLocation[mOp.getVRegValue()])->begin(); inst != endBB; --inst) {
+ MachineOpCode opc = inst->getOpcode();
+ if(TMI->isBranch(opc) || TMI->isNop(opc))
+ continue;
+ else {
+ if(mOp.getVRegValue()->getType() == Type::FloatTy)
+ BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVS, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
+ else if(mOp.getVRegValue()->getType() == Type::DoubleTy)
+ BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::FMOVD, 3).addReg(mOp.getVRegValue()).addRegDef(tmp);
+ else
+ BuildMI(*(newValLocation[mOp.getVRegValue()]), ++inst, V9::ORr, 3).addReg(mOp.getVRegValue()).addImm(0).addRegDef(tmp);
+
+
+ break;
+ }
+
+ }
+
+ }
+ else {
+ //Remove the phi and replace it with an OR
+ DEBUG(std::cerr << "Def: " << mOp << "\n");
+ if(tmp->getType() == Type::FloatTy)
+ BuildMI(**currentMBB, I, V9::FMOVS, 3).addReg(tmp).addRegDef(mOp.getVRegValue());
+ else if(tmp->getType() == Type::DoubleTy)
+ BuildMI(**currentMBB, I, V9::FMOVD, 3).addReg(tmp).addRegDef(mOp.getVRegValue());
+ else
+ BuildMI(**currentMBB, I, V9::ORr, 3).addReg(tmp).addImm(0).addRegDef(mOp.getVRegValue());
+
+ worklist.push_back(std::make_pair(*currentMBB,I));
+ }
+ }
+ }
}
}
}
for(std::vector<std::pair<MachineBasicBlock*, MachineBasicBlock::iterator> >::iterator I = worklist.begin(), E = worklist.end(); I != E; ++I) {
DEBUG(std::cerr << "Deleting PHI " << *I->second << "\n");
I->first->erase(I->second);
-
+
}
if(instrsMovedDown.count(mbb)) {
for(std::vector<std::pair<MachineInstr*, int> >::iterator I = instrsMovedDown[mbb].begin(), E = instrsMovedDown[mbb].end(); I != E; ++I) {
- if(branchStage[mbb] == I->second)
- sideMBB->push_back((I->first)->clone());
+ if(branchStage[mbb] == I->second)
+ sideMBB->push_back((I->first)->clone());
}
//Add unconditional branches to original exits
std::vector<BasicBlock*> newLLVMEp;
for(std::vector<MachineBasicBlock*>::iterator currentMBB = MB.begin(),
- lastMBB = MB.end(); currentMBB != lastMBB; ++currentMBB) {
- BasicBlock *tmpBB = new BasicBlock("SideEpilogue", (Function*) (*currentMBB)->getBasicBlock()->getParent());
- MachineBasicBlock *tmp = new MachineBasicBlock(tmpBB);
+ lastMBB = MB.end(); currentMBB != lastMBB; ++currentMBB) {
+ BasicBlock *tmpBB = new BasicBlock("SideEpilogue", (Function*) (*currentMBB)->getBasicBlock()->getParent());
+ MachineBasicBlock *tmp = new MachineBasicBlock(tmpBB);
- //Clone instructions and insert into new MBB
- for(MachineBasicBlock::iterator I = (*currentMBB)->begin(),
- E = (*currentMBB)->end(); I != E; ++I) {
-
- MachineInstr *clone = I->clone();
- if(clone->getOpcode() == V9::BA && (currentMBB+1 == lastMBB)) {
- //update branch to side exit
- for(unsigned i = 0; i < clone->getNumOperands(); ++i) {
- MachineOperand &mOp = clone->getOperand(i);
- if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
- mOp.setValueReg(sideBB);
- }
- }
- }
-
- tmp->push_back(clone);
-
- }
+ //Clone instructions and insert into new MBB
+ for(MachineBasicBlock::iterator I = (*currentMBB)->begin(),
+ E = (*currentMBB)->end(); I != E; ++I) {
+
+ MachineInstr *clone = I->clone();
+ if(clone->getOpcode() == V9::BA && (currentMBB+1 == lastMBB)) {
+ //update branch to side exit
+ for(unsigned i = 0; i < clone->getNumOperands(); ++i) {
+ MachineOperand &mOp = clone->getOperand(i);
+ if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
+ mOp.setValueReg(sideBB);
+ }
+ }
+ }
+
+ tmp->push_back(clone);
+
+ }
- //Add llvm branch
- TerminatorInst *newBranch = new BranchInst(sideBB, tmpBB);
+ //Add llvm branch
+ TerminatorInst *newBranch = new BranchInst(sideBB, tmpBB);
- newEp.push_back(tmp);
- (((MachineBasicBlock*)SB[0])->getParent())->getBasicBlockList().push_back(tmp);
+ newEp.push_back(tmp);
+ (((MachineBasicBlock*)SB[0])->getParent())->getBasicBlockList().push_back(tmp);
- newLLVMEp.push_back(tmpBB);
+ newLLVMEp.push_back(tmpBB);
}
side_llvm_epilogues.push_back(newLLVMEp);
//Get BB side exit we are dealing with
MachineBasicBlock *currentMBB = prologues[P][sideExitNum];
if(P >= (unsigned) stage) {
- //Iterate backwards of machine instructions to find the branch we need to update
- for(MachineBasicBlock::reverse_iterator mInst = currentMBB->rbegin(), mInstEnd = currentMBB->rend(); mInst != mInstEnd; ++mInst) {
- MachineOpCode OC = mInst->getOpcode();
-
- //If its a branch update its branchto
- if(TMI->isBranch(OC)) {
- for(unsigned opNum = 0; opNum < mInst->getNumOperands(); ++opNum) {
- MachineOperand &mOp = mInst->getOperand(opNum);
- if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
- //Check if we branch to side exit
- if(mOp.getVRegValue() == sideExits[mbb]) {
- mOp.setValueReg(side_llvm_epilogues[P][0]);
- }
- }
- }
- DEBUG(std::cerr << "New Prologue Branch: " << *mInst << "\n");
- }
- }
-
- //Update llvm branch
- TerminatorInst *branchVal = ((BasicBlock*) currentMBB->getBasicBlock())->getTerminator();
- DEBUG(std::cerr << *branchVal << "\n");
-
- for(unsigned i=0; i < branchVal->getNumSuccessors(); ++i) {
- if(branchVal->getSuccessor(i) == sideExits[mbb]) {
- DEBUG(std::cerr << "Replacing successor bb\n");
- branchVal->setSuccessor(i, side_llvm_epilogues[P][0]);
- }
- }
+ //Iterate backwards of machine instructions to find the branch we need to update
+ for(MachineBasicBlock::reverse_iterator mInst = currentMBB->rbegin(), mInstEnd = currentMBB->rend(); mInst != mInstEnd; ++mInst) {
+ MachineOpCode OC = mInst->getOpcode();
+
+ //If its a branch update its branchto
+ if(TMI->isBranch(OC)) {
+ for(unsigned opNum = 0; opNum < mInst->getNumOperands(); ++opNum) {
+ MachineOperand &mOp = mInst->getOperand(opNum);
+ if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
+ //Check if we branch to side exit
+ if(mOp.getVRegValue() == sideExits[mbb]) {
+ mOp.setValueReg(side_llvm_epilogues[P][0]);
+ }
+ }
+ }
+ DEBUG(std::cerr << "New Prologue Branch: " << *mInst << "\n");
+ }
+ }
+
+ //Update llvm branch
+ TerminatorInst *branchVal = ((BasicBlock*) currentMBB->getBasicBlock())->getTerminator();
+ DEBUG(std::cerr << *branchVal << "\n");
+
+ for(unsigned i=0; i < branchVal->getNumSuccessors(); ++i) {
+ if(branchVal->getSuccessor(i) == sideExits[mbb]) {
+ DEBUG(std::cerr << "Replacing successor bb\n");
+ branchVal->setSuccessor(i, side_llvm_epilogues[P][0]);
+ }
+ }
}
else {
- //must add BA branch because another prologue or kernel has the actual side exit branch
- //Add unconditional branches to original exits
- assert( (sideExitNum+1) < prologues[P].size() && "must have valid prologue to branch to");
- BuildMI(prologues[P][sideExitNum], V9::BA, 1).addPCDisp((BasicBlock*)(prologues[P][sideExitNum+1])->getBasicBlock());
- BuildMI(prologues[P][sideExitNum], V9::NOP, 0);
+ //must add BA branch because another prologue or kernel has the actual side exit branch
+ //Add unconditional branches to original exits
+ assert( (sideExitNum+1) < prologues[P].size() && "must have valid prologue to branch to");
+ BuildMI(prologues[P][sideExitNum], V9::BA, 1).addPCDisp((BasicBlock*)(prologues[P][sideExitNum+1])->getBasicBlock());
+ BuildMI(prologues[P][sideExitNum], V9::NOP, 0);
- TerminatorInst *newBranch = new BranchInst((BasicBlock*) (prologues[P][sideExitNum+1])->getBasicBlock(), (BasicBlock*) (prologues[P][sideExitNum])->getBasicBlock());
+ TerminatorInst *newBranch = new BranchInst((BasicBlock*) (prologues[P][sideExitNum+1])->getBasicBlock(), (BasicBlock*) (prologues[P][sideExitNum])->getBasicBlock());
}
}
//If its a branch update its branchto
if(TMI->isBranch(OC)) {
- for(unsigned opNum = 0; opNum < mInst->getNumOperands(); ++opNum) {
- MachineOperand &mOp = mInst->getOperand(opNum);
- if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
- //Check if we branch to side exit
- if(mOp.getVRegValue() == sideExits[mbb]) {
- if(side_llvm_epilogues.size() > 0)
- mOp.setValueReg(side_llvm_epilogues[0][0]);
- else
- mOp.setValueReg(sideBB);
- }
- }
- }
- DEBUG(std::cerr << "New Prologue Branch: " << *mInst << "\n");
+ for(unsigned opNum = 0; opNum < mInst->getNumOperands(); ++opNum) {
+ MachineOperand &mOp = mInst->getOperand(opNum);
+ if (mOp.getType() == MachineOperand::MO_PCRelativeDisp) {
+ //Check if we branch to side exit
+ if(mOp.getVRegValue() == sideExits[mbb]) {
+ if(side_llvm_epilogues.size() > 0)
+ mOp.setValueReg(side_llvm_epilogues[0][0]);
+ else
+ mOp.setValueReg(sideBB);
+ }
+ }
+ }
+ DEBUG(std::cerr << "New Prologue Branch: " << *mInst << "\n");
}
}
for(unsigned i=0; i < branchVal->getNumSuccessors(); ++i) {
if(branchVal->getSuccessor(i) == sideExits[mbb]) {
- DEBUG(std::cerr << "Replacing successor bb\n");
- if(side_llvm_epilogues.size() > 0)
- branchVal->setSuccessor(i, side_llvm_epilogues[0][0]);
- else
- branchVal->setSuccessor(i, sideBB);
+ DEBUG(std::cerr << "Replacing successor bb\n");
+ if(side_llvm_epilogues.size() > 0)
+ branchVal->setSuccessor(i, side_llvm_epilogues[0][0]);
+ else
+ branchVal->setSuccessor(i, sideBB);
}
}
}
int depth;
int height;
MSNodeSBAttributes(int asap=-1, int alap=-1, int mob=-1,
- int d=-1, int h=-1) : ASAP(asap), ALAP(alap),
- MOB(mob), depth(d),
- height(h) {}
+ int d=-1, int h=-1) : ASAP(asap), ALAP(alap),
+ MOB(mob), depth(d),
+ height(h) {}
};
class ModuloSchedulingSBPass : public FunctionPass {
const TargetMachine ⌖
-
+
//Map to hold Value* defs
std::map<const Value*, MachineInstr*> defMap;
//Map to hold machine to llvm instrs for each valid BB
std::map<SuperBlock, std::map<MachineInstr*, Instruction*> > machineTollvm;
-
+
//LLVM Instruction we know we can add TmpInstructions to its MCFI
Instruction *defaultInst;
//Current initiation interval
int II;
-
+
//Internal Functions
- void FindSuperBlocks(Function &F, LoopInfo &LI,
- std::vector<std::vector<const MachineBasicBlock*> > &Worklist);
+ void FindSuperBlocks(Function &F, LoopInfo &LI,
+ std::vector<std::vector<const MachineBasicBlock*> > &Worklist);
bool MachineBBisValid(const MachineBasicBlock *B,
- std::map<const MachineInstr*, unsigned> &indexMap,
- unsigned &offset);
+ std::map<const MachineInstr*, unsigned> &indexMap,
+ unsigned &offset);
bool CreateDefMap(std::vector<const MachineBasicBlock*> &SB);
- bool getIndVar(std::vector<const MachineBasicBlock*> &superBlock,
- std::map<BasicBlock*, MachineBasicBlock*> &bbMap,
- std::map<const MachineInstr*, unsigned> &indexMap);
+ bool getIndVar(std::vector<const MachineBasicBlock*> &superBlock,
+ std::map<BasicBlock*, MachineBasicBlock*> &bbMap,
+ std::map<const MachineInstr*, unsigned> &indexMap);
bool assocIndVar(Instruction *I, std::set<Instruction*> &indVar,
- std::vector<Instruction*> &stack,
- std::map<BasicBlock*, MachineBasicBlock*> &bbMap,
- const BasicBlock *first,
- std::set<const BasicBlock*> &llvmSuperBlock);
+ std::vector<Instruction*> &stack,
+ std::map<BasicBlock*, MachineBasicBlock*> &bbMap,
+ const BasicBlock *first,
+ std::set<const BasicBlock*> &llvmSuperBlock);
int calculateResMII(std::vector<const MachineBasicBlock*> &superBlock);
int calculateRecMII(MSchedGraphSB *graph, int MII);
void findAllCircuits(MSchedGraphSB *g, int II);
- void addRecc(std::vector<MSchedGraphSBNode*> &stack,
- std::map<MSchedGraphSBNode*, MSchedGraphSBNode*> &newNodes);
+ void addRecc(std::vector<MSchedGraphSBNode*> &stack,
+ std::map<MSchedGraphSBNode*, MSchedGraphSBNode*> &newNodes);
bool circuit(MSchedGraphSBNode *v, std::vector<MSchedGraphSBNode*> &stack,
- std::set<MSchedGraphSBNode*> &blocked, std::vector<MSchedGraphSBNode*> &SCC,
- MSchedGraphSBNode *s, std::map<MSchedGraphSBNode*,
- std::set<MSchedGraphSBNode*> > &B,
- int II, std::map<MSchedGraphSBNode*, MSchedGraphSBNode*> &newNodes);
+ std::set<MSchedGraphSBNode*> &blocked, std::vector<MSchedGraphSBNode*> &SCC,
+ MSchedGraphSBNode *s, std::map<MSchedGraphSBNode*,
+ std::set<MSchedGraphSBNode*> > &B,
+ int II, std::map<MSchedGraphSBNode*, MSchedGraphSBNode*> &newNodes);
void unblock(MSchedGraphSBNode *u, std::set<MSchedGraphSBNode*> &blocked,
- std::map<MSchedGraphSBNode*, std::set<MSchedGraphSBNode*> > &B);
+ std::map<MSchedGraphSBNode*, std::set<MSchedGraphSBNode*> > &B);
void addSCC(std::vector<MSchedGraphSBNode*> &SCC, std::map<MSchedGraphSBNode*, MSchedGraphSBNode*> &newNodes);
void calculateNodeAttributes(MSchedGraphSB *graph, int MII);
bool ignoreEdge(MSchedGraphSBNode *srcNode, MSchedGraphSBNode *destNode);
int calculateASAP(MSchedGraphSBNode *node, int MII, MSchedGraphSBNode *destNode);
int calculateALAP(MSchedGraphSBNode *node, int MII,
- int maxASAP, MSchedGraphSBNode *srcNode);
+ int maxASAP, MSchedGraphSBNode *srcNode);
int findMaxASAP();
int calculateHeight(MSchedGraphSBNode *node,MSchedGraphSBNode *srcNode);
int calculateDepth(MSchedGraphSBNode *node, MSchedGraphSBNode *destNode);
void computePartialOrder();
- void connectedComponentSet(MSchedGraphSBNode *node, std::set<MSchedGraphSBNode*> &ccSet,
- std::set<MSchedGraphSBNode*> &lastNodes);
+ void connectedComponentSet(MSchedGraphSBNode *node, std::set<MSchedGraphSBNode*> &ccSet,
+ std::set<MSchedGraphSBNode*> &lastNodes);
void searchPath(MSchedGraphSBNode *node,
- std::vector<MSchedGraphSBNode*> &path,
- std::set<MSchedGraphSBNode*> &nodesToAdd,
- std::set<MSchedGraphSBNode*> &new_reccurrence);
+ std::vector<MSchedGraphSBNode*> &path,
+ std::set<MSchedGraphSBNode*> &nodesToAdd,
+ std::set<MSchedGraphSBNode*> &new_reccurrence);
void orderNodes();
bool computeSchedule(std::vector<const MachineBasicBlock*> &BB, MSchedGraphSB *MSG);
bool scheduleNode(MSchedGraphSBNode *node, int start, int end);
void predIntersect(std::set<MSchedGraphSBNode*> &CurrentSet, std::set<MSchedGraphSBNode*> &IntersectResult);
void succIntersect(std::set<MSchedGraphSBNode*> &CurrentSet, std::set<MSchedGraphSBNode*> &IntersectResult);
void reconstructLoop(std::vector<const MachineBasicBlock*> &SB);
- void fixBranches(std::vector<std::vector<MachineBasicBlock*> > &prologues,
- std::vector<std::vector<BasicBlock*> > &llvm_prologues,
- std::vector<MachineBasicBlock*> &machineKernelBB,
- std::vector<BasicBlock*> &llvmKernelBB,
- std::vector<std::vector<MachineBasicBlock*> > &epilogues,
- std::vector<std::vector<BasicBlock*> > &llvm_epilogues,
- std::vector<const MachineBasicBlock*> &SB,
- std::map<const MachineBasicBlock*, Value*> &sideExits);
-
- void writePrologues(std::vector<std::vector<MachineBasicBlock *> > &prologues,
- std::vector<const MachineBasicBlock*> &origBB,
- std::vector<std::vector<BasicBlock*> > &llvm_prologues,
- std::map<const Value*, std::pair<const MachineInstr*, int> > &valuesToSave,
- std::map<Value*, std::map<int, Value*> > &newValues,
- std::map<Value*, MachineBasicBlock*> &newValLocation);
-
- void writeKernel(std::vector<BasicBlock*> &llvmBB, std::vector<MachineBasicBlock*> &machineBB,
- std::map<const Value*, std::pair<const MachineInstr*, int> > &valuesToSave,
- std::map<Value*, std::map<int, Value*> > &newValues,
- std::map<Value*, MachineBasicBlock*> &newValLocation,
- std::map<Value*, std::map<int, Value*> > &kernelPHIs);
-
- void removePHIs(std::vector<const MachineBasicBlock*> &SB,
- std::vector<std::vector<MachineBasicBlock*> > &prologues,
- std::vector<std::vector<MachineBasicBlock*> > &epilogues,
- std::vector<MachineBasicBlock*> &kernelBB,
- std::map<Value*, MachineBasicBlock*> &newValLocation);
-
- void writeEpilogues(std::vector<std::vector<MachineBasicBlock*> > &epilogues,
- std::vector<const MachineBasicBlock*> &origSB,
- std::vector<std::vector<BasicBlock*> > &llvm_epilogues,
- std::map<const Value*, std::pair<const MachineInstr*, int> > &valuesToSave,
- std::map<Value*, std::map<int, Value*> > &newValues,
- std::map<Value*, MachineBasicBlock*> &newValLocation,
- std::map<Value*, std::map<int, Value*> > &kernelPHIs);
-
- void writeSideExits(std::vector<std::vector<MachineBasicBlock *> > &prologues,
- std::vector<std::vector<BasicBlock*> > &llvm_prologues,
- std::vector<std::vector<MachineBasicBlock *> > &epilogues,
- std::vector<std::vector<BasicBlock*> > &llvm_epilogues,
- std::map<const MachineBasicBlock*, Value*> &sideExits,
- std::map<MachineBasicBlock*, std::vector<std::pair<MachineInstr*, int> > > &instrsMovedDown,
- std::vector<const MachineBasicBlock*> &SB,
- std::vector<MachineBasicBlock*> &kernelMBBs,
- std::map<MachineBasicBlock*, int> branchStage);
+ void fixBranches(std::vector<std::vector<MachineBasicBlock*> > &prologues,
+ std::vector<std::vector<BasicBlock*> > &llvm_prologues,
+ std::vector<MachineBasicBlock*> &machineKernelBB,
+ std::vector<BasicBlock*> &llvmKernelBB,
+ std::vector<std::vector<MachineBasicBlock*> > &epilogues,
+ std::vector<std::vector<BasicBlock*> > &llvm_epilogues,
+ std::vector<const MachineBasicBlock*> &SB,
+ std::map<const MachineBasicBlock*, Value*> &sideExits);
+
+ void writePrologues(std::vector<std::vector<MachineBasicBlock *> > &prologues,
+ std::vector<const MachineBasicBlock*> &origBB,
+ std::vector<std::vector<BasicBlock*> > &llvm_prologues,
+ std::map<const Value*, std::pair<const MachineInstr*, int> > &valuesToSave,
+ std::map<Value*, std::map<int, Value*> > &newValues,
+ std::map<Value*, MachineBasicBlock*> &newValLocation);
+
+ void writeKernel(std::vector<BasicBlock*> &llvmBB, std::vector<MachineBasicBlock*> &machineBB,
+ std::map<const Value*, std::pair<const MachineInstr*, int> > &valuesToSave,
+ std::map<Value*, std::map<int, Value*> > &newValues,
+ std::map<Value*, MachineBasicBlock*> &newValLocation,
+ std::map<Value*, std::map<int, Value*> > &kernelPHIs);
+
+ void removePHIs(std::vector<const MachineBasicBlock*> &SB,
+ std::vector<std::vector<MachineBasicBlock*> > &prologues,
+ std::vector<std::vector<MachineBasicBlock*> > &epilogues,
+ std::vector<MachineBasicBlock*> &kernelBB,
+ std::map<Value*, MachineBasicBlock*> &newValLocation);
+
+ void writeEpilogues(std::vector<std::vector<MachineBasicBlock*> > &epilogues,
+ std::vector<const MachineBasicBlock*> &origSB,
+ std::vector<std::vector<BasicBlock*> > &llvm_epilogues,
+ std::map<const Value*, std::pair<const MachineInstr*, int> > &valuesToSave,
+ std::map<Value*, std::map<int, Value*> > &newValues,
+ std::map<Value*, MachineBasicBlock*> &newValLocation,
+ std::map<Value*, std::map<int, Value*> > &kernelPHIs);
+
+ void writeSideExits(std::vector<std::vector<MachineBasicBlock *> > &prologues,
+ std::vector<std::vector<BasicBlock*> > &llvm_prologues,
+ std::vector<std::vector<MachineBasicBlock *> > &epilogues,
+ std::vector<std::vector<BasicBlock*> > &llvm_epilogues,
+ std::map<const MachineBasicBlock*, Value*> &sideExits,
+ std::map<MachineBasicBlock*, std::vector<std::pair<MachineInstr*, int> > > &instrsMovedDown,
+ std::vector<const MachineBasicBlock*> &SB,
+ std::vector<MachineBasicBlock*> &kernelMBBs,
+ std::map<MachineBasicBlock*, int> branchStage);
public:
ModuloSchedulingSBPass(TargetMachine &targ) : target(targ) {}
virtual bool runOnFunction(Function &F);
virtual const char* getPassName() const { return "ModuloScheduling-SuperBlock"; }
-
-
+
+
// getAnalysisUsage
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
- /// HACK: We don't actually need scev, but we have
- /// to say we do so that the pass manager does not delete it
- /// before we run.
- AU.addRequired<LoopInfo>();
- AU.addRequired<ScalarEvolution>();
- AU.addRequired<DependenceAnalyzer>();
+ /// HACK: We don't actually need scev, but we have
+ /// to say we do so that the pass manager does not delete it
+ /// before we run.
+ AU.addRequired<LoopInfo>();
+ AU.addRequired<ScalarEvolution>();
+ AU.addRequired<DependenceAnalyzer>();
}
};
}
// init IG matrix
for(unsigned int i=0; i < Size; i++)
for(unsigned int j=0; j < Size; j++)
- IG[i][j] = 0;
+ IG[i][j] = 0;
}
//-----------------------------------------------------------------------------
// that there is some wrong logic in some other method.
//-----------------------------------------------------------------------------
void InterferenceGraph::setInterference(const V9LiveRange *const LR1,
- const V9LiveRange *const LR2 ) {
+ const V9LiveRange *const LR2 ) {
assert(LR1 != LR2);
IGNode *IGNode1 = LR1->getUserIGNode();
//----------------------------------------------------------------------------
void InterferenceGraph::mergeIGNodesOfLRs(const V9LiveRange *LR1,
- V9LiveRange *LR2) {
+ V9LiveRange *LR2) {
assert( LR1 != LR2); // cannot merge the same live range
std::cerr << " [" << i << "] ";
for( unsigned int j=0; j < Size; j++)
- if(IG[i][j])
+ if(IG[i][j])
std::cerr << "(" << i << "," << j << ") ";
std::cerr << "\n";
}
}
};
-static inline std::ostream &operator << (std::ostream &os,
+static inline std::ostream &operator << (std::ostream &os,
const V9LiveRange &lr) {
os << "LiveRange@" << (void *)(&lr);
return os;
unsigned V9LiveRange::getRegClassID() const { return getRegClass()->getID(); }
LiveRangeInfo::LiveRangeInfo(const Function *F, const TargetMachine &tm,
- std::vector<RegClass *> &RCL)
+ std::vector<RegClass *> &RCL)
: Meth(F), TM(tm), RegClassList(RCL), MRI(*tm.getRegInfo()) { }
// CallRetInstrList for processing its args, ret value, and ret addr.
//
if(TM.getInstrInfo()->isReturn(MInst->getOpcode()) ||
- TM.getInstrInfo()->isCall(MInst->getOpcode()))
- CallRetInstrList.push_back(MInst);
+ TM.getInstrInfo()->isCall(MInst->getOpcode()))
+ CallRetInstrList.push_back(MInst);
// iterate over explicit MI operands and create a new LR
// for each operand that is defined by the instruction
for (MachineInstr::val_op_iterator OpI = MInst->begin(),
OpE = MInst->end(); OpI != OpE; ++OpI)
- if (OpI.isDef()) {
- const Value *Def = *OpI;
+ if (OpI.isDef()) {
+ const Value *Def = *OpI;
bool isCC = (OpI.getMachineOperand().getType()
== MachineOperand::MO_CCRegister);
V9LiveRange* LR = createOrAddToLiveRange(Def, isCC);
LR->setColor(MRI.getClassRegNum(OpI.getMachineOperand().getReg(),
getClassId));
}
- }
+ }
// iterate over implicit MI operands and create a new LR
// for each operand that is defined by the instruction
for (unsigned i = 0; i < MInst->getNumImplicitRefs(); ++i)
- if (MInst->getImplicitOp(i).isDef()) {
- const Value *Def = MInst->getImplicitRef(i);
+ if (MInst->getImplicitOp(i).isDef()) {
+ const Value *Def = MInst->getImplicitRef(i);
V9LiveRange* LR = createOrAddToLiveRange(Def, /*isCC*/ false);
// If the implicit operand has a pre-assigned register,
MInst->getImplicitOp(i).getReg(),
getClassId));
}
- }
+ }
} // for all machine instructions in the BB
} // for all BBs in function
for each definition (def) in inst
for each operand (op) of inst that is a use
if the def and op are of the same register type
- if the def and op do not interfere //i.e., not simultaneously live
- if (degree(LR of def) + degree(LR of op)) <= # avail regs
- if both LRs do not have suggested colors
- merge2IGNodes(def, op) // i.e., merge 2 LRs
+ if the def and op do not interfere //i.e., not simultaneously live
+ if (degree(LR of def) + degree(LR of op)) <= # avail regs
+ if both LRs do not have suggested colors
+ merge2IGNodes(def, op) // i.e., merge 2 LRs
*/
//---------------------------------------------------------------------------
const MachineInstr *MI = MII;
if( DEBUG_RA >= RA_DEBUG_LiveRanges) {
- std::cerr << " *Iterating over machine instr ";
- MI->dump();
- std::cerr << "\n";
+ std::cerr << " *Iterating over machine instr ";
+ MI->dump();
+ std::cerr << "\n";
}
// iterate over MI operands to find defs
for(MachineInstr::const_val_op_iterator DefI = MI->begin(),
DefE = MI->end(); DefI != DefE; ++DefI) {
- if (DefI.isDef()) { // this operand is modified
- V9LiveRange *LROfDef = getLiveRangeForValue( *DefI );
- RegClass *RCOfDef = LROfDef->getRegClass();
+ if (DefI.isDef()) { // this operand is modified
+ V9LiveRange *LROfDef = getLiveRangeForValue( *DefI );
+ RegClass *RCOfDef = LROfDef->getRegClass();
- MachineInstr::const_val_op_iterator UseI = MI->begin(),
+ MachineInstr::const_val_op_iterator UseI = MI->begin(),
UseE = MI->end();
- for( ; UseI != UseE; ++UseI) { // for all uses
- V9LiveRange *LROfUse = getLiveRangeForValue( *UseI );
- if (!LROfUse) { // if LR of use is not found
- //don't warn about labels
- if (!isa<BasicBlock>(*UseI) && DEBUG_RA >= RA_DEBUG_LiveRanges)
- std::cerr << " !! Warning: No LR for use " << RAV(*UseI)<< "\n";
- continue; // ignore and continue
- }
-
- if (LROfUse == LROfDef) // nothing to merge if they are same
- continue;
-
- if (MRI.getRegTypeForLR(LROfDef) ==
+ for( ; UseI != UseE; ++UseI) { // for all uses
+ V9LiveRange *LROfUse = getLiveRangeForValue( *UseI );
+ if (!LROfUse) { // if LR of use is not found
+ //don't warn about labels
+ if (!isa<BasicBlock>(*UseI) && DEBUG_RA >= RA_DEBUG_LiveRanges)
+ std::cerr << " !! Warning: No LR for use " << RAV(*UseI)<< "\n";
+ continue; // ignore and continue
+ }
+
+ if (LROfUse == LROfDef) // nothing to merge if they are same
+ continue;
+
+ if (MRI.getRegTypeForLR(LROfDef) ==
MRI.getRegTypeForLR(LROfUse)) {
- // If the two RegTypes are the same
- if (!RCOfDef->getInterference(LROfDef, LROfUse) ) {
+ // If the two RegTypes are the same
+ if (!RCOfDef->getInterference(LROfDef, LROfUse) ) {
- unsigned CombinedDegree =
- LROfDef->getUserIGNode()->getNumOfNeighbors() +
- LROfUse->getUserIGNode()->getNumOfNeighbors();
+ unsigned CombinedDegree =
+ LROfDef->getUserIGNode()->getNumOfNeighbors() +
+ LROfUse->getUserIGNode()->getNumOfNeighbors();
if (CombinedDegree > RCOfDef->getNumOfAvailRegs()) {
// get more precise estimate of combined degree
getCombinedDegree(LROfUse->getUserIGNode());
}
- if (CombinedDegree <= RCOfDef->getNumOfAvailRegs()) {
- // if both LRs do not have different pre-assigned colors
- // and both LRs do not have suggested colors
+ if (CombinedDegree <= RCOfDef->getNumOfAvailRegs()) {
+ // if both LRs do not have different pre-assigned colors
+ // and both LRs do not have suggested colors
if (! InterfsPreventCoalescing(*LROfDef, *LROfUse)) {
- RCOfDef->mergeIGNodesOfLRs(LROfDef, LROfUse);
- unionAndUpdateLRs(LROfDef, LROfUse);
- }
-
- } // if combined degree is less than # of regs
- } // if def and use do not interfere
- }// if reg classes are the same
- } // for all uses
- } // if def
+ RCOfDef->mergeIGNodesOfLRs(LROfDef, LROfUse);
+ unionAndUpdateLRs(LROfDef, LROfUse);
+ }
+
+ } // if combined degree is less than # of regs
+ } // if def and use do not interfere
+ }// if reg classes are the same
+ } // for all uses
+ } // if def
} // for all defs
} // for all machine instructions
} // for all BBs
public:
LiveRangeInfo(const Function *F,
- const TargetMachine& tm,
- std::vector<RegClass *> & RCList);
+ const TargetMachine& tm,
+ std::vector<RegClass *> & RCList);
/// Destructor to destroy all LiveRanges in the V9LiveRange Map
/// instruction.
///
void PhyRegAlloc::addInterference(const Value *Def, const ValueSet *LVSet,
- bool isCallInst) {
+ bool isCallInst) {
ValueSet::const_iterator LIt = LVSet->begin();
// get the live range of instruction
/// the return value does not interfere with that call itself).
///
void PhyRegAlloc::setCallInterferences(const MachineInstr *MInst,
- const ValueSet *LVSetAft) {
+ const ValueSet *LVSetAft) {
if (DEBUG_RA >= RA_DEBUG_Interference)
std::cerr << "\n For call inst: " << *MInst;
std::cerr << "\n\tLR after Call: " << *LR << "\n";
LR->setCallInterference();
if (DEBUG_RA >= RA_DEBUG_Interference)
- std::cerr << "\n ++After adding call interference for LR: " << *LR << "\n";
+ std::cerr << "\n ++After adding call interference for LR: " << *LR << "\n";
}
}
bool isCallInst = TM.getInstrInfo()->isCall(MInst->getOpcode());
if (isCallInst) {
- // set the isCallInterference flag of each live range which extends
- // across this call instruction. This information is used by graph
- // coloring algorithm to avoid allocating volatile colors to live ranges
- // that span across calls (since they have to be saved/restored)
- setCallInterferences(MInst, &LVSetAI);
+ // set the isCallInterference flag of each live range which extends
+ // across this call instruction. This information is used by graph
+ // coloring algorithm to avoid allocating volatile colors to live ranges
+ // that span across calls (since they have to be saved/restored)
+ setCallInterferences(MInst, &LVSetAI);
}
// iterate over all MI operands to find defs
for (MachineInstr::const_val_op_iterator OpI = MInst->begin(),
OpE = MInst->end(); OpI != OpE; ++OpI) {
- if (OpI.isDef()) // create a new LR since def
- addInterference(*OpI, &LVSetAI, isCallInst);
+ if (OpI.isDef()) // create a new LR since def
+ addInterference(*OpI, &LVSetAI, isCallInst);
- // Calculate the spill cost of each live range
- V9LiveRange *LR = LRI->getLiveRangeForValue(*OpI);
- if (LR) LR->addSpillCost(BBLoopDepthCost);
+ // Calculate the spill cost of each live range
+ V9LiveRange *LR = LRI->getLiveRangeForValue(*OpI);
+ if (LR) LR->addSpillCost(BBLoopDepthCost);
}
// Also add interference for any implicit definitions in a machine
// instr (currently, only calls have this).
unsigned NumOfImpRefs = MInst->getNumImplicitRefs();
for (unsigned z=0; z < NumOfImpRefs; z++)
if (MInst->getImplicitOp(z).isDef())
- addInterference( MInst->getImplicitRef(z), &LVSetAI, isCallInst );
+ addInterference( MInst->getImplicitRef(z), &LVSetAI, isCallInst );
} // for all machine instructions in BB
} // for all BBs in function
const V9LiveRange *LROfOp2 = LRI->getLiveRangeForValue(*It2);
if (LROfOp2) {
- RegClass *RCOfOp1 = LROfOp1->getRegClass();
- RegClass *RCOfOp2 = LROfOp2->getRegClass();
+ RegClass *RCOfOp1 = LROfOp1->getRegClass();
+ RegClass *RCOfOp2 = LROfOp2->getRegClass();
- if (RCOfOp1 == RCOfOp2 ){
- RCOfOp1->setInterference( LROfOp1, LROfOp2 );
- setInterf = true;
- }
+ if (RCOfOp1 == RCOfOp2 ){
+ RCOfOp1->setInterference( LROfOp1, LROfOp2 );
+ setInterf = true;
+ }
} // if Op2 has a LR
} // for all other defs in machine instr
} // for all operands in an instruction
// do not process Phis
if (MInst->getOpcode() == V9::PHI)
- continue;
+ continue;
// if there are any added instructions...
if (AddedInstrMap.count(MInst)) {
void PhyRegAlloc::insertCode4SpilledLR(const V9LiveRange *LR,
MachineBasicBlock::iterator& MII,
MachineBasicBlock &MBB,
- const unsigned OpNum) {
+ const unsigned OpNum) {
MachineInstr *MInst = MII;
const BasicBlock *BB = MBB.getBasicBlock();
assert((! TM.getInstrInfo()->isCall(MInst->getOpcode()) || OpNum == 0) &&
"Outgoing arg of a call must be handled elsewhere (func arg ok)");
assert(! TM.getInstrInfo()->isReturn(MInst->getOpcode()) &&
- "Return value of a ret must be handled elsewhere");
+ "Return value of a ret must be handled elsewhere");
MachineOperand& Op = MInst->getOperand(OpNum);
bool isDef = Op.isDef();
if (LR) {
if (! LR->isMarkedForSpill()) {
assert(LR->hasColor() && "LR is neither spilled nor colored?");
- unsigned RCID = LR->getRegClassID();
- unsigned Color = LR->getColor();
-
- if (MRI.isRegVolatile(RCID, Color) ) {
- // if this is a call to the first-level reoptimizer
- // instrumentation entry point, and the register is not
- // modified by call, don't save and restore it.
- if (isLLVMFirstTrigger && !MRI.modifiedByCall(RCID, Color))
- continue;
-
- // if the value is in both LV sets (i.e., live before and after
- // the call machine instruction)
- unsigned Reg = MRI.getUnifiedRegNum(RCID, Color);
-
- // if we haven't already pushed this register...
- if( PushedRegSet.find(Reg) == PushedRegSet.end() ) {
- unsigned RegType = MRI.getRegTypeForLR(LR);
-
- // Now get two instructions - to push on stack and pop from stack
- // and add them to InstrnsBefore and InstrnsAfter of the
- // call instruction
- int StackOff =
+ unsigned RCID = LR->getRegClassID();
+ unsigned Color = LR->getColor();
+
+ if (MRI.isRegVolatile(RCID, Color) ) {
+ // if this is a call to the first-level reoptimizer
+ // instrumentation entry point, and the register is not
+ // modified by call, don't save and restore it.
+ if (isLLVMFirstTrigger && !MRI.modifiedByCall(RCID, Color))
+ continue;
+
+ // if the value is in both LV sets (i.e., live before and after
+ // the call machine instruction)
+ unsigned Reg = MRI.getUnifiedRegNum(RCID, Color);
+
+ // if we haven't already pushed this register...
+ if( PushedRegSet.find(Reg) == PushedRegSet.end() ) {
+ unsigned RegType = MRI.getRegTypeForLR(LR);
+
+ // Now get two instructions - to push on stack and pop from stack
+ // and add them to InstrnsBefore and InstrnsAfter of the
+ // call instruction
+ int StackOff =
MF->getInfo<SparcV9FunctionInfo>()->pushTempValue(MRI.getSpilledRegSize(RegType));
- //---- Insert code for pushing the reg on stack ----------
+ //---- Insert code for pushing the reg on stack ----------
- std::vector<MachineInstr*> AdIBef, AdIAft;
+ std::vector<MachineInstr*> AdIBef, AdIAft;
// We may need a scratch register to copy the saved value
// to/from memory. This may itself have to insert code to
instrnsBefore.insert(instrnsBefore.end(),
AdIAft.begin(), AdIAft.end());
- //---- Insert code for popping the reg from the stack ----------
- AdIBef.clear();
+ //---- Insert code for popping the reg from the stack ----------
+ AdIBef.clear();
AdIAft.clear();
// We may need a scratch register to copy the saved value
instrnsAfter.insert(instrnsAfter.end(),
AdIBef.begin(), AdIBef.end());
- MRI.cpMem2RegMI(instrnsAfter, MRI.getFramePointer(), StackOff,
+ MRI.cpMem2RegMI(instrnsAfter, MRI.getFramePointer(), StackOff,
Reg, RegType, scratchReg);
if (AdIAft.size() > 0)
instrnsAfter.insert(instrnsAfter.end(),
AdIAft.begin(), AdIAft.end());
-
- PushedRegSet.insert(Reg);
+
+ PushedRegSet.insert(Reg);
- if(DEBUG_RA) {
- std::cerr << "\nFor call inst:" << *CallMI;
- std::cerr << " -inserted caller saving instrs: Before:\n\t ";
+ if(DEBUG_RA) {
+ std::cerr << "\nFor call inst:" << *CallMI;
+ std::cerr << " -inserted caller saving instrs: Before:\n\t ";
for_each(instrnsBefore.begin(), instrnsBefore.end(),
std::mem_fun(&MachineInstr::dump));
- std::cerr << " -and After:\n\t ";
+ std::cerr << " -and After:\n\t ";
for_each(instrnsAfter.begin(), instrnsAfter.end(),
std::mem_fun(&MachineInstr::dump));
- }
- } // if not already pushed
- } // if LR has a volatile color
+ }
+ } // if not already pushed
+ } // if LR has a volatile color
} // if LR has color
} // if there is a LR for Var
} // for each value in the LV set after instruction
// RegClassList. This must be done before calling constructLiveRanges().
for (unsigned rc = 0; rc != NumOfRegClasses; ++rc)
RegClassList.push_back (new RegClass (Fn, TM.getRegInfo(),
- MRI.getMachineRegClass(rc)));
+ MRI.getMachineRegClass(rc)));
LRI->constructLiveRanges(); // create LR info
if (DEBUG_RA >= RA_DEBUG_LiveRanges)
SavedStateMapTy FnAllocState;
void addInterference(const Value *Def, const ValueSet *LVSet,
- bool isCallInst);
+ bool isCallInst);
bool markAllocatedRegs(MachineInstr* MInst);
void addInterferencesForArgs();
void finishSavingState(Module &M);
void setCallInterferences(const MachineInstr *MI,
- const ValueSet *LVSetAft);
+ const ValueSet *LVSetAft);
void move2DelayedInstr(const MachineInstr *OrigMI,
- const MachineInstr *DelayedMI);
+ const MachineInstr *DelayedMI);
void markUnusableSugColors();
void allocateStackSpace4SpilledLRs();
MachineBasicBlock &MBB);
int getUsableUniRegAtMI(int RegType, const ValueSet *LVSetBef,
- MachineInstr *MI,
+ MachineInstr *MI,
std::vector<MachineInstr*>& MIBef,
std::vector<MachineInstr*>& MIAft);
//----------------------------------------------------------------------------
RegClass::RegClass(const Function *M,
const SparcV9RegInfo *_MRI_,
- const TargetRegClassInfo *_MRC_)
+ const TargetRegClassInfo *_MRC_)
: Meth(M), MRI(_MRI_), MRC(_MRC_),
RegClassID( _MRC_->getRegClassID() ),
IG(this), IGNodeStack() {
IGNode->pushOnStack(); // set OnStack and dec deg of neighs
if (DEBUG_RA >= RA_DEBUG_Coloring) {
- std::cerr << " pushed un-constrained IGNode " << IGNode->getIndex()
+ std::cerr << " pushed un-constrained IGNode " << IGNode->getIndex()
<< " on to stack\n";
}
}
if (!IGNode->isOnStack()) {
double SpillCost = (double) IGNode->getParentLR()->getSpillCost() /
- (double) (IGNode->getCurDegree() + 1);
+ (double) (IGNode->getCurDegree() + 1);
if (isFirstNode) { // for the first IG node
- MinSpillCost = SpillCost;
- MinCostIGNode = IGNode;
- isFirstNode = false;
+ MinSpillCost = SpillCost;
+ MinCostIGNode = IGNode;
+ isFirstNode = false;
} else if (MinSpillCost > SpillCost) {
- MinSpillCost = SpillCost;
- MinCostIGNode = IGNode;
+ MinSpillCost = SpillCost;
+ MinCostIGNode = IGNode;
}
}
}
public:
RegClass(const Function *M,
- const SparcV9RegInfo *_MRI_,
- const TargetRegClassInfo *_MRC_);
+ const SparcV9RegInfo *_MRI_,
+ const TargetRegClassInfo *_MRC_);
inline void createInterferenceGraph() { IG.createGraph(); }
{ IG.addLRToIG(LR); }
inline void setInterference(const V9LiveRange *const LR1,
- const V9LiveRange *const LR2)
+ const V9LiveRange *const LR2)
{ IG.setInterference(LR1, LR2); }
inline unsigned getInterference(const V9LiveRange *const LR1,
- const V9LiveRange *const LR2) const
+ const V9LiveRange *const LR2) const
{ return IG.getInterference(LR1, LR2); }
inline void mergeIGNodesOfLRs(const V9LiveRange *const LR1,
- V9LiveRange *const LR2)
+ V9LiveRange *const LR2)
{ IG.mergeIGNodesOfLRs(LR1, LR2); }
// construct a forest of BURG instruction trees (class InstrForest) and then
// uses the BURG-generated tree grammar (BURM) to find the optimal instruction
// sequences for the SparcV9.
-//
+//
//===----------------------------------------------------------------------===//
#include "MachineInstrAnnot.h"
RootSet treeRoots;
public:
- /*ctor*/ InstrForest (Function *F);
- /*dtor*/ ~InstrForest ();
+ /*ctor*/ InstrForest (Function *F);
+ /*dtor*/ ~InstrForest ();
/// getTreeNodeForInstr - Returns the tree node for an Instruction.
///
// Distinguish special cases of some instructions such as Ret and Br
//
if (opLabel == Instruction::Ret && cast<ReturnInst>(I)->getReturnValue()) {
- opLabel = RetValueOp; // ret(value) operation
+ opLabel = RetValueOp; // ret(value) operation
}
else if (opLabel ==Instruction::Br && !cast<BranchInst>(I)->isUnconditional())
{
- opLabel = BrCondOp; // br(cond) operation
+ opLabel = BrCondOp; // br(cond) operation
} else if (opLabel >= Instruction::SetEQ && opLabel <= Instruction::SetGT) {
- opLabel = SetCCOp; // common label for all SetCC ops
+ opLabel = SetCCOp; // common label for all SetCC ops
} else if (opLabel == Instruction::Alloca && I->getNumOperands() > 0) {
- opLabel = AllocaN; // Alloca(ptr, N) operation
+ opLabel = AllocaN; // Alloca(ptr, N) operation
} else if (opLabel == Instruction::GetElementPtr &&
cast<GetElementPtrInst>(I)->hasIndices()) {
- opLabel = opLabel + 100; // getElem with index vector
+ opLabel = opLabel + 100; // getElem with index vector
} else if (opLabel == Instruction::Xor &&
BinaryOperator::isNot(I)) {
opLabel = (I->getType() == Type::BoolTy)? NotOp // boolean Not operator
opLabel == Instruction::Xor) {
// Distinguish bitwise operators from logical operators!
if (I->getType() != Type::BoolTy)
- opLabel = opLabel + 100; // bitwise operator
+ opLabel = opLabel + 100; // bitwise operator
} else if (opLabel == Instruction::Cast) {
const Type *ITy = I->getType();
switch(ITy->getTypeID())
inline void InstrForest::noteTreeNodeForInstr(Instruction *instr,
InstructionNode *treeNode) {
(*this)[instr] = treeNode;
- treeRoots.push_back(treeNode); // mark node as root of a new tree
+ treeRoots.push_back(treeNode); // mark node as root of a new tree
}
inline void InstrForest::setLeftChild(InstrTreeNode *parent,
// that should be considered a data value.
// Check latter condition here just to simplify the next IF.
bool includeAddressOperand =
- (isa<BasicBlock>(operand) || isa<Function>(operand))
- && !instr->isTerminator();
+ (isa<BasicBlock>(operand) || isa<Function>(operand))
+ && !instr->isTerminator();
if (includeAddressOperand || isa<Instruction>(operand) ||
- isa<Constant>(operand) || isa<Argument>(operand)) {
+
isa<Constant>(operand) || isa<Argument>(operand)) {
// This operand is a data value.
// An instruction that computes the incoming value is added as a
// child of the current instruction if:
// the value has only a single use
// AND both instructions are in the same basic block.
// AND the current instruction is not a PHI (because the incoming
- // value is conceptually in a predecessor block,
- // even though it may be in the same static block)
+ // value is conceptually in a predecessor block,
+ // even though it may be in the same static block)
// (Note that if the value has only a single use (viz., `instr'),
// the def of the value can be safely moved just before instr
// and therefore it is safe to combine these two instructions.)
static inline void
CreateSETSWConst(int32_t C,
Instruction* dest, std::vector<MachineInstr*>& mvec,
- MachineCodeForInstruction& mcfi, Value* val) {
+ MachineCodeForInstruction& mcfi, Value* val) {
//TmpInstruction for intermediate values
TmpInstruction *tmpReg = new TmpInstruction(mcfi, (Instruction*) val);
CreateSETXConst(uint64_t C,
Instruction* tmpReg, Instruction* dest,
std::vector<MachineInstr*>& mvec,
- MachineCodeForInstruction& mcfi, Value* val) {
+ MachineCodeForInstruction& mcfi, Value* val) {
assert(C > (unsigned int) ~0 && "Use SETUW/SETSW for 32-bit values!");
MachineInstr* MI;
static inline void
CreateSETXLabel(Value* val, Instruction* tmpReg,
Instruction* dest, std::vector<MachineInstr*>& mvec,
- MachineCodeForInstruction& mcfi) {
+ MachineCodeForInstruction& mcfi) {
assert(isa<Constant>(val) &&
"I only know about constant values and global addresses");
MachineOperand::MachineOperandType
ChooseRegOrImmed(Value* val,
MachineOpCode opCode, const TargetMachine& target,
- bool canUseImmed, unsigned int& getMachineRegNum,
- int64_t& getImmedValue) {
+ bool canUseImmed, unsigned int& getMachineRegNum,
+ int64_t& getImmedValue) {
getMachineRegNum = 0;
getImmedValue = 0;
// Cases worth optimizing are:
// (1) Add with 0 for float or double: use an FMOV of appropriate type,
- // instead of an FADD (1 vs 3 cycles). There is no integer MOV.
+ // instead of an FADD (1 vs 3 cycles). There is no integer MOV.
if (ConstantFP *FPC = dyn_cast<ConstantFP>(constOp)) {
double dval = FPC->getValue();
if (dval == 0.0)
// Cases worth optimizing are:
// (1) Sub with 0 for float or double: use an FMOV of appropriate type,
- // instead of an FSUB (1 vs 3 cycles). There is no integer MOV.
+ // instead of an FSUB (1 vs 3 cycles). There is no integer MOV.
if (ConstantFP *FPC = dyn_cast<ConstantFP>(constOp)) {
double dval = FPC->getValue();
if (dval == 0.0)
M = BuildMI(V9::ADDr,3).addReg(lval).addMReg(Zero).addRegDef(destVal);
mvec.push_back(M);
} else if (isPowerOf2(C, pow)) {
- if(!needNeg) {
+ if(!needNeg) {
unsigned opSize = target.getTargetData().getTypeSize(resultType);
MachineOpCode opCode = (opSize <= 32)? V9::SLLr5 : V9::SLLXr6;
CreateShiftInstructions(target, F, opCode, lval, NULL, pow,
destVal, mvec, mcfi);
- }
- else {
- //Create tmp instruction to hold intermeidate value, since we need
- //to negate the result
- tmpNeg = new TmpInstruction(mcfi, lval);
- unsigned opSize = target.getTargetData().getTypeSize(resultType);
- MachineOpCode opCode = (opSize <= 32)? V9::SLLr5 : V9::SLLXr6;
- CreateShiftInstructions(target, F, opCode, lval, NULL, pow,
- tmpNeg, mvec, mcfi);
- }
-
+ }
+ else {
+ //Create tmp instruction to hold intermeidate value, since we need
+ //to negate the result
+ tmpNeg = new TmpInstruction(mcfi, lval);
+ unsigned opSize = target.getTargetData().getTypeSize(resultType);
+ MachineOpCode opCode = (opSize <= 32)? V9::SLLr5 : V9::SLLXr6;
+ CreateShiftInstructions(target, F, opCode, lval, NULL, pow,
+ tmpNeg, mvec, mcfi);
+ }
+
}
if (mvec.size() > 0 && needNeg) {
- MachineInstr* M = 0;
- if(tmpNeg)
+ MachineInstr* M = 0;
+ if(tmpNeg)
// insert <reg = SUB 0, reg> after the instr to flip the sign
- M = CreateIntNegInstruction(target, tmpNeg, destVal);
- else
- M = CreateIntNegInstruction(target, destVal);
+ M = CreateIntNegInstruction(target, tmpNeg, destVal);
+ else
+ M = CreateIntNegInstruction(target, destVal);
mvec.push_back(M);
}
}
// sra N, 31, t1 // t1 = ~0, if N < 0, 0 else
// srl t1, 32-k, t2 // t2 = 2^k - 1, if N < 0, 0 else
// add t2, N, t3 // t3 = N + 2^k -1, if N < 0, N else
- // sra t3, k, result // result = N / 2^k
+ // sra t3, k, result // result = N / 2^k
//
// If N is 64 bits, use:
// srax N, k-1, t1 // t1 = sign bit in high k positions
// srlx t1, 64-k, t2 // t2 = 2^k - 1, if N < 0, 0 else
// add t2, N, t3 // t3 = N + 2^k -1, if N < 0, N else
- // sra t3, k, result // result = N / 2^k
+ // sra t3, k, result // result = N / 2^k
TmpInstruction *sraTmp, *srlTmp, *addTmp;
MachineCodeForInstruction& mcfi
= MachineCodeForInstruction::get(destVal);
if (((int)paddedSize) > 8 * SparcV9FrameInfo::SizeOfEachArgOnStack ||
!target.getInstrInfo()->constantFitsInImmedField(V9::LDXi,offsetFromFP)) {
CreateCodeForVariableSizeAlloca(target, result, tsize,
- ConstantSInt::get(Type::IntTy,numElements),
- getMvec);
+ ConstantSInt::get(Type::IntTy,numElements),
+ getMvec);
return;
}
/// offset is not a constant or if it cannot fit in the offset field. Use
/// [reg+offset] in all other cases. This assumes that all array refs are
/// "lowered" to one of these forms:
-/// %x = load (subarray*) ptr, constant ; single constant offset
-/// %x = load (subarray*) ptr, offsetVal ; single non-constant offset
+/// %x = load (subarray*) ptr, constant ; single constant offset
+/// %x = load (subarray*) ptr, offsetVal ; single non-constant offset
/// Generally, this should happen via strength reduction + LICM. Also, strength
/// reduction should take care of using the same register for the loop index
/// variable and an array index, when that is profitable.
///
extern bool ThisIsAChainRule(int eruleno) {
switch(eruleno) {
- case 111: // stmt: reg
+ case 111: // stmt: reg
case 123:
case 124:
case 125:
void GetInstructionsByRule(InstructionNode* subtreeRoot, int ruleForNode,
short* nts, TargetMachine &target,
std::vector<MachineInstr*>& mvec) {
- bool checkCast = false; // initialize here to use fall-through
+ bool checkCast = false; // initialize here to use fall-through
bool maskUnsignedResult = false;
int nextRule;
int forwardOperandNum = -1;
case 1: // stmt: Ret
case 2: // stmt: RetValue(reg)
{ // NOTE: Prepass of register allocation is responsible
- // for moving return value to appropriate register.
+ // for moving return value to appropriate register.
// Copy the return value to the required return register.
// Mark the return Value as an implicit ref of the RET instr..
// Mark the return-address register as a hidden virtual reg.
- // Finally put a NOP in the delay slot.
+ // Finally put a NOP in the delay slot.
ReturnInst *returnInstr=cast<ReturnInst>(subtreeRoot->getInstruction());
Value* retVal = returnInstr->getReturnValue();
MachineCodeForInstruction& mcfi =
break;
}
- case 3: // stmt: Store(reg,reg)
- case 4: // stmt: Store(reg,ptrreg)
+ case 3: // stmt: Store(reg,reg)
+ case 4: // stmt: Store(reg,ptrreg)
SetOperandsForMemInstr(ChooseStoreInstruction(
subtreeRoot->leftChild()->getValue()->getType()),
mvec, subtreeRoot, target);
break;
- case 5: // stmt: BrUncond
+ case 5: // stmt: BrUncond
{
BranchInst *BI = cast<BranchInst>(subtreeRoot->getInstruction());
mvec.push_back(BuildMI(V9::BA, 1).addPCDisp(BI->getSuccessor(0)));
break;
}
- case 206: // stmt: BrCond(setCCconst)
+ case 206: // stmt: BrCond(setCCconst)
{ // setCCconst => boolean was computed with `%b = setCC type reg1 const'
// If the constant is ZERO, we can use the branch-on-integer-register
// instructions and avoid the SUBcc instruction entirely.
// ELSE FALL THROUGH
}
- case 6: // stmt: BrCond(setCC)
+ case 6: // stmt: BrCond(setCC)
{ // bool => boolean was computed with SetCC.
// The branch to use depends on whether it is FP, signed, or unsigned.
// If it is an integer CC, we also need to find the unique
break;
}
- case 208: // stmt: BrCond(boolconst)
+ case 208: // stmt: BrCond(boolconst)
{
// boolconst => boolean is a constant; use BA to first or second label
Constant* constVal =
break;
}
- case 8: // stmt: BrCond(boolreg)
+ case 8: // stmt: BrCond(boolreg)
{ // boolreg => boolean is recorded in an integer register.
// Use branch-on-integer-register instruction.
//
break;
}
- case 9: // stmt: Switch(reg)
+ case 9: // stmt: Switch(reg)
assert(0 && "*** SWITCH instruction is not implemented yet.");
break;
- case 10: // reg: VRegList(reg, reg)
+ case 10: // reg: VRegList(reg, reg)
assert(0 && "VRegList should never be the topmost non-chain rule");
break;
- case 21: // bool: Not(bool,reg): Compute with a conditional-move-on-reg
+ case 21: // bool: Not(bool,reg): Compute with a conditional-move-on-reg
{ // First find the unary operand. It may be left or right, usually right.
Instruction* notI = subtreeRoot->getInstruction();
Value* notArg = BinaryOperator::getNotArgument(
break;
}
- case 421: // reg: BNot(reg,reg): Compute as reg = reg XOR-NOT 0
+ case 421: // reg: BNot(reg,reg): Compute as reg = reg XOR-NOT 0
{ // First find the unary operand. It may be left or right, usually right.
Value* notArg = BinaryOperator::getNotArgument(
cast<BinaryOperator>(subtreeRoot->getInstruction()));
break;
}
- case 322: // reg: Not(tobool, reg):
+ case 322: // reg: Not(tobool, reg):
// Fold CAST-TO-BOOL with NOT by inverting the sense of cast-to-bool
foldCase = true;
// Just fall through!
- case 22: // reg: ToBoolTy(reg):
+ case 22: // reg: ToBoolTy(reg):
{
Instruction* castI = subtreeRoot->getInstruction();
Value* opVal = subtreeRoot->leftChild()->getValue();
- MachineCodeForInstruction &mcfi = MachineCodeForInstruction::get(castI);
- TmpInstruction* tempReg =
- new TmpInstruction(mcfi, opVal);
+ MachineCodeForInstruction &mcfi = MachineCodeForInstruction::get(castI);
+ TmpInstruction* tempReg =
+ new TmpInstruction(mcfi, opVal);
break;
}
- case 23: // reg: ToUByteTy(reg)
- case 24: // reg: ToSByteTy(reg)
- case 25: // reg: ToUShortTy(reg)
- case 26: // reg: ToShortTy(reg)
- case 27: // reg: ToUIntTy(reg)
- case 28: // reg: ToIntTy(reg)
- case 29: // reg: ToULongTy(reg)
- case 30: // reg: ToLongTy(reg)
+ case 23: // reg: ToUByteTy(reg)
+ case 24: // reg: ToSByteTy(reg)
+ case 25: // reg: ToUShortTy(reg)
+ case 26: // reg: ToShortTy(reg)
+ case 27: // reg: ToUIntTy(reg)
+ case 28: // reg: ToIntTy(reg)
+ case 29: // reg: ToULongTy(reg)
+ case 30: // reg: ToLongTy(reg)
{
//======================================================================
// Rules for integer conversions:
break;
}
- case 31: // reg: ToFloatTy(reg):
- case 32: // reg: ToDoubleTy(reg):
- case 232: // reg: ToDoubleTy(Constant):
+ case 31: // reg: ToFloatTy(reg):
+ case 32: // reg: ToDoubleTy(reg):
+ case 232: // reg: ToDoubleTy(Constant):
// If this instruction has a parent (a user) in the tree
// and the user is translated as an FsMULd instruction,
}
break;
- case 19: // reg: ToArrayTy(reg):
- case 20: // reg: ToPointerTy(reg):
+ case 19: // reg: ToArrayTy(reg):
+ case 20: // reg: ToPointerTy(reg):
forwardOperandNum = 0; // forward first operand to user
break;
- case 233: // reg: Add(reg, Constant)
+ case 233: // reg: Add(reg, Constant)
maskUnsignedResult = true;
M = CreateAddConstInstruction(subtreeRoot);
if (M != NULL) {
}
// ELSE FALL THROUGH
- case 33: // reg: Add(reg, reg)
+ case 33: // reg: Add(reg, reg)
maskUnsignedResult = true;
Add3OperandInstr(ChooseAddInstruction(subtreeRoot), subtreeRoot, mvec);
break;
- case 234: // reg: Sub(reg, Constant)
+ case 234: // reg: Sub(reg, Constant)
maskUnsignedResult = true;
M = CreateSubConstInstruction(subtreeRoot);
if (M != NULL) {
}
// ELSE FALL THROUGH
- case 34: // reg: Sub(reg, reg)
+ case 34: // reg: Sub(reg, reg)
maskUnsignedResult = true;
Add3OperandInstr(ChooseSubInstructionByType(
subtreeRoot->getInstruction()->getType()),
subtreeRoot, mvec);
break;
- case 135: // reg: Mul(todouble, todouble)
+ case 135: // reg: Mul(todouble, todouble)
checkCast = true;
// FALL THROUGH
- case 35: // reg: Mul(reg, reg)
+ case 35: // reg: Mul(reg, reg)
{
maskUnsignedResult = true;
MachineOpCode forceOp = ((checkCast && BothFloatToDouble(subtreeRoot))
MachineCodeForInstruction::get(mulInstr),forceOp);
break;
}
- case 335: // reg: Mul(todouble, todoubleConst)
+ case 335: // reg: Mul(todouble, todoubleConst)
checkCast = true;
// FALL THROUGH
- case 235: // reg: Mul(reg, Constant)
+ case 235: // reg: Mul(reg, Constant)
{
maskUnsignedResult = true;
MachineOpCode forceOp = ((checkCast && BothFloatToDouble(subtreeRoot))
forceOp);
break;
}
- case 236: // reg: Div(reg, Constant)
+ case 236: // reg: Div(reg, Constant)
maskUnsignedResult = true;
L = mvec.size();
CreateDivConstInstruction(target, subtreeRoot, mvec);
break;
// ELSE FALL THROUGH
- case 36: // reg: Div(reg, reg)
+ case 36: // reg: Div(reg, reg)
{
maskUnsignedResult = true;
break;
}
- case 37: // reg: Rem(reg, reg)
- case 237: // reg: Rem(reg, Constant)
+ case 37: // reg: Rem(reg, reg)
+ case 237: // reg: Rem(reg, Constant)
{
maskUnsignedResult = true;
break;
}
- case 38: // bool: And(bool, bool)
- case 138: // bool: And(bool, not)
- case 238: // bool: And(bool, boolconst)
- case 338: // reg : BAnd(reg, reg)
- case 538: // reg : BAnd(reg, Constant)
+ case 38: // bool: And(bool, bool)
+ case 138: // bool: And(bool, not)
+ case 238: // bool: And(bool, boolconst)
+ case 338: // reg : BAnd(reg, reg)
+ case 538: // reg : BAnd(reg, Constant)
Add3OperandInstr(V9::ANDr, subtreeRoot, mvec);
break;
- case 438: // bool: BAnd(bool, bnot)
+ case 438: // bool: BAnd(bool, bnot)
{ // Use the argument of NOT as the second argument!
// Mark the NOT node so that no code is generated for it.
// If the type is boolean, set 1 or 0 in the result register.
break;
}
- case 39: // bool: Or(bool, bool)
- case 139: // bool: Or(bool, not)
- case 239: // bool: Or(bool, boolconst)
- case 339: // reg : BOr(reg, reg)
- case 539: // reg : BOr(reg, Constant)
+ case 39: // bool: Or(bool, bool)
+ case 139: // bool: Or(bool, not)
+ case 239: // bool: Or(bool, boolconst)
+ case 339: // reg : BOr(reg, reg)
+ case 539: // reg : BOr(reg, Constant)
Add3OperandInstr(V9::ORr, subtreeRoot, mvec);
break;
- case 439: // bool: BOr(bool, bnot)
+ case 439: // bool: BOr(bool, bnot)
{ // Use the argument of NOT as the second argument!
// Mark the NOT node so that no code is generated for it.
// If the type is boolean, set 1 or 0 in the result register.
break;
}
- case 40: // bool: Xor(bool, bool)
- case 140: // bool: Xor(bool, not)
- case 240: // bool: Xor(bool, boolconst)
- case 340: // reg : BXor(reg, reg)
- case 540: // reg : BXor(reg, Constant)
+ case 40: // bool: Xor(bool, bool)
+ case 140: // bool: Xor(bool, not)
+ case 240: // bool: Xor(bool, boolconst)
+ case 340: // reg : BXor(reg, reg)
+ case 540: // reg : BXor(reg, Constant)
Add3OperandInstr(V9::XORr, subtreeRoot, mvec);
break;
- case 440: // bool: BXor(bool, bnot)
+ case 440: // bool: BXor(bool, bnot)
{ // Use the argument of NOT as the second argument!
// Mark the NOT node so that no code is generated for it.
// If the type is boolean, set 1 or 0 in the result register.
break;
}
- case 41: // setCCconst: SetCC(reg, Constant)
+ case 41: // setCCconst: SetCC(reg, Constant)
{ // Comparison is with a constant:
//
// If the bool result must be computed into a register (see below),
// ELSE FALL THROUGH
}
- case 42: // bool: SetCC(reg, reg):
+ case 42: // bool: SetCC(reg, reg):
{
// This generates a SUBCC instruction, putting the difference in a
// result reg. if needed, and/or setting a condition code if needed.
break;
}
- case 51: // reg: Load(reg)
- case 52: // reg: Load(ptrreg)
+ case 51: // reg: Load(reg)
+ case 52: // reg: Load(ptrreg)
SetOperandsForMemInstr(ChooseLoadInstruction(
subtreeRoot->getValue()->getType()),
mvec, subtreeRoot, target);
break;
- case 55: // reg: GetElemPtr(reg)
- case 56: // reg: GetElemPtrIdx(reg,reg)
+ case 55: // reg: GetElemPtr(reg)
+ case 56: // reg: GetElemPtrIdx(reg,reg)
// If the GetElemPtr was folded into the user (parent), it will be
// caught above. For other cases, we have to compute the address.
SetOperandsForMemInstr(V9::ADDr, mvec, subtreeRoot, target);
break;
- case 57: // reg: Alloca: Implement as 1 instruction:
- { // add %fp, offsetFromFP -> result
+ case 57: // reg: Alloca: Implement as 1 instruction:
+ { // add %fp, offsetFromFP -> result
AllocationInst* instr =
cast<AllocationInst>(subtreeRoot->getInstruction());
unsigned tsize =
break;
}
- case 58: // reg: Alloca(reg): Implement as 3 instructions:
- // mul num, typeSz -> tmp
- // sub %sp, tmp -> %sp
- { // add %sp, frameSizeBelowDynamicArea -> result
+ case 58: // reg: Alloca(reg): Implement as 3 instructions:
+ // mul num, typeSz -> tmp
+ // sub %sp, tmp -> %sp
+ { // add %sp, frameSizeBelowDynamicArea -> result
AllocationInst* instr =
cast<AllocationInst>(subtreeRoot->getInstruction());
const Type* eltType = instr->getAllocatedType();
break;
}
- case 61: // reg: Call
+ case 61: // reg: Call
{ // Generate a direct (CALL) or indirect (JMPL) call.
// Mark the return-address register, the indirection
// register (for indirect calls), the operands of the Call,
break;
}
- case 62: // reg: Shl(reg, reg)
+ case 62: // reg: Shl(reg, reg)
{
Value* argVal1 = subtreeRoot->leftChild()->getValue();
Value* argVal2 = subtreeRoot->rightChild()->getValue();
break;
}
- case 63: // reg: Shr(reg, reg)
+ case 63: // reg: Shr(reg, reg)
{
const Type* opType = subtreeRoot->leftChild()->getValue()->getType();
assert((opType->isInteger() || isa<PointerType>(opType)) &&
break;
}
- case 64: // reg: Phi(reg,reg)
+ case 64: // reg: Phi(reg,reg)
break; // don't forward the value
- case 66: // reg: VAArg (reg): the va_arg instruction
+ case 66: // reg: VAArg (reg): the va_arg instruction
{ // Load argument from stack using current va_list pointer value.
// Use 64-bit load for all non-FP args, and LDDF or double for FP.
Instruction* vaArgI = subtreeRoot->getInstruction();
break;
}
- case 71: // reg: VReg
- case 72: // reg: Constant
+ case 71: // reg: VReg
+ case 72: // reg: Constant
break; // don't forward the value
default:
}
virtual int getOutgoingArgOffset(MachineFunction& mcInfo,
- unsigned argNum) const {
+ unsigned argNum) const {
return FirstOutgoingArgOffsetFromSP + argNum * SizeOfEachArgOnStack;
}
// A forest of BURG instruction trees (class InstrForest) which represents
// a function to the BURG-based instruction selector, and a bunch of constants
// and declarations used by the generated BURG code.
-//
+//
//===----------------------------------------------------------------------===//
#ifndef SPARCV9INSTRFOREST_H
/// opcode returned by Instruction::getOpcode().
///
static const int
- InvalidOp = -1,
+ InvalidOp = -1,
VRegListOp = 97,
- VRegNodeOp = 98,
+ VRegNodeOp = 98,
ConstantNodeOp = 99,
- LabelNodeOp = 100,
- RetValueOp = 100 + Instruction::Ret, // 101
- BrCondOp = 100 + Instruction::Br, // 102
+ LabelNodeOp = 100,
+ RetValueOp = 100 + Instruction::Ret, // 101
+ BrCondOp = 100 + Instruction::Br, // 102
BAndOp = 100 + Instruction::And, // 111
BOrOp = 100 + Instruction::Or, // 112
BXorOp = 100 + Instruction::Xor, // 113
BNotOp = 200 + Instruction::Xor, // 213
NotOp = 300 + Instruction::Xor, // 313
- SetCCOp = 100 + Instruction::SetEQ, // 114
- AllocaN = 100 + Instruction::Alloca, // 122
- LoadIdx = 100 + Instruction::Load, // 123
- GetElemPtrIdx = 100 + Instruction::GetElementPtr, // 125
- ToBoolTy = 100 + Instruction::Cast; // 127
+ SetCCOp = 100 + Instruction::SetEQ, // 114
+ AllocaN = 100 + Instruction::Alloca, // 122
+ LoadIdx = 100 + Instruction::Load, // 123
+ GetElemPtrIdx = 100 + Instruction::GetElementPtr, // 125
+ ToBoolTy = 100 + Instruction::Cast; // 127
static const int
- ToUByteTy = ToBoolTy + 1,
- ToSByteTy = ToBoolTy + 2,
- ToUShortTy = ToBoolTy + 3,
- ToShortTy = ToBoolTy + 4,
- ToUIntTy = ToBoolTy + 5,
- ToIntTy = ToBoolTy + 6,
- ToULongTy = ToBoolTy + 7,
- ToLongTy = ToBoolTy + 8,
- ToFloatTy = ToBoolTy + 9,
- ToDoubleTy = ToBoolTy + 10,
- ToArrayTy = ToBoolTy + 11,
- ToPointerTy = ToBoolTy + 12;
+ ToUByteTy = ToBoolTy + 1,
+ ToSByteTy = ToBoolTy + 2,
+ ToUShortTy = ToBoolTy + 3,
+ ToShortTy = ToBoolTy + 4,
+ ToUIntTy = ToBoolTy + 5,
+ ToIntTy = ToBoolTy + 6,
+ ToULongTy = ToBoolTy + 7,
+ ToLongTy = ToBoolTy + 8,
+ ToFloatTy = ToBoolTy + 9,
+ ToDoubleTy = ToBoolTy + 10,
+ ToArrayTy = ToBoolTy + 11,
+ ToPointerTy = ToBoolTy + 12;
/// Data types needed by BURG
///
namespace llvm {
class InstrTreeNode;
};
-extern short* burm_nts[];
-extern StateLabel burm_label (InstrTreeNode* p);
-extern StateLabel burm_state (OpLabel op, StateLabel leftState,
- StateLabel rightState);
-extern StateLabel burm_rule (StateLabel state, int goalNT);
-extern InstrTreeNode** burm_kids (InstrTreeNode* p, int eruleno,
- InstrTreeNode* kids[]);
-extern void printcover (InstrTreeNode*, int, int);
-extern void printtree (InstrTreeNode*);
-extern int treecost (InstrTreeNode*, int, int);
-extern void printMatches (InstrTreeNode*);
+extern short* burm_nts[];
+extern StateLabel burm_label (InstrTreeNode* p);
+extern StateLabel burm_state (OpLabel op, StateLabel leftState,
+ StateLabel rightState);
+extern StateLabel burm_rule (StateLabel state, int goalNT);
+extern InstrTreeNode** burm_kids (InstrTreeNode* p, int eruleno,
+ InstrTreeNode* kids[]);
+extern void printcover (InstrTreeNode*, int, int);
+extern void printtree (InstrTreeNode*);
+extern int treecost (InstrTreeNode*, int, int);
+extern void printMatches (InstrTreeNode*);
namespace llvm {
void operator=(const InstrTreeNode &); // DO NOT IMPLEMENT
public:
enum InstrTreeNodeType { NTInstructionNode,
- NTVRegListNode,
- NTVRegNode,
- NTConstNode,
- NTLabelNode };
+ NTVRegListNode,
+ NTVRegNode,
+ NTConstNode,
+ NTLabelNode };
InstrTreeNode* LeftChild;
InstrTreeNode* RightChild;
InstrTreeNode* Parent;
protected:
InstrTreeNodeType treeNodeType;
- Value* val;
+ Value* val;
public:
InstrTreeNode(InstrTreeNodeType nodeType, Value* _val)
delete LeftChild;
delete RightChild;
}
- InstrTreeNodeType getNodeType () const { return treeNodeType; }
- Value* getValue () const { return val; }
- inline OpLabel getOpLabel () const { return opLabel; }
+ InstrTreeNodeType getNodeType () const { return treeNodeType; }
+ Value* getValue () const { return val; }
+ inline OpLabel getOpLabel () const { return opLabel; }
inline InstrTreeNode *leftChild () const { return LeftChild; }
inline InstrTreeNode *parent () const { return Parent; }
// If right child is a list node, recursively get its *left* child
inline InstrTreeNode* rightChild() const {
return (!RightChild ? 0 :
- (RightChild->getOpLabel() == VRegListOp
- ? RightChild->LeftChild : RightChild));
+ (RightChild->getOpLabel() == VRegListOp
+ ? RightChild->LeftChild : RightChild));
}
void dump(int dumpChildren, int indent) const;
protected:
class GetElementPtrInst;
enum SparcV9InstrSchedClass {
- SPARC_NONE, /* Instructions with no scheduling restrictions */
- SPARC_IEUN, /* Integer class that can use IEU0 or IEU1 */
- SPARC_IEU0, /* Integer class IEU0 */
- SPARC_IEU1, /* Integer class IEU1 */
- SPARC_FPM, /* FP Multiply or Divide instructions */
- SPARC_FPA, /* All other FP instructions */
- SPARC_CTI, /* Control-transfer instructions */
- SPARC_LD, /* Load instructions */
- SPARC_ST, /* Store instructions */
- SPARC_SINGLE, /* Instructions that must issue by themselves */
-
- SPARC_INV, /* This should stay at the end for the next value */
+ SPARC_NONE, /* Instructions with no scheduling restrictions */
+ SPARC_IEUN, /* Integer class that can use IEU0 or IEU1 */
+ SPARC_IEU0, /* Integer class IEU0 */
+ SPARC_IEU1, /* Integer class IEU1 */
+ SPARC_FPM, /* FP Multiply or Divide instructions */
+ SPARC_FPA, /* All other FP instructions */
+ SPARC_CTI, /* Control-transfer instructions */
+ SPARC_LD, /* Load instructions */
+ SPARC_ST, /* Store instructions */
+ SPARC_SINGLE, /* Instructions that must issue by themselves */
+
+ SPARC_INV, /* This should stay at the end for the next value */
SPARC_NUM_SCHED_CLASSES = SPARC_INV
};
// End-of-array marker
INVALID_OPCODE,
- NUM_REAL_OPCODES = PHI, // number of valid opcodes
+ NUM_REAL_OPCODES = PHI, // number of valid opcodes
NUM_TOTAL_OPCODES = INVALID_OPCODE
};
}
// Do this by creating a code sequence equivalent to:
// SETSW -(stackSize), %g1
int uregNum = TM.getRegInfo()->getUnifiedRegNum(
- TM.getRegInfo()->getRegClassIDOfType(Type::IntTy),
- SparcV9IntRegClass::g1);
+ TM.getRegInfo()->getRegClassIDOfType(Type::IntTy),
+ SparcV9IntRegClass::g1);
MachineInstr* M = BuildMI(V9::SETHI, 2).addSImm(C)
.addMReg(uregNum, MachineOperand::Def);
unsigned SugCol = LR->getSuggestedColor();
if (!IsColorUsedArr[SugCol]) {
if (LR->isSuggestedColorUsable()) {
- // if the suggested color is volatile, we should use it only if
- // there are no call interferences. Otherwise, it will get spilled.
- if (DEBUG_RA)
- std::cerr << "\n -Coloring with sug color: " << SugCol;
+ // if the suggested color is volatile, we should use it only if
+ // there are no call interferences. Otherwise, it will get spilled.
+ if (DEBUG_RA)
+ std::cerr << "\n -Coloring with sug color: " << SugCol;
- LR->setColor(LR->getSuggestedColor());
- return;
+ LR->setColor(LR->getSuggestedColor());
+ return;
} else if(DEBUG_RA) {
std::cerr << "\n Couldn't alloc Sug col - LR volatile & calls interf";
}
// If the LR is a double try to allocate f32 - f63
// If the above fails or LR is single precision
// If the LR does not interfere with a call
-// start allocating from f0
-// Else start allocating from f6
+// start allocating from f0
+// Else start allocating from f6
// If a color is still not found because LR interferes with a call
// Search in f0 - f6. If found mark for spill across calls.
// If a color is still not fond, mark for spilling
// color could be found.
// Now try to allocate even a volatile color
ColorFound = findFloatColor(LR, SparcV9FloatRegClass::StartOfAllRegs,
- SparcV9FloatRegClass::StartOfNonVolatileRegs,
- IsColorUsedArr);
+ SparcV9FloatRegClass::StartOfNonVolatileRegs,
+ IsColorUsedArr);
}
if (ColorFound >= 0) {
for (unsigned c = 0; c < NC; c+=2)
if (!IsColorUsedArr[c]) {
assert(!IsColorUsedArr[c+1] && "Incorrect used regs for FP double!");
- return c;
+ return c;
}
return -1;
}
if (!IsColorUsedArr[c]) {
assert(!IsColorUsedArr[c+1] &&
"Incorrect marking of used regs for SparcV9 FP double!");
- return c;
+ return c;
}
} else {
// find first unused color for a single
class SparcV9FloatRegClass : public TargetRegClassInfo {
int findFloatColor(const V9LiveRange *LR, unsigned Start,
- unsigned End,
+ unsigned End,
const std::vector<bool> &IsColorUsedArr) const;
public:
SparcV9FloatRegClass(unsigned ID)
getInvalidRegNum() : SparcV9FloatRegClass::f0 + (argNo * 2);
else
assert(0 && "Illegal FP register type");
- return 0;
+ return 0;
}
}
// We always suggest %i7 by convention.
//---------------------------------------------------------------------------
void SparcV9RegInfo::suggestReg4RetAddr(MachineInstr *RetMI,
- LiveRangeInfo& LRI) const {
+ LiveRangeInfo& LRI) const {
assert(target.getInstrInfo()->isReturn(RetMI->getOpcode()));
// done - it will be colored (or spilled) as a normal live range.
//---------------------------------------------------------------------------
void SparcV9RegInfo::suggestRegs4MethodArgs(const Function *Meth,
- LiveRangeInfo& LRI) const
+ LiveRangeInfo& LRI) const
{
// Check if this is a varArgs function. needed for choosing regs.
bool isVarArgs = isVarArgsFunction(Meth->getType());
// if LR received the correct color, nothing to do
//
if( UniLRReg == UniArgReg )
- continue;
+ continue;
// We are here because the LR did not receive the suggested
// but LR received another register.
// the UniLRReg register
//
if( isArgInReg ) {
- if( regClassIDOfArgReg != RegClassID ) {
- // NOTE: This code has not been well-tested.
+ if( regClassIDOfArgReg != RegClassID ) {
+ // NOTE: This code has not been well-tested.
- // It is a variable argument call: the float reg must go in a %o reg.
- // We have to move an int reg to a float reg via memory.
+ // It is a variable argument call: the float reg must go in a %o reg.
+ // We have to move an int reg to a float reg via memory.
//
assert(isVarArgs &&
RegClassID == FloatRegClassID &&
regClassIDOfArgReg == IntRegClassID &&
"This should only be an Int register for an FP argument");
- int TmpOff = MachineFunction::get(Meth).getInfo<SparcV9FunctionInfo>()->pushTempValue(
+ int TmpOff = MachineFunction::get(Meth).getInfo<SparcV9FunctionInfo>()->pushTempValue(
getSpilledRegSize(regType));
- cpReg2MemMI(InstrnsBefore,
+ cpReg2MemMI(InstrnsBefore,
UniArgReg, getFramePointer(), TmpOff, IntRegType);
- cpMem2RegMI(InstrnsBefore,
+ cpMem2RegMI(InstrnsBefore,
getFramePointer(), TmpOff, UniLRReg, regType);
- }
- else {
- cpReg2RegMI(InstrnsBefore, UniArgReg, UniLRReg, regType);
- }
+ }
+ else {
+ cpReg2RegMI(InstrnsBefore, UniArgReg, UniLRReg, regType);
+ }
}
else {
- // Now the arg is coming on stack. Since the LR received a register,
- // we just have to load the arg on stack into that register
- //
+ // Now the arg is coming on stack. Since the LR received a register,
+ // we just have to load the arg on stack into that register
+ //
const TargetFrameInfo& frameInfo = *target.getFrameInfo();
- int offsetFromFP =
+ int offsetFromFP =
frameInfo.getIncomingArgOffset(MachineFunction::get(Meth),
argNo);
offsetFromFP += slotSize - argSize;
}
- cpMem2RegMI(InstrnsBefore,
+ cpMem2RegMI(InstrnsBefore,
getFramePointer(), offsetFromFP, UniLRReg, regType);
}
if( isArgInReg ) {
- if( regClassIDOfArgReg != RegClassID ) {
+ if( regClassIDOfArgReg != RegClassID ) {
assert(0 &&
"FP arguments to a varargs function should be explicitly "
"copied to/from int registers by instruction selection!");
- // It must be a float arg for a variable argument call, which
+ // It must be a float arg for a variable argument call, which
// must come in a %o reg. Move the int reg to the stack.
//
assert(isVarArgs && regClassIDOfArgReg == IntRegClassID &&
else {
- // Now the arg is coming on stack. Since the LR did NOT
- // received a register as well, it is allocated a stack position. We
- // can simply change the stack position of the LR. We can do this,
- // since this method is called before any other method that makes
- // uses of the stack pos of the LR (e.g., updateMachineInstr)
+ // Now the arg is coming on stack. Since the LR did NOT
+ // received a register as well, it is allocated a stack position. We
+ // can simply change the stack position of the LR. We can do this,
+ // since this method is called before any other method that makes
+ // uses of the stack pos of the LR (e.g., updateMachineInstr)
//
const TargetFrameInfo& frameInfo = *target.getFrameInfo();
- int offsetFromFP =
+ int offsetFromFP =
frameInfo.getIncomingArgOffset(MachineFunction::get(Meth),
argNo);
offsetFromFP += slotSize - argSize;
}
- LR->modifySpillOffFromFP( offsetFromFP );
+ LR->modifySpillOffFromFP( offsetFromFP );
}
}
// outgoing call args and the return value of the call.
//---------------------------------------------------------------------------
void SparcV9RegInfo::suggestRegs4CallArgs(MachineInstr *CallMI,
- LiveRangeInfo& LRI) const {
+ LiveRangeInfo& LRI) const {
assert ( (target.getInstrInfo())->isCall(CallMI->getOpcode()) );
CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
int RegType) const {
assert( ((int)SrcReg != getInvalidRegNum()) &&
((int)DestReg != getInvalidRegNum()) &&
- "Invalid Register");
+ "Invalid Register");
MachineInstr * MI = NULL;
// To find the register class used for a specified Type
//
unsigned getRegClassIDOfType (const Type *type,
- bool isCCReg = false) const;
+ bool isCCReg = false) const;
// To find the register class to which a specified register belongs
//
LiveRangeInfo& LRI) const;
void suggestReg4RetValue(MachineInstr *RetI,
- LiveRangeInfo& LRI) const;
+ LiveRangeInfo& LRI) const;
void colorMethodArgs(const Function *Func,
LiveRangeInfo &LRI,
// as required. See SparcV9RegInfo.cpp for the implementation.
//
void suggestReg4RetAddr(MachineInstr *RetMI,
- LiveRangeInfo &LRI) const;
+ LiveRangeInfo &LRI) const;
void suggestReg4CallAddr(MachineInstr *CallMI, LiveRangeInfo &LRI) const;
-- Shift instructions cannot be grouped with other IEU0-specific instructions.
-- CC setting instructions cannot be grouped with other IEU1-specific instrs.
-- Several instructions must be issued in a single-instruction group:
- MOVcc or MOVr, MULs/x and DIVs/x, SAVE/RESTORE, many others
+ MOVcc or MOVr, MULs/x and DIVs/x, SAVE/RESTORE, many others
-- A CALL or JMPL breaks a group, ie, is not combined with subsequent instrs.
--
--
/*numEntries*/ 4,
/* V[] */ {
/*Cycle G */ { AllIssueSlots.rid, 0, 1 },
- { CTIIssueSlots.rid, 0, 1 },
+ { CTIIssueSlots.rid, 0, 1 },
/*Cycle E */ { IAlu0.rid, 1, 1 },
/*Cycles E-C */ { CTIDelayCycle.rid, 1, 2 }
/*Cycle C */
// opCode, isSingleIssue, breaksGroup, numBubbles
- // Special cases for single-issue only
- // Other single issue cases are below.
-//{ V9::LDDA, true, true, 0 },
-//{ V9::STDA, true, true, 0 },
-//{ V9::LDDF, true, true, 0 },
-//{ V9::LDDFA, true, true, 0 },
- { V9::ADDCr, true, true, 0 },
- { V9::ADDCi, true, true, 0 },
- { V9::ADDCccr, true, true, 0 },
- { V9::ADDCcci, true, true, 0 },
- { V9::SUBCr, true, true, 0 },
- { V9::SUBCi, true, true, 0 },
- { V9::SUBCccr, true, true, 0 },
- { V9::SUBCcci, true, true, 0 },
-//{ V9::LDSTUB, true, true, 0 },
-//{ V9::SWAP, true, true, 0 },
-//{ V9::SWAPA, true, true, 0 },
-//{ V9::CAS, true, true, 0 },
-//{ V9::CASA, true, true, 0 },
-//{ V9::CASX, true, true, 0 },
-//{ V9::CASXA, true, true, 0 },
-//{ V9::LDFSR, true, true, 0 },
-//{ V9::LDFSRA, true, true, 0 },
-//{ V9::LDXFSR, true, true, 0 },
-//{ V9::LDXFSRA, true, true, 0 },
-//{ V9::STFSR, true, true, 0 },
-//{ V9::STFSRA, true, true, 0 },
-//{ V9::STXFSR, true, true, 0 },
-//{ V9::STXFSRA, true, true, 0 },
-//{ V9::SAVED, true, true, 0 },
-//{ V9::RESTORED, true, true, 0 },
-//{ V9::FLUSH, true, true, 9 },
-//{ V9::FLUSHW, true, true, 9 },
-//{ V9::ALIGNADDR, true, true, 0 },
-//{ V9::DONE, true, true, 0 },
-//{ V9::RETRY, true, true, 0 },
-//{ V9::TCC, true, true, 0 },
-//{ V9::SHUTDOWN, true, true, 0 },
-
- // Special cases for breaking group *before*
- // CURRENTLY NOT SUPPORTED!
- { V9::CALL, false, false, 0 },
- { V9::JMPLCALLr, false, false, 0 },
- { V9::JMPLCALLi, false, false, 0 },
- { V9::JMPLRETr, false, false, 0 },
- { V9::JMPLRETi, false, false, 0 },
-
- // Special cases for breaking the group *after*
- { V9::MULXr, true, true, (4+34)/2 },
- { V9::MULXi, true, true, (4+34)/2 },
- { V9::FDIVS, false, true, 0 },
- { V9::FDIVD, false, true, 0 },
- { V9::FDIVQ, false, true, 0 },
- { V9::FSQRTS, false, true, 0 },
- { V9::FSQRTD, false, true, 0 },
- { V9::FSQRTQ, false, true, 0 },
+ // Special cases for single-issue only
+ // Other single issue cases are below.
+//{ V9::LDDA, true, true, 0 },
+//{ V9::STDA, true, true, 0 },
+//{ V9::LDDF, true, true, 0 },
+//{ V9::LDDFA, true, true, 0 },
+ { V9::ADDCr, true, true, 0 },
+ { V9::ADDCi, true, true, 0 },
+ { V9::ADDCccr, true, true, 0 },
+ { V9::ADDCcci, true, true, 0 },
+ { V9::SUBCr, true, true, 0 },
+ { V9::SUBCi, true, true, 0 },
+ { V9::SUBCccr, true, true, 0 },
+ { V9::SUBCcci, true, true, 0 },
+//{ V9::LDSTUB, true, true, 0 },
+//{ V9::SWAP, true, true, 0 },
+//{ V9::SWAPA, true, true, 0 },
+//{ V9::CAS, true, true, 0 },
+//{ V9::CASA, true, true, 0 },
+//{ V9::CASX, true, true, 0 },
+//{ V9::CASXA, true, true, 0 },
+//{ V9::LDFSR, true, true, 0 },
+//{ V9::LDFSRA, true, true, 0 },
+//{ V9::LDXFSR, true, true, 0 },
+//{ V9::LDXFSRA, true, true, 0 },
+//{ V9::STFSR, true, true, 0 },
+//{ V9::STFSRA, true, true, 0 },
+//{ V9::STXFSR, true, true, 0 },
+//{ V9::STXFSRA, true, true, 0 },
+//{ V9::SAVED, true, true, 0 },
+//{ V9::RESTORED, true, true, 0 },
+//{ V9::FLUSH, true, true, 9 },
+//{ V9::FLUSHW, true, true, 9 },
+//{ V9::ALIGNADDR, true, true, 0 },
+//{ V9::DONE, true, true, 0 },
+//{ V9::RETRY, true, true, 0 },
+//{ V9::TCC, true, true, 0 },
+//{ V9::SHUTDOWN, true, true, 0 },
+
+ // Special cases for breaking group *before*
+ // CURRENTLY NOT SUPPORTED!
+ { V9::CALL, false, false, 0 },
+ { V9::JMPLCALLr, false, false, 0 },
+ { V9::JMPLCALLi, false, false, 0 },
+ { V9::JMPLRETr, false, false, 0 },
+ { V9::JMPLRETi, false, false, 0 },
+
+ // Special cases for breaking the group *after*
+ { V9::MULXr, true, true, (4+34)/2 },
+ { V9::MULXi, true, true, (4+34)/2 },
+ { V9::FDIVS, false, true, 0 },
+ { V9::FDIVD, false, true, 0 },
+ { V9::FDIVQ, false, true, 0 },
+ { V9::FSQRTS, false, true, 0 },
+ { V9::FSQRTD, false, true, 0 },
+ { V9::FSQRTQ, false, true, 0 },
//{ V9::FCMP{LE,GT,NE,EQ}, false, true, 0 },
- // Instructions that introduce bubbles
-//{ V9::MULScc, true, true, 2 },
-//{ V9::SMULcc, true, true, (4+18)/2 },
-//{ V9::UMULcc, true, true, (4+19)/2 },
- { V9::SDIVXr, true, true, 68 },
- { V9::SDIVXi, true, true, 68 },
- { V9::UDIVXr, true, true, 68 },
- { V9::UDIVXi, true, true, 68 },
-//{ V9::SDIVcc, true, true, 36 },
-//{ V9::UDIVcc, true, true, 37 },
- { V9::WRCCRr, true, true, 4 },
- { V9::WRCCRi, true, true, 4 },
-//{ V9::WRPR, true, true, 4 },
-//{ V9::RDCCR, true, true, 0 }, // no bubbles after, but see below
-//{ V9::RDPR, true, true, 0 },
+ // Instructions that introduce bubbles
+//{ V9::MULScc, true, true, 2 },
+//{ V9::SMULcc, true, true, (4+18)/2 },
+//{ V9::UMULcc, true, true, (4+19)/2 },
+ { V9::SDIVXr, true, true, 68 },
+ { V9::SDIVXi, true, true, 68 },
+ { V9::UDIVXr, true, true, 68 },
+ { V9::UDIVXi, true, true, 68 },
+//{ V9::SDIVcc, true, true, 36 },
+//{ V9::UDIVcc, true, true, 37 },
+ { V9::WRCCRr, true, true, 4 },
+ { V9::WRCCRi, true, true, 4 },
+//{ V9::WRPR, true, true, 4 },
+//{ V9::RDCCR, true, true, 0 }, // no bubbles after, but see below
+//{ V9::RDPR, true, true, 0 },
};
SparcV9SchedInfo::SparcV9SchedInfo(const TargetMachine& tgt)
: TargetSchedInfo(tgt,
(unsigned int) SPARC_NUM_SCHED_CLASSES,
- SparcV9RUsageDesc,
- SparcV9InstrUsageDeltas,
- SparcV9InstrIssueDeltas,
- sizeof(SparcV9InstrUsageDeltas)/sizeof(InstrRUsageDelta),
- sizeof(SparcV9InstrIssueDeltas)/sizeof(InstrIssueDelta))
+ SparcV9RUsageDesc,
+ SparcV9InstrUsageDeltas,
+ SparcV9InstrIssueDeltas,
+ sizeof(SparcV9InstrUsageDeltas)/sizeof(InstrRUsageDelta),
+ sizeof(SparcV9InstrIssueDeltas)/sizeof(InstrIssueDelta))
{
maxNumIssueTotal = 4;
- longestIssueConflict = 0; // computed from issuesGaps[]
+ longestIssueConflict = 0; // computed from issuesGaps[]
// must be called after above parameters are initialized.
initializeResources();
cl::desc("Emit LLVM-to-MachineCode mapping info to assembly"));
cl::opt<bool> EnableModSched("enable-modsched",
- cl::desc("Enable modulo scheduling pass"), cl::Hidden);
+ cl::desc("Enable modulo scheduling pass"), cl::Hidden);
cl::opt<bool> EnableSBModSched("enable-modschedSB",
- cl::desc("Enable superblock modulo scheduling (experimental)"), cl::Hidden);
+ cl::desc("Enable superblock modulo scheduling (experimental)"), cl::Hidden);
// Register the target.
RegisterTarget<SparcV9TargetMachine> X("sparcv9", " SPARC V9");
//
// Methods of class for temporary intermediate values used within the current
// SparcV9 backend.
-//
+//
//===----------------------------------------------------------------------===//
#include "SparcV9TmpInstr.h"
DA = 5 << Op0Shift, DB = 6 << Op0Shift,
DC = 7 << Op0Shift, DD = 8 << Op0Shift,
DE = 9 << Op0Shift, DF = 10 << Op0Shift,
-
+
// XS, XD - These prefix codes are for single and double precision scalar
// floating point operations performed in the SSE registers.
XD = 11 << Op0Shift, XS = 12 << Op0Shift,
/// stackAlignment - The minimum alignment known to hold of the stack frame on
/// entry to the function and which must be maintained by every function.
unsigned stackAlignment;
-
+
/// Used by instruction selector
bool indirectExternAndWeakGlobals;
-
+
/// Used by the asm printer
bool asmDarwinLinkerStubs;
bool asmLeadingUnderscore;
bool asmPrintDotLCommConstants;
bool asmPrintConstantAlignment;
public:
- /// This constructor initializes the data members to match that
+ /// This constructor initializes the data members to match that
/// of the specified module.
///
X86Subtarget(const Module &M);
/// stack frame on entry to the function and which must be maintained by every
/// function for this subtarget.
unsigned getStackAlignment() const { return stackAlignment; }
-
+
/// Returns true if the instruction selector should treat global values
- /// referencing external or weak symbols as indirect rather than direct
+ /// referencing external or weak symbols as indirect rather than direct
/// references.
bool getIndirectExternAndWeakGlobals() const {
return indirectExternAndWeakGlobals;
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