The order in which the predicate is added differs between Thumb and ARM mode. Fix...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144494 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMFastISel.cpp b/lib/Target/ARM/ARMFastISel.cpp
index f3e6fc7781b27cea3bb0f0be6657657b846caa7e..d330367125565955f70e67aa93e4c716adcd21b3 100644 (file)
--- a/lib/Target/ARM/ARMFastISel.cpp
+++ b/lib/Target/ARM/ARMFastISel.cpp
@@ -2108,18 +2108,25 @@ bool ARMFastISel::SelectCall(const Instruction *I,
   MachineInstrBuilder MIB;
   unsigned CallOpc = ARMSelectCallOp(GV);
   // Explicitly adding the predicate here.
-  if(isThumb2)
-    // Explicitly adding the predicate here.
-    MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
-                                 TII.get(CallOpc)));
-  else
+  if(isThumb2) {
     // Explicitly adding the predicate here.
     MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
                                  TII.get(CallOpc)));
-  if (!IntrMemName)
-    MIB.addGlobalAddress(GV, 0, 0);
-  else 
-    MIB.addExternalSymbol(IntrMemName, 0);
+    if (!IntrMemName)
+      MIB.addGlobalAddress(GV, 0, 0);
+    else 
+      MIB.addExternalSymbol(IntrMemName, 0);
+  } else {
+    if (!IntrMemName)
+      // Explicitly adding the predicate here.
+      MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
+                                   TII.get(CallOpc))
+            .addGlobalAddress(GV, 0, 0));
+    else
+      MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
+                                   TII.get(CallOpc))
+            .addExternalSymbol(IntrMemName, 0));
+  }
   
   // Add implicit physical register uses to the call.
   for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
@@ -2136,7 +2143,6 @@ bool ARMFastISel::SelectCall(const Instruction *I,
 }
 
 bool ARMFastISel::SelectIntrinsicCall(const IntrinsicInst &I) {
-  if (!isThumb2) return false;
   // FIXME: Handle more intrinsics.
   switch (I.getIntrinsicID()) {
   default: return false;

diff --git a/test/CodeGen/ARM/fast-isel-intrinsic.ll b/test/CodeGen/ARM/fast-isel-intrinsic.ll
index f96b5ad3078a59b2ab2277f17dd6595543bc0d8d..9a924b491b63ccb4035dd3e9165761bf3786589d 100644 (file)
--- a/test/CodeGen/ARM/fast-isel-intrinsic.ll
+++ b/test/CodeGen/ARM/fast-isel-intrinsic.ll
@@ -1,3 +1,4 @@
+; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM
 ; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB
 
 @message1 = global [60 x i8] c"The LLVM Compiler Infrastructure\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00", align 1
@@ -10,7 +11,7 @@ define void @t1() nounwind ssp {
 ; ARM: movw r1, #64
 ; ARM: movw r2, #10
 ; ARM: uxtb r1, r1
-; ARM: bl #14
+; ARM: bl _memset
 ; THUMB: t1
 ; THUMB: ldr.n r0, LCPI0_0
 ; THUMB: adds r0, #5
@@ -36,7 +37,7 @@ define void @t2() nounwind ssp {
 ; ARM: str r0, [sp]                @ 4-byte Spill
 ; ARM: mov r0, r1
 ; ARM: ldr r1, [sp]                @ 4-byte Reload
-; ARM: bl #14
+; ARM: bl _memcpy
 ; THUMB: t2
 ; THUMB: ldr.n r0, LCPI1_0
 ; THUMB: ldr r0, [r0]
@@ -60,7 +61,7 @@ define void @t3() nounwind ssp {
 ; ARM: add r0, r0, #16
 ; ARM: movw r2, #10
 ; ARM: mov r0, r1
-; ARM: bl #14
+; ARM: bl _memmove
 ; THUMB: t3
 ; THUMB: ldr.n r0, LCPI2_0
 ; THUMB: ldr r0, [r0]