Generate branch machine instructions with MachineBasicBlock operands instead of

LLVM BasicBlock operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13566 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/InstSelectSimple.cpp b/lib/Target/X86/InstSelectSimple.cpp
index e0e641e1ac9fcc85e8a76182fbf0c3308d5011bf..f9d5387532061e46225fd190e5006ab0d993dc20 100644 (file)
--- a/lib/Target/X86/InstSelectSimple.cpp
+++ b/lib/Target/X86/InstSelectSimple.cpp
@@ -1379,7 +1379,7 @@ void ISel::visitBranchInst(BranchInst &BI) {
 
   if (!BI.isConditional()) {  // Unconditional branch?
     if (BI.getSuccessor(0) != NextBB)
-      BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
+      BuildMI(BB, X86::JMP, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
     return;
   }
 
@@ -1392,12 +1392,12 @@ void ISel::visitBranchInst(BranchInst &BI) {
     BuildMI(BB, X86::TEST8rr, 2).addReg(condReg).addReg(condReg);
     if (BI.getSuccessor(1) == NextBB) {
       if (BI.getSuccessor(0) != NextBB)
-        BuildMI(BB, X86::JNE, 1).addPCDisp(BI.getSuccessor(0));
+        BuildMI(BB, X86::JNE, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
     } else {
-      BuildMI(BB, X86::JE, 1).addPCDisp(BI.getSuccessor(1));
+      BuildMI(BB, X86::JE, 1).addMBB(MBBMap[BI.getSuccessor(1)]);
       
       if (BI.getSuccessor(0) != NextBB)
-        BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
+        BuildMI(BB, X86::JMP, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
     }
     return;
   }
@@ -1429,14 +1429,16 @@ void ISel::visitBranchInst(BranchInst &BI) {
   };
   
   if (BI.getSuccessor(0) != NextBB) {
-    BuildMI(BB, OpcodeTab[isSigned][OpNum], 1).addPCDisp(BI.getSuccessor(0));
+    BuildMI(BB, OpcodeTab[isSigned][OpNum], 1)
+      .addMBB(MBBMap[BI.getSuccessor(0)]);
     if (BI.getSuccessor(1) != NextBB)
-      BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(1));
+      BuildMI(BB, X86::JMP, 1).addMBB(MBBMap[BI.getSuccessor(1)]);
   } else {
     // Change to the inverse condition...
     if (BI.getSuccessor(1) != NextBB) {
       OpNum ^= 1;
-      BuildMI(BB, OpcodeTab[isSigned][OpNum], 1).addPCDisp(BI.getSuccessor(1));
+      BuildMI(BB, OpcodeTab[isSigned][OpNum], 1)
+        .addMBB(MBBMap[BI.getSuccessor(1)]);
     }
   }
 }

diff --git a/lib/Target/X86/X86ISelSimple.cpp b/lib/Target/X86/X86ISelSimple.cpp
index e0e641e1ac9fcc85e8a76182fbf0c3308d5011bf..f9d5387532061e46225fd190e5006ab0d993dc20 100644 (file)
--- a/lib/Target/X86/X86ISelSimple.cpp
+++ b/lib/Target/X86/X86ISelSimple.cpp
@@ -1379,7 +1379,7 @@ void ISel::visitBranchInst(BranchInst &BI) {
 
   if (!BI.isConditional()) {  // Unconditional branch?
     if (BI.getSuccessor(0) != NextBB)
-      BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
+      BuildMI(BB, X86::JMP, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
     return;
   }
 
@@ -1392,12 +1392,12 @@ void ISel::visitBranchInst(BranchInst &BI) {
     BuildMI(BB, X86::TEST8rr, 2).addReg(condReg).addReg(condReg);
     if (BI.getSuccessor(1) == NextBB) {
       if (BI.getSuccessor(0) != NextBB)
-        BuildMI(BB, X86::JNE, 1).addPCDisp(BI.getSuccessor(0));
+        BuildMI(BB, X86::JNE, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
     } else {
-      BuildMI(BB, X86::JE, 1).addPCDisp(BI.getSuccessor(1));
+      BuildMI(BB, X86::JE, 1).addMBB(MBBMap[BI.getSuccessor(1)]);
       
       if (BI.getSuccessor(0) != NextBB)
-        BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
+        BuildMI(BB, X86::JMP, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
     }
     return;
   }
@@ -1429,14 +1429,16 @@ void ISel::visitBranchInst(BranchInst &BI) {
   };
   
   if (BI.getSuccessor(0) != NextBB) {
-    BuildMI(BB, OpcodeTab[isSigned][OpNum], 1).addPCDisp(BI.getSuccessor(0));
+    BuildMI(BB, OpcodeTab[isSigned][OpNum], 1)
+      .addMBB(MBBMap[BI.getSuccessor(0)]);
     if (BI.getSuccessor(1) != NextBB)
-      BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(1));
+      BuildMI(BB, X86::JMP, 1).addMBB(MBBMap[BI.getSuccessor(1)]);
   } else {
     // Change to the inverse condition...
     if (BI.getSuccessor(1) != NextBB) {
       OpNum ^= 1;
-      BuildMI(BB, OpcodeTab[isSigned][OpNum], 1).addPCDisp(BI.getSuccessor(1));
+      BuildMI(BB, OpcodeTab[isSigned][OpNum], 1)
+        .addMBB(MBBMap[BI.getSuccessor(1)]);
     }
   }
 }