* 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc: (21 commits)
[POWERPC] spusched: Fix initial timeslice calculation
[POWERPC] spufs: Fix incorrect initialization of cbe_spu_info.spus
[POWERPC] Fix Maple platform ISA bus
[POWERPC] Make pci_iounmap actually unmap things
[POWERPC] Add function to check if address is an IO port
[POWERPC] Fix Pegasos keyboard detection
[POWERPC] iSeries: Fix section mismatch warning in lpevents
[POWERPC] iSeries: Fix section mismatch warnings
[POWERPC] iSeries: We need vio_enable_interrupts
[POWERPC] Fix RTC and device tree on linkstation machines
[POWERPC] Add of_register_i2c_devices()
[POWERPC] Fix loop with unsigned long counter variable
[POWERPC] Fix register labels on show_regs() message for 4xx/Book-E
[POWERPC] Only allow building of BootX text support on PPC_MULTIPLATFORM
[POWERPC] Fix the ability to reset on MPC8544 DS and MPC8568 MDS boards
[POWERPC] Fix mpc7448hpc2 tsi108 device_type bug
[POWREPC] Fixup a number of modpost warnings on ppc32
[POWERPC] Fix ethernet PHY support on MPC8544 DS
[POWERPC] Don't try to allocate resources for a Freescale POWERPC PHB
Revert "[POWERPC] Don't complain if size-cells == 0 in prom_parse()"
...
config BOOTX_TEXT
bool "Support for early boot text console (BootX or OpenFirmware only)"
- depends PPC_OF
+ depends PPC_OF && PPC_MULTIPLATFORM
help
Say Y here to see progress messages from the boot firmware in text
mode. Requires either BootX or Open Firmware.
PowerPC,603e { /* Really 8241 */
device_type = "cpu";
reg = <0>;
- clock-frequency = <bebc200>; /* Fixed by bootwrapper */
- timebase-frequency = <1743000>; /* Fixed by bootwrapper */
- bus-frequency = <0>; /* From bootloader */
+ clock-frequency = <bebc200>; /* Fixed by bootloader */
+ timebase-frequency = <1743000>; /* Fixed by bootloader */
+ bus-frequency = <0>; /* Fixed by bootloader */
/* Following required by dtc but not used */
- i-cache-line-size = <0>;
- d-cache-line-size = <0>;
i-cache-size = <4000>;
d-cache-size = <4000>;
};
fef00000 fef00000 00100000>; /* pci iack */
i2c@80003000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
device_type = "i2c";
compatible = "fsl-i2c";
reg = <80003000 1000>;
interrupts = <5 2>;
interrupt-parent = <&mpic>;
+
+ rtc@32 {
+ device_type = "rtc";
+ compatible = "ricoh,rs5c372b";
+ reg = <32>;
+ };
};
serial@80004500 {
interrupt-parent = <&mpic>;
};
- mpic: pic@80040000 {
+ mpic: interrupt-controller@80040000 {
#interrupt-cells = <2>;
#address-cells = <0>;
device_type = "open-pic";
PowerPC,603e { /* Really 8241 */
device_type = "cpu";
reg = <0>;
- clock-frequency = <fdad680>; /* Fixed by bootwrapper */
- timebase-frequency = <1F04000>; /* Fixed by bootwrapper */
- bus-frequency = <0>; /* From bootloader */
+ clock-frequency = <fdad680>; /* Fixed by bootloader */
+ timebase-frequency = <1F04000>; /* Fixed by bootloader */
+ bus-frequency = <0>; /* Fixed by bootloader */
/* Following required by dtc but not used */
- i-cache-line-size = <0>;
- d-cache-line-size = <0>;
i-cache-size = <4000>;
d-cache-size = <4000>;
};
fef00000 fef00000 00100000>; /* pci iack */
i2c@80003000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
device_type = "i2c";
compatible = "fsl-i2c";
reg = <80003000 1000>;
interrupts = <5 2>;
interrupt-parent = <&mpic>;
+
+ rtc@32 {
+ device_type = "rtc";
+ compatible = "ricoh,rs5c372b";
+ reg = <32>;
+ };
};
serial@80004500 {
interrupt-parent = <&mpic>;
};
- mpic: pic@80040000 {
- interrupt-parent = <&mpic>;
+ mpic: interrupt-controller@80040000 {
#interrupt-cells = <2>;
#address-cells = <0>;
device_type = "open-pic";
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
- device_type = "tsi108-bridge";
+ device_type = "tsi-bridge";
ranges = <00000000 c0000000 00010000>;
reg = <c0000000 00010000>;
bus-frequency = <0>;
interrupts = <1d 2 1e 2 22 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy0>;
+ phy-connection-type = "rgmii-id";
};
ethernet@26000 {
interrupts = <1f 2 20 2 21 2>;
interrupt-parent = <&mpic>;
phy-handle = <&phy1>;
+ phy-connection-type = "rgmii-id";
};
serial@4500 {
};
+ global-utilities@e0000 { //global utilities block
+ compatible = "fsl,mpc8548-guts";
+ reg = <e0000 1000>;
+ fsl,has-rstcr;
+ };
+
mpic: pic@40000 {
clock-frequency = <0>;
interrupt-controller;
interrupt-parent = <&mpic>;
};
+ global-utilities@e0000 { //global utilities block
+ compatible = "fsl,mpc8548-guts";
+ reg = <e0000 1000>;
+ fsl,has-rstcr;
+ };
+
pci@8000 {
interrupt-map-mask = <f800 0 0 7>;
interrupt-map = <
mtmsrd r24 /* RI on */
lhz r24,PACAPACAINDEX(r13) /* Get processor # */
cmpwi 0,r24,0 /* Are we processor 0? */
- beq .__start_initialization_iSeries /* Start up the first processor */
- mfspr r4,SPRN_CTRLF
+ bne 1f
+ b .__start_initialization_iSeries /* Start up the first processor */
+1: mfspr r4,SPRN_CTRLF
li r5,CTRL_RUNLATCH /* Turn off the run light */
andc r4,r4,r5
mtspr SPRN_CTRLT,r4
#endif
#ifdef CONFIG_PPC_ISERIES
-_STATIC(__start_initialization_iSeries)
+_INIT_STATIC(__start_initialization_iSeries)
/* Clear out the BSS */
LOAD_REG_IMMEDIATE(r11,__bss_stop)
LOAD_REG_IMMEDIATE(r8,__bss_start)
#include <linux/pci.h>
#include <linux/mm.h>
#include <asm/io.h>
+#include <asm/pci-bridge.h>
/*
* Here comes the ppc64 implementation of the IOMAP
void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
{
- /* Nothing to do */
+ if (isa_vaddr_is_ioport(addr))
+ return;
+ if (pcibios_vaddr_is_ioport(addr))
+ return;
+ iounmap(addr);
}
+
EXPORT_SYMBOL(pci_iomap);
EXPORT_SYMBOL(pci_iounmap);
}
EXPORT_SYMBOL_GPL(virq_to_hw);
-struct irq_host *irq_alloc_host(unsigned int revmap_type,
- unsigned int revmap_arg,
- struct irq_host_ops *ops,
- irq_hw_number_t inval_irq)
+__init_refok struct irq_host *irq_alloc_host(unsigned int revmap_type,
+ unsigned int revmap_arg,
+ struct irq_host_ops *ops,
+ irq_hw_number_t inval_irq)
{
struct irq_host *host;
unsigned int size = sizeof(struct irq_host);
spin_unlock(&hose_spinlock);
}
-struct pci_controller * pcibios_alloc_controller(struct device_node *dev)
+__init_refok struct pci_controller * pcibios_alloc_controller(struct device_node *dev)
{
struct pci_controller *phb;
kfree(phb);
}
+int pcibios_vaddr_is_ioport(void __iomem *address)
+{
+ int ret = 0;
+ struct pci_controller *hose;
+ unsigned long size;
+
+ spin_lock(&hose_spinlock);
+ list_for_each_entry(hose, &hose_list, list_node) {
+#ifdef CONFIG_PPC64
+ size = hose->pci_io_size;
+#else
+ size = hose->io_resource.end - hose->io_resource.start + 1;
+#endif
+ if (address >= hose->io_base_virt &&
+ address < (hose->io_base_virt + size)) {
+ ret = 1;
+ break;
+ }
+ }
+ spin_unlock(&hose_spinlock);
+ return ret;
+}
+
/*
* Return the domain number for this bus.
*/
static int pci_bus_count;
+static void
+fixup_hide_host_resource_fsl(struct pci_dev* dev)
+{
+ int i, class = dev->class >> 8;
+
+ if ((class == PCI_CLASS_PROCESSOR_POWERPC) &&
+ (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) &&
+ (dev->bus->parent == NULL)) {
+ for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
+ dev->resource[i].start = 0;
+ dev->resource[i].end = 0;
+ dev->resource[i].flags = 0;
+ }
+ }
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl);
+
static void
fixup_broken_pcnet32(struct pci_dev* dev)
{
subsys_initcall(pcibios_init);
-void __init pcibios_fixup_bus(struct pci_bus *bus)
+void pcibios_fixup_bus(struct pci_bus *bus)
{
struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
unsigned long io_offset;
printk(" CR: %08lx XER: %08lx\n", regs->ccr, regs->xer);
trap = TRAP(regs);
if (trap == 0x300 || trap == 0x600)
+#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
+ printk("DEAR: "REG", ESR: "REG"\n", regs->dar, regs->dsisr);
+#else
printk("DAR: "REG", DSISR: "REG"\n", regs->dar, regs->dsisr);
+#endif
printk("TASK = %p[%d] '%s' THREAD: %p",
current, current->pid, current->comm, task_thread_info(current));
/* Max address size we deal with */
#define OF_MAX_ADDR_CELLS 4
#define OF_CHECK_COUNTS(na, ns) ((na) > 0 && (na) <= OF_MAX_ADDR_CELLS && \
- (ns) >= 0)
+ (ns) > 0)
static struct of_bus *of_match_bus(struct device_node *np);
static int __of_address_to_resource(struct device_node *dev,
break;
}
np = of_find_node_by_type(NULL, "8042");
+ /* Pegasos has no device_type on its 8042 node, look for the
+ * name instead */
+ if (!np)
+ np = of_find_node_by_name(NULL, "8042");
break;
case FDC_BASE: /* FDC1 */
np = of_find_node_by_type(NULL, "fdc");
* Called by setup_system after ppc_md->probe and ppc_md->early_init.
* Call it again after setting udbg_putc in ppc_md->setup_arch.
*/
-void register_early_udbg_console(void)
+void __init register_early_udbg_console(void)
{
if (early_console_initialized)
return;
static long __init lmb_add_region(struct lmb_region *rgn, unsigned long base,
unsigned long size)
{
- unsigned long i, coalesced = 0;
- long adjacent;
+ unsigned long coalesced = 0;
+ long adjacent, i;
/* First try and coalesce this LMB with another. */
for (i=0; i < rgn->cnt; i++) {
INIT_LIST_HEAD(&ctx->aff_list);
if (gang)
spu_gang_add_ctx(gang, ctx);
- ctx->cpus_allowed = current->cpus_allowed;
+
+ __spu_update_sched_info(ctx);
spu_set_timeslice(ctx);
ctx->stats.util_state = SPU_UTIL_IDLE_LOADED;
spu_acquire(ctx);
if (ctx->state == SPU_STATE_SAVED) {
__spu_update_sched_info(ctx);
+ spu_set_timeslice(ctx);
ret = spu_activate(ctx, 0);
if (ret) {
/*
* We have to update the scheduling priority under active_mutex
* to protect against find_victim().
+ *
+ * No need to update the timeslice ASAP, it will get updated
+ * once the current one has expired.
*/
spu_update_sched_info(ctx);
}
INIT_LIST_HEAD(&spu_prio->runq[i]);
__clear_bit(i, spu_prio->bitmap);
}
- for (i = 0; i < MAX_NUMNODES; i++) {
- mutex_init(&cbe_spu_info[i].list_mutex);
- INIT_LIST_HEAD(&cbe_spu_info[i].spus);
- }
spin_lock_init(&spu_prio->runq_lock);
setup_timer(&spusched_timer, spusched_wake, 0);
}
__setup("spread_lpevents=", set_spread_lpevents);
-void setup_hvlpevent_queue(void)
+void __init setup_hvlpevent_queue(void)
{
void *eventStack;
/* Fixup "bus-range" OF property */
fixup_bus_range(dev);
+ /* Check for legacy IOs */
+ isa_bridge_find_early(hose);
+
return 0;
}
}
}
-static void __devinit quirk_fsl_pcie_transparent(struct pci_dev *dev)
+static void __init quirk_fsl_pcie_transparent(struct pci_dev *dev)
{
struct resource *res;
int i, res_idx = PCI_BRIDGE_RESOURCES;
/* check PCI express link status */
if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
- hose->indirect_type = PPC_INDIRECT_TYPE_EXT_REG |
+ hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG |
PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
if (fsl_pcie_check_link(hose))
hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
arch_initcall(gfar_of_init);
+#ifdef CONFIG_I2C_BOARDINFO
+#include <linux/i2c.h>
+struct i2c_driver_device {
+ char *of_device;
+ char *i2c_driver;
+ char *i2c_type;
+};
+
+static struct i2c_driver_device i2c_devices[] __initdata = {
+ {"ricoh,rs5c372a", "rtc-rs5c372", "rs5c372a",},
+ {"ricoh,rs5c372b", "rtc-rs5c372", "rs5c372b",},
+ {"ricoh,rv5c386", "rtc-rs5c372", "rv5c386",},
+ {"ricoh,rv5c387a", "rtc-rs5c372", "rv5c387a",},
+};
+
+static int __init of_find_i2c_driver(struct device_node *node, struct i2c_board_info *info)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(i2c_devices); i++) {
+ if (!of_device_is_compatible(node, i2c_devices[i].of_device))
+ continue;
+ strncpy(info->driver_name, i2c_devices[i].i2c_driver, KOBJ_NAME_LEN);
+ strncpy(info->type, i2c_devices[i].i2c_type, I2C_NAME_SIZE);
+ return 0;
+ }
+ return -ENODEV;
+}
+
+static void __init of_register_i2c_devices(struct device_node *adap_node, int bus_num)
+{
+ struct device_node *node = NULL;
+
+ while ((node = of_get_next_child(adap_node, node))) {
+ struct i2c_board_info info;
+ const u32 *addr;
+ int len;
+
+ addr = of_get_property(node, "reg", &len);
+ if (!addr || len < sizeof(int) || *addr > (1 << 10) - 1) {
+ printk(KERN_WARNING "fsl_ioc.c: invalid i2c device entry\n");
+ continue;
+ }
+
+ info.irq = irq_of_parse_and_map(node, 0);
+ if (info.irq == NO_IRQ)
+ info.irq = -1;
+
+ if (of_find_i2c_driver(node, &info) < 0)
+ continue;
+
+ info.platform_data = NULL;
+ info.addr = *addr;
+
+ i2c_register_board_info(bus_num, &info, 1);
+ }
+}
+
static int __init fsl_i2c_of_init(void)
{
struct device_node *np;
fsl_i2c_platform_data));
if (ret)
goto unreg;
+
+ of_register_i2c_devices(np, i);
}
return 0;
}
arch_initcall(fsl_i2c_of_init);
+#endif
#ifdef CONFIG_PPC_83xx
static int __init mpc83xx_wdt_init(void)
mbase = ioremap(cfg_data & PAGE_MASK, PAGE_SIZE);
hose->cfg_data = mbase + (cfg_data & ~PAGE_MASK);
hose->ops = &indirect_pci_ops;
+ hose->indirect_type = flags;
}
return bus->sysdata;
}
+static inline int isa_vaddr_is_ioport(void __iomem *address)
+{
+ /* No specific ISA handling on ppc32 at this stage, it
+ * all goes through PCI
+ */
+ return 0;
+}
+
/* These are used for config access before all the PCI probing
has been done. */
int early_read_config_byte(struct pci_controller *hose, int bus, int dev_fn,
extern void isa_bridge_find_early(struct pci_controller *hose);
+static inline int isa_vaddr_is_ioport(void __iomem *address)
+{
+ /* Check if address hits the reserved legacy IO range */
+ unsigned long ea = (unsigned long)address;
+ return ea >= ISA_IO_BASE && ea < ISA_IO_END;
+}
+
extern int pcibios_unmap_io_space(struct pci_bus *bus);
extern int pcibios_map_io_space(struct pci_bus *bus);
pcibios_alloc_controller(struct device_node *dev);
#ifdef CONFIG_PCI
extern unsigned long pci_address_to_pio(phys_addr_t address);
+extern int pcibios_vaddr_is_ioport(void __iomem *address);
#else
static inline unsigned long pci_address_to_pio(phys_addr_t address)
{
return (unsigned long)-1;
}
+static inline int pcibios_vaddr_is_ioport(void __iomem *address)
+{
+ return 0;
+}
#endif
.type GLUE(.,name),@function; \
GLUE(.,name):
+#define _INIT_STATIC(name) \
+ .section ".text.init.refok"; \
+ .align 2 ; \
+ .section ".opd","aw"; \
+name: \
+ .quad GLUE(.,name); \
+ .quad .TOC.@tocbase; \
+ .quad 0; \
+ .previous; \
+ .type GLUE(.,name),@function; \
+GLUE(.,name):
+
#else /* 32-bit */
#define _GLOBAL(n) \
extern struct vio_dev *vio_find_node(struct device_node *vnode);
extern int vio_enable_interrupts(struct vio_dev *dev);
extern int vio_disable_interrupts(struct vio_dev *dev);
+#else
+static inline int vio_enable_interrupts(struct vio_dev *dev)
+{
+ return 0;
+}
#endif
static inline struct vio_driver *to_vio_driver(struct device_driver *drv)
projects / firefly-linux-kernel-4.4.55.git / commitdiff