Fix a typo in a comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46513 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index 5d6b1a27ad53b083a58c5648fbb6e2cfaecec4a2..48bc3cd115b56692033b99ea35ba844d1c7f8781 100644 (file)
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -1386,7 +1386,7 @@ void BURegReductionPriorityQueue<SF>::AddPseudoTwoAddrDeps() {
           if (!SuccSU->Node || !SuccSU->Node->isTargetOpcode())
             continue;
           // Don't constrain nodes with physical register defs if the
-          // predecessor can cloober them.
+          // predecessor can clobber them.
           if (SuccSU->hasPhysRegDefs) {
             if (canClobberPhysRegDefs(SuccSU, SU, TII, MRI))
               continue;