Try trivial remat before the coalescer gives up on a vr / physreg coalescing for...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99575 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SimpleRegisterCoalescing.cpp b/lib/CodeGen/SimpleRegisterCoalescing.cpp
index f51bedd3347f571bd6a9e75586e748b328a12ea5..15ca3740b8f2e73a9bee714fc34f0f56cdbd3ae4 100644 (file)
--- a/lib/CodeGen/SimpleRegisterCoalescing.cpp
+++ b/lib/CodeGen/SimpleRegisterCoalescing.cpp
@@ -1664,7 +1664,8 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
       if (JoinPInt.ranges.size() > 1000) {
         mri_->setRegAllocationHint(JoinVInt.reg, 0, JoinPReg);
         ++numAborts;
-        DEBUG(dbgs() << "\tPhysical register too complicated, abort!\n");
+        DEBUG(dbgs()
+              << "\tPhysical register live interval too complicated, abort!\n");
         return false;
       }
 
@@ -1675,6 +1676,11 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
       if (Length > Threshold &&
           (((float)std::distance(mri_->use_nodbg_begin(JoinVReg),
                                  mri_->use_nodbg_end()) / Length) < Ratio)) {
+        // Before giving up coalescing, if definition of source is defined by
+        // trivial computation, try rematerializing it.
+        if (ReMaterializeTrivialDef(SrcInt, DstReg, DstSubIdx, CopyMI))
+          return true;
+
         mri_->setRegAllocationHint(JoinVInt.reg, 0, JoinPReg);
         ++numAborts;
         DEBUG(dbgs() << "\tMay tie down a physical register, abort!\n");

diff --git a/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll b/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll
index ae723f0c299eebc5f72d5d3cb5f1c09f4518b559..d9655fd19b3c361b110a966574ff6492713fb86a 100644 (file)
--- a/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll
+++ b/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll
@@ -1,5 +1,7 @@
 ; RUN: llc < %s -march=x86-64 -mattr=+sse3 -stats |& grep {2 machine-licm}
+; RUN: llc < %s -march=x86-64 -mattr=+sse3 | FileCheck %s
 ; rdar://6627786
+; rdar://7792037
 
 target triple = "x86_64-apple-darwin10.0"
        %struct.Key = type { i64 }
@@ -11,6 +13,13 @@ entry:
        br label %bb4
 
 bb4:           ; preds = %bb.i, %bb26, %bb4, %entry
+; CHECK: %bb4
+; CHECK: xorb
+; CHECK: callq
+; CHECK: movq
+; CHECK: xorl
+; CHECK: xorb
+
        %0 = call i32 (...)* @xxGetOffsetForCode(i32 undef) nounwind            ; <i32> [#uses=0]
        %ins = or i64 %p, 2097152               ; <i64> [#uses=1]
        %1 = call i32 (...)* @xxCalculateMidType(%struct.Key* %desc, i32 0) nounwind            ; <i32> [#uses=1]

diff --git a/test/CodeGen/X86/phys_subreg_coalesce-2.ll b/test/CodeGen/X86/phys_subreg_coalesce-2.ll
index 60ec2645c28b412e6a9c8c99a60a4c14a66391f5..23c509c9936bd251e9da5d09834990608d4ab29c 100644 (file)
--- a/test/CodeGen/X86/phys_subreg_coalesce-2.ll
+++ b/test/CodeGen/X86/phys_subreg_coalesce-2.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86 | grep mov | count 6
+; RUN: llc < %s -march=x86 | grep mov | count 5
 ; PR2659
 
 define i32 @binomial(i32 %n, i32 %k) nounwind {

diff --git a/test/CodeGen/X86/pr2659.ll b/test/CodeGen/X86/pr2659.ll
index 01bb9f14f64183225c50d5697b3b2d577b43e1d4..27047dfdfd8cf00b5c141f368442c918143c93d6 100644 (file)
--- a/test/CodeGen/X86/pr2659.ll
+++ b/test/CodeGen/X86/pr2659.ll
@@ -1,4 +1,5 @@
-; RUN: llc < %s -march=x86 -mtriple=i686-apple-darwin9.4.0 | grep movl | count 6
+; RUN: llc < %s -march=x86 -mtriple=i686-apple-darwin9.4.0 | grep movl | count 5
+; RUN: llc < %s -march=x86 -mtriple=i686-apple-darwin9.4.0 | FileCheck %s
 ; PR2659
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
@@ -13,6 +14,11 @@ forcond.preheader:              ; preds = %entry
   %cmp44 = icmp eq i32 %k, 0            ; <i1> [#uses=1]
   br i1 %cmp44, label %afterfor, label %forbody
 
+; CHECK: %forcond.preheader.forbody_crit_edge
+; CHECK: movl $1
+; CHECK-NOT: xorl
+; CHECK-NEXT: movl $1
+
 ifthen:         ; preds = %entry
   ret i32 0