#include <linux/spi/spi.h>\r
#include <linux/mmc/host.h>\r
#include <linux/android_pmem.h>\r
+#include <linux/usb/android_composite.h>\r
\r
#include <mach/hardware.h>\r
#include <asm/setup.h>\r
},\r
};\r
#endif\r
+/********************usb*********************/\r
+struct usb_mass_storage_platform_data mass_storage_pdata = {\r
+ .nluns = 1,\r
+ .vendor = "RockChip",\r
+ .product = "rk9 sdk",\r
+ .release = 0x0100,\r
+};\r
\r
static void __init rk29_board_iomux_init(void)\r
{\r
#endif\r
&android_pmem_device,\r
&rk29_vpu_mem_device,\r
+#ifdef CONFIG_DWC_OTG\r
+ &rk29_device_dwc_otg,\r
+#endif\r
+#ifdef CONFIG_USB_ANDROID\r
+ &android_usb_device,\r
+ &usb_mass_storage_device,\r
+#endif\r
};\r
\r
/*****************************************************************************************\r
#include <linux/fs.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
+#include <linux/usb/android_composite.h>
#include <linux/delay.h>
#include <mach/irqs.h>
#include <mach/rk29_iomap.h>
.resource = rk29_iis_8ch_resource,
};
#endif
+#ifdef CONFIG_DWC_OTG
+/*DWC_OTG*/
+static struct resource dwc_otg_resource[] = {
+ {
+ .start = IRQ_USB_OTG0,
+ .end = IRQ_USB_OTG0,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .start = RK29_USBOTG0_PHYS,
+ .end = RK29_USBOTG0_PHYS + RK29_USBOTG0_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+
+};
+
+struct platform_device rk29_device_dwc_otg = {
+ .name = "dwc_otg",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(dwc_otg_resource),
+ .resource = dwc_otg_resource,
+};
+
+static char *usb_functions_rockchip[] = {
+ "usb_mass_storage",
+};
+
+static char *usb_functions_rockchip_adb[] = {
+ "usb_mass_storage",
+ "adb",
+};
+
+static char *usb_functions_rndis_rockchip[] = {
+ "rndis",
+ "usb_mass_storage",
+};
+
+static char *usb_functions_rndis_rockchip_adb[] = {
+ "rndis",
+ "usb_mass_storage",
+ "adb",
+};
+
+#ifdef CONFIG_USB_ANDROID_DIAG
+static char *usb_functions_adb_diag[] = {
+ "usb_mass_storage",
+ "adb",
+ "diag",
+};
+#endif
+
+static char *usb_functions_all[] = {
+#ifdef CONFIG_USB_ANDROID_RNDIS
+ "rndis",
+#endif
+ "usb_mass_storage",
+#ifdef CONFIG_USB_ANDROID_ADB
+ "adb",
+#endif
+#ifdef CONFIG_USB_ANDROID_ACM
+ "acm",
+#endif
+#ifdef CONFIG_USB_ANDROID_DIAG
+ "diag",
+#endif
+};
+
+static struct android_usb_product usb_products[] = {
+ {
+ .product_id = 0x2810,//0x0c02,//0x4e11,
+ .num_functions = ARRAY_SIZE(usb_functions_rockchip),
+ .functions = usb_functions_rockchip,
+ },
+ {
+ .product_id = 0x4e12,
+ .num_functions = ARRAY_SIZE(usb_functions_rockchip_adb),
+ .functions = usb_functions_rockchip_adb,
+ },
+ {
+ .product_id = 0x4e13,
+ .num_functions = ARRAY_SIZE(usb_functions_rndis_rockchip),
+ .functions = usb_functions_rndis_rockchip,
+ },
+ {
+ .product_id = 0x4e14,
+ .num_functions = ARRAY_SIZE(usb_functions_rndis_rockchip_adb),
+ .functions = usb_functions_rndis_rockchip_adb,
+ },
+#ifdef CONFIG_USB_ANDROID_DIAG
+ {
+ .product_id = 0x4e17,
+ .num_functions = ARRAY_SIZE(usb_functions_adb_diag),
+ .functions = usb_functions_adb_diag,
+ },
+#endif
+};
+
+static struct android_usb_platform_data android_usb_pdata = {
+ .vendor_id = 0x2207,//0x0bb4,//0x18d1,
+ .product_id = 0x2810,//0x4e11,
+ .version = 0x0100,
+ .product_name = "rk2818 sdk",
+ .manufacturer_name = "RockChip",
+ .num_products = ARRAY_SIZE(usb_products),
+ .products = usb_products,
+ .num_functions = ARRAY_SIZE(usb_functions_all),
+ .functions = usb_functions_all,
+};
+
+//static
+struct platform_device android_usb_device = {
+ .name = "android_usb",
+ .id = -1,
+ .dev = {
+ .platform_data = &android_usb_pdata,
+ },
+};
+
+//static
+struct platform_device usb_mass_storage_device = {
+ .name = "usb_mass_storage",
+ .id = -1,
+ .dev = {
+ .platform_data = &mass_storage_pdata,
+ },
+};
+#endif
extern struct platform_device rk29_device_adc;
extern struct rk29_bl_info rk29_bl_info;
extern struct platform_device rk29_device_backlight;
+extern struct platform_device rk29_device_dwc_otg;
+extern struct platform_device android_usb_device;
+extern struct usb_mass_storage_platform_data mass_storage_pdata;
+extern struct platform_device usb_mass_storage_device;
#endif
}
DEVICE_ATTR(wr_reg_test, S_IRUGO|S_IWUSR, wr_reg_test_show, 0);
+extern int dwc_debug(int flag);
+static ssize_t debug_show( struct device *_dev,
+ struct device_attribute *attr, char *buf)
+{
+ dwc_otg_device_t *otg_dev = _dev->platform_data;
+ dwc_otg_dump_global_registers( otg_dev->core_if);
+ if (dwc_otg_is_host_mode(otg_dev->core_if)) {
+ dwc_otg_dump_host_registers( otg_dev->core_if);
+ } else {
+ dwc_otg_dump_dev_registers( otg_dev->core_if);
+ }
+ return sprintf( buf, "Register Dump\n" );
+}
+static ssize_t debug_store( struct device *_dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count )
+{
+ uint32_t val = simple_strtoul(buf, NULL, 16);
+ dwc_debug(val);
+ return count;
+}
+
+DEVICE_ATTR(step, S_IRUGO|S_IWUSR, debug_show, debug_store);
/**@}*/
/**
error |= device_create_file(dev, &dev_attr_hcd_frrem);
error |= device_create_file(dev, &dev_attr_rd_reg_test);
error |= device_create_file(dev, &dev_attr_wr_reg_test);
+ error |= device_create_file(dev, &dev_attr_step);
if (error)
pr_err("DWC_OTG: Creating some device files failed\n");
}
device_remove_file(dev, &dev_attr_hcd_frrem);
device_remove_file(dev, &dev_attr_rd_reg_test);
device_remove_file(dev, &dev_attr_wr_reg_test);
+ device_remove_file(dev, &dev_attr_step);
}
#endif
#include "linux/dwc_otg_plat.h"
-#include <mach/rk2818_iomap.h>
#include "dwc_otg_regs.h"
#include "dwc_otg_driver.h"
#include "dwc_otg_cil.h"
-#define SCU_BASE_ADDR_VA RK2818_SCU_BASE
static dwc_otg_core_if_t * dwc_core_if = NULL;
/**
* This function is called to initialize the DWC_otg CSR data
dwc_write_reg32( &_core_if->dev_if->dev_global_regs->dctl, dctl.d32 );
/* Configure data FIFO sizes */
- dwc_write_reg32( &global_regs->grxfsiz, 0x00000400 );
- dwc_write_reg32( &global_regs->gnptxfsiz, 0x00200400 ); //ep0 tx fifo
- dwc_write_reg32( &global_regs->dptxfsiz_dieptxf[0], 0x01000420 ); //ep1 tx fifo
- dwc_write_reg32( &global_regs->dptxfsiz_dieptxf[1], 0x00200520 ); //ep3 tx fifo
- dwc_write_reg32( &global_regs->dptxfsiz_dieptxf[2], 0x01800540 ); //ep5 tx fifo
+ dwc_write_reg32( &global_regs->grxfsiz, 0x00000210 );
+ dwc_write_reg32( &global_regs->gnptxfsiz, 0x00100210 ); //ep0 tx fifo
+ dwc_write_reg32( &global_regs->dptxfsiz_dieptxf[0], 0x01000220 ); //ep1 tx fifo
+ dwc_write_reg32( &global_regs->dptxfsiz_dieptxf[1], 0x00100320 ); //ep3 tx fifo
+ dwc_write_reg32( &global_regs->dptxfsiz_dieptxf[2], 0x00800330 ); //ep5 tx fifo
if(_core_if->en_multiple_tx_fifo && _core_if->dma_enable)
{
volatile grstctl_t greset = { .d32 = 0};
volatile gusbcfg_data_t usbcfg = { .d32 = 0 };
volatile gintsts_data_t gintsts = { .d32 = 0 };
+ volatile dctl_data_t dctl = {.d32 = 0};
int count = 0;
DWC_DEBUGPL(DBG_CILV, "%s\n", __func__);
/* Wait for AHB master IDLE state. */
}
}
while (greset.b.ahbidle == 0);
-
+#if 1
/* Core Soft Reset */
count = 0;
greset.b.csftrst = 1;
}
while (greset.b.csftrst == 1);
+ dctl.d32 = dwc_read_reg32( &_core_if->dev_if->dev_global_regs->dctl );
+ dctl.b.sftdiscon = 1;
+ dwc_write_reg32( &_core_if->dev_if->dev_global_regs->dctl, dctl.d32 );
+#endif
usbcfg.d32 = dwc_read_reg32( &global_regs->gusbcfg);
if(_core_if->usb_mode == USB_MODE_FORCE_HOST)
{
dwc_write_reg32( &global_regs->gusbcfg, usbcfg.d32 );
/* Wait for 3 PHY Clocks*/
//DWC_PRINT("100ms\n");
- mdelay(10);
+ mdelay(100);
count = 0;
if(usbcfg.b.force_hst_mode)
do
printk("SCU_CLKGATE2_CON: 0x%08x\n",regvalue);
regvalue = dwc_read_reg32((uint32_t *)(SCU_BASE_ADDR_VA+0x28));
printk("SCU_SOFTRST_CON: 0x%08x\n",regvalue);
- regvalue = dwc_read_reg32((uint32_t *)(RK2818_REGFILE_BASE+0x3c));
+ regvalue = dwc_read_reg32((uint32_t *)(USB_GRF_CON));
printk("USB_PHY_CON1: 0x%08x\n",regvalue);
}
-extern void dwc_otg_dump_pcd_flags(void);
void dwc_otg_dump_flags(dwc_otg_core_if_t *_core_if)
{
printk("_______________________dwc_otg flags_______________________________\n");
printk("core_if->op_state = %x\n",_core_if->op_state);
printk("core_if->usb_mode = %x\n",_core_if->usb_mode);
printk("core_if->usb_wakeup = %x\n",_core_if->usb_wakeup);
- dwc_otg_dump_pcd_flags();
}
-extern int rk28_msc_switch(int action);
+int dwc_step = 0;
int dwc_debug(int flag)
{
dwc_otg_core_if_t *core_if = dwc_core_if;
break;
case 7:
dwc_otg_dump_flags(core_if);
- rk28_msc_switch(2);
break;
case 8:
- rk28_msc_switch(2);
+ dwc_step = 0;
break;
case 9:
dwc_otg_dump_flags(core_if);
#include <asm/io.h>
#include <asm/sizes.h>
-#include <mach/rk2818_iomap.h>
#include "linux/dwc_otg_plat.h"
#include <linux/platform_device.h>
dwc_otg_device_t *dwc_otg_device;
int32_t snpsid;
int irq;
- uint32_t otgreg;
/*
*Enable usb phy
*/
- unsigned int * otg_phy_con1 = (unsigned int*)(RK2818_REGFILE_BASE+0x3c);
+ unsigned int * otg_phy_con1 = (unsigned int*)(USB_GRF_CON);
*otg_phy_con1 |= (0x01<<2);
*otg_phy_con1 |= (0x01<<3); // exit suspend.
goto fail;
dwc_otg_device->base =
- ioremap(res_base->start,RK2818_USBOTG_SIZE);
+ ioremap(res_base->start,USBOTG_SIZE);
if (dwc_otg_device->base == NULL)
{
dev_err(dev, "ioremap() failed\n");
if(core_if->usb_wakeup)
{
core_if->usb_wakeup = 0;
-// rk28_send_wakeup_key(); /* exit wake up */
}
return 0;
}
void rk28_host11_driver_enable(dwc_otg_core_if_t *core_if)
{
- unsigned int * otg_phy_con1 = (unsigned int*)(RK2818_REGFILE_BASE+0x3c);
- unsigned int * scu_clkgate1_con = (unsigned int*)(RK2818_SCU_BASE+0x20);
+ unsigned int * otg_phy_con1 = (unsigned int*)(USB_GRF_CON);
+ unsigned int * scu_clkgate1_con = (unsigned int*)(USB_CLKGATE_CON);
/*
* enable usb phy & clockgate host controller
*/
void rk28_host11_driver_disable(dwc_otg_core_if_t *core_if)
{
- unsigned int * otg_phy_con1 = (unsigned int*)(RK2818_REGFILE_BASE+0x3c);
- unsigned int * scu_clkgate1_con = (unsigned int*)(RK2818_SCU_BASE+0x20);
+ unsigned int * otg_phy_con1 = (unsigned int*)(USB_GRF_CON);
+ unsigned int * scu_clkgate1_con = (unsigned int*)(USB_CLKGATE_CON);
dwc_otg_disable_global_interrupts( core_if );
hub_disconnect_device(g_root_hub11);
if (core_if->hcd_cb && core_if->hcd_cb->stop) {
/*
*Enable usb phy
*/
- unsigned int * otg_phy_con1 = (unsigned int*)(RK2818_REGFILE_BASE+0x3c);
+ unsigned int * otg_phy_con1 = (unsigned int*)(USB_GRF_CON);
*otg_phy_con1 &= ~(0x01<<31); // exit suspend.
#if 0
*otg_phy_con1 |= (0x01<<2);
goto fail;
dwc_otg_device->base =
- ioremap(res_base->start,RK2818_USBHOST_SIZE);
+ ioremap(res_base->start,USBOTG_SIZE);
printk("%s host1.1 reg addr: 0x%x remap:0x%x\n",__func__,
(unsigned)res_base->start, (unsigned)dwc_otg_device->base);
if (dwc_otg_device->base == NULL)
#include <linux/usb/gadget.h>
#include <linux/platform_device.h>
-#include <mach/rk2818_iomap.h>
-
#include "dwc_otg_driver.h"
#include "dwc_otg_pcd.h"
#include "dwc_otg_regs.h"
DWC_DEBUGPL(DBG_PCDV,"%s(%p)\n", __func__, _dev);
}
-extern void rk28_send_wakeup_key( void ) ;
int dwc_pcd_reset(dwc_otg_pcd_t *pcd)
{
dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
{
dwc_otg_pcd_t *pcd = s_pcd;
- unsigned int * otg_phy_con1 = (unsigned int*)(RK2818_REGFILE_BASE+0x3c);
+ unsigned int * otg_phy_con1 = (unsigned int*)(USB_GRF_CON);
// unsigned int * usb_core_ctrl_reg = (unsigned int*)(USB_OTG_BASE_ADDR_VA);
if(exitsuspend && (pcd->phy_suspend == 1)) {
pcd->phy_suspend = 0;
android_unlock_suspend(&usb_msc_lock);
#endif
}
-
+extern int dwc_step;
static void dwc_phy_reconnect(struct work_struct *work)
{
dwc_otg_pcd_t *pcd;
* Enable the global interrupt after all the interrupt
* handlers are installed.
*/
+ #if 0
+ printk("debug while 1, please enter command to continue!\n");
+ dwc_step = 1;
+ while(dwc_step)
+ mdelay(5);
+ #endif
dctl.d32 = dwc_read_reg32( &core_if->dev_if->dev_global_regs->dctl );
dctl.b.sftdiscon = 0;
dwc_write_reg32( &core_if->dev_if->dev_global_regs->dctl, dctl.d32 );
dwc_otg_pcd_t *pcd = s_pcd;
return pcd->vbus_status ;
}
-int dwc_otg_set_vbus_status(uint8_t status)
-{
- dwc_otg_pcd_t *pcd = s_pcd;
- pcd->vbus_status = status;
- return pcd->vbus_status;
-}
int dwc_otg_set_phy_status(uint8_t status)
{
dwc_otg_pcd_t *pcd = s_pcd;
return 0;
}
EXPORT_SYMBOL(usb_gadget_unregister_driver);
-void dwc_otg_dump_pcd_flags(void)
-{
- dwc_otg_pcd_t *pcd = s_pcd;
- if(pcd)
- {
- printk("pcd->phy_suspend = %x\n",pcd->phy_suspend);
- printk("pcd->vbus_status = %x\n",pcd->vbus_status);
- printk("pcd->conn_status = %x\n",pcd->conn_status);
- }
-}
-int rk28_msc_switch(int action)
-{
- return 0;
-}
#else
-int dwc_otg_set_vbus_status(int status)
-{
- return 0;
-}
int rk28_usb_suspend( int exitsuspend )
{
return 0;
{
return 0;
}
-void dwc_otg_dump_pcd_flags(void)
-{
- return;
-}
-int rk28_msc_switch(int action)
-{
- return 0;
-}
#endif /* DWC_HOST_ONLY */
#include "dwc_otg_pcd.h"
-//#define DEBUG_EP0
+#define DEBUG_EP0
/* request functions defined in "dwc_otg_pcd.c" */
extern void request_done( dwc_otg_pcd_ep_t *_ep, dwc_otg_pcd_request_t *_req,
#include <linux/delay.h>
#include <asm/io.h>
+#include <mach/rk29_iomap.h>
+#define GRF_REG_BASE RK29_GRF_BASE
+#define USB20_OTG0_BASE RK29_USBOTG0_PHYS
+#define USB20_OTG1_BASE RK29_USBOTG1_PHYS
+#define USB11_HOST_BASE RK29_USBHOST_PHYS
+#define USBOTG_SIZE RK29_USBOTG0_SIZE
+#define USB_GRF_CON (GRF_REG_BASE+0X9C)
+#define USB_CLKGATE_CON (RK29_CRU_BASE+0X60)
+#ifndef SCU_BASE_ADDR_VA
+#define SCU_BASE_ADDR_VA RK29_CRU_BASE
+#endif
/**
* @file
*
/* Default vendor and product IDs, overridden by platform data */
#define VENDOR_ID 0x2207//0x18D1
-#define PRODUCT_ID 0x2810
+#define PRODUCT_ID 0x2910
struct android_dev {
struct usb_composite_dev *cdev;
projects / firefly-linux-kernel-4.4.55.git / commitdiff