Fix test/Regression/ExecutionEngine/2005-12-02-TailCallBug.ll and PR672.

This also fixes 177.mesa, the only program that fails with --enable-x86-fastcc
turned on.  Given a clean nightly tester run, we should be able to turn it
on by default!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24578 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86ISelPattern.cpp b/lib/Target/X86/X86ISelPattern.cpp
index 5c4594aa9ec9bc2f16eb064b1e70bec62ff4f552..28f799ee4a85b71207db2680e53bd8e89a2993d1 100644 (file)
--- a/lib/Target/X86/X86ISelPattern.cpp
+++ b/lib/Target/X86/X86ISelPattern.cpp
@@ -3067,6 +3067,20 @@ void ISel::EmitFastCCToFastCCTailCall(SDNode *TailCallNode) {
 
   // TODO: handle jmp [mem]
   if (!isDirect) {
+    // We do not want the register allocator to allocate CalleeReg to a callee 
+    // saved register, as these will be restored before the JMP.  To prevent
+    // this, emit explicit clobbers of callee saved regs here.  A better way to
+    // solve this would be to specify that the register constraints of TAILJMPr
+    // only allow registers that are not callee saved, but we currently can't
+    // express that.  This forces all four of these regs to be saved and 
+    // reloaded for all functions with an indirect tail call.
+    // TODO: Improve this!
+    BuildMI(BB, X86::IMPLICIT_DEF, 4)
+       .addReg(X86::ESI, MachineOperand::Def)
+       .addReg(X86::EDI, MachineOperand::Def)
+       .addReg(X86::EBX, MachineOperand::Def)
+       .addReg(X86::EBP, MachineOperand::Def);
+    
     BuildMI(BB, X86::TAILJMPr, 1).addReg(CalleeReg);
   } else if (GlobalAddressSDNode *GASD = dyn_cast<GlobalAddressSDNode>(Callee)){
     BuildMI(BB, X86::TAILJMPd, 1).addGlobalAddress(GASD->getGlobal(), true);