ARM: dts: imx6qdl: Enable CODA960 VPU
authorPhilipp Zabel <p.zabel@pengutronix.de>
Tue, 11 Nov 2014 21:12:47 +0000 (19:12 -0200)
committerShawn Guo <shawn.guo@linaro.org>
Sun, 23 Nov 2014 07:08:12 +0000 (15:08 +0800)
This patch adds links to the on-chip SRAM and reset controller nodes
and switches the interrupts. Make the BIT processor interrupt, which exists on
all variants, the first one. The JPEG unit interrupt, which does not exist on
i.MX27 and i.MX5 thus is an optional second interrupt.
Use different compatible strings for i.MX6Q/D and i.MX6S/DL, as they have to
load separate firmware images for some reason.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
arch/arm/boot/dts/imx6dl.dtsi
arch/arm/boot/dts/imx6q.dtsi
arch/arm/boot/dts/imx6qdl.dtsi

index 44d887656712d467fe2bdce345700b281534a970..1ac2fe7328679b128da6ef74669abad2d4bd08fd 100644 (file)
                      "di0_sel", "di1_sel",
                      "di0", "di1";
 };
+
+&vpu {
+       compatible = "fsl,imx6dl-vpu", "cnm,coda960";
+};
index e9f3646d1760618cb04027329754c53194068a8c..85f72e6b5badebe9afb92a4ebda4414efb19aa83 100644 (file)
                };
        };
 };
+
+&vpu {
+       compatible = "fsl,imx6q-vpu", "cnm,coda960";
+};
index 9596ed5867e6d9a6b838d5c6880ab0d86b26bb4b..e529308811e6030676d8611488180fb8dc2990f6 100644 (file)
                        };
 
                        vpu: vpu@02040000 {
+                               compatible = "cnm,coda960";
                                reg = <0x02040000 0x3c000>;
                                interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>,
                                             <0 12 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupt-names = "bit", "jpeg";
+                               clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
+                                        <&clks IMX6QDL_CLK_MMDC_CH0_AXI>,
+                                        <&clks IMX6QDL_CLK_OCRAM>;
+                               clock-names = "per", "ahb", "ocram";
+                               resets = <&src 1>;
+                               iram = <&ocram>;
                        };
 
                        aipstz@0207c000 { /* AIPSTZ1 */