Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't

optimize it to a SINT_TO_FP when the sign bit is known zero. X86 isel should perform the optimization itself.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62504 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 544b71cf8f8f42aba537b503cc779f73155c1b86..0f5103b5c6779599edcb01ac3eb2bb988e463846 100644 (file)
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -4884,8 +4884,15 @@ SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) {
 }
 
 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
-  MVT SrcVT = Op.getOperand(0).getValueType();
+  SDValue N0 = Op.getOperand(0);
+
+  // Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't
+  // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
+  // the optimization here.
+  if (DAG.SignBitIsZero(N0))
+    return DAG.getNode(ISD::SINT_TO_FP, Op.getValueType(), N0);
 
+  MVT SrcVT = N0.getValueType();
   if (SrcVT == MVT::i64) {
     // We only handle SSE2 f64 target here; caller can handle the rest.
     if (Op.getValueType() != MVT::f64 || !X86ScalarSSEf64)

diff --git a/test/CodeGen/X86/uint_to_fp.ll b/test/CodeGen/X86/uint_to_fp.ll
index 3ea7a947b967bd902f1233b8ce262221095e53be..148437f3ddbf131069b633b4ffb34d1909d815cf 100644 (file)
--- a/test/CodeGen/X86/uint_to_fp.ll
+++ b/test/CodeGen/X86/uint_to_fp.ll
@@ -1,4 +1,5 @@
 ; RUN: llvm-as < %s | llc -march=x86 -mcpu=yonah | not grep {sub.*esp}
+; RUN: llvm-as < %s | llc -march=x86 -mcpu=yonah | grep cvtsi2ss
 ; rdar://6034396
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"