tegra_dc_setup_clk(dc, dc->clk);
clk_enable(dc->clk);
+ clk_enable(dc->emc_clk);
enable_irq(dc->irq);
tegra_dc_init(dc);
if (dc->out_ops && dc->out_ops->disable)
dc->out_ops->disable(dc);
+ clk_disable(dc->emc_clk);
clk_disable(dc->clk);
tegra_dvfs_set_rate(dc->clk, 0);
{
struct tegra_dc *dc;
struct clk *clk;
+ struct clk *emc_clk;
struct resource *res;
struct resource *base_res;
struct resource *fb_mem = NULL;
goto err_iounmap_reg;
}
+ emc_clk = clk_get(&ndev->dev, "emc");
+ if (IS_ERR_OR_NULL(emc_clk)) {
+ dev_err(&ndev->dev, "can't get emc clock\n");
+ ret = -ENOENT;
+ goto err_put_clk;
+ }
+
+ /*
+ * The emc is a shared clock, it will be set to the highest
+ * requested rate from any user. Set the rate to ULONG_MAX to
+ * always request the max rate whenever this request is enabled
+ */
+ clk_set_rate(emc_clk, ULONG_MAX);
+
dc->clk = clk;
+ dc->emc_clk = emc_clk;
dc->base_res = base_res;
dc->base = base;
dc->irq = irq;
dev_name(&ndev->dev), dc)) {
dev_err(&ndev->dev, "request_irq %d failed\n", irq);
ret = -EBUSY;
- goto err_put_clk;
+ goto err_put_emc_clk;
}
/* hack to ballence enable_irq calls in _tegra_dc_enable() */
err_free_irq:
free_irq(irq, dc);
+err_put_emc_clk:
+ clk_put(emc_clk);
err_put_clk:
clk_put(clk);
err_iounmap_reg:
_tegra_dc_disable(dc);
free_irq(dc->irq, dc);
+ clk_put(dc->emc_clk);
clk_put(dc->clk);
iounmap(dc->base);
if (dc->fb_mem)