Lower vector compares to VCMP nodes, just like we lower vector comparison

predicates to VCMPo nodes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27285 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index 2aabd4b51439220490cfeea6a56e8551914801dd..d5da69f5062ec1332d2a87928e517deaeaf6da3b 100644 (file)
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -235,6 +235,7 @@ const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
   case PPCISD::CALL:          return "PPCISD::CALL";
   case PPCISD::RET_FLAG:      return "PPCISD::RET_FLAG";
   case PPCISD::MFCR:          return "PPCISD::MFCR";
+  case PPCISD::VCMP:          return "PPCISD::VCMP";
   case PPCISD::VCMPo:         return "PPCISD::VCMPo";
   }
 }
@@ -752,31 +753,53 @@ SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
     return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask);
   }
   case ISD::INTRINSIC_WO_CHAIN: {
-    bool HasChain = Op.getOperand(0).getValueType() == MVT::Other;
-    unsigned IntNo=cast<ConstantSDNode>(Op.getOperand(HasChain))->getValue();
+    unsigned IntNo=cast<ConstantSDNode>(Op.getOperand(0))->getValue();
     
     // If this is a lowered altivec predicate compare, CompareOpc is set to the
     // opcode number of the comparison.
     int CompareOpc = -1;
+    bool isDot = false;
     switch (IntNo) {
     default: return SDOperand();    // Don't custom lower most intrinsics.
-    case Intrinsic::ppc_altivec_vcmpbfp_p:  CompareOpc = 966; break;
-    case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; break;
-    case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc =   6; break;
-    case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc =  70; break;
-    case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; break;
-    case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; break;
-    case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; break;
-    case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; break;
-    case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; break;
-    case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; break;
-    case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; break;
-    case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; break;
-    case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; break;
+    // Comparison predicates.
+    case Intrinsic::ppc_altivec_vcmpbfp_p:  CompareOpc = 966; isDot = 1; break;
+    case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
+    case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc =   6; isDot = 1; break;
+    case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc =  70; isDot = 1; break;
+    case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
+    case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
+    case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
+    case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
+    case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
+    case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
+    case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
+    case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
+    case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
+
+    // Normal Comparisons.
+    case Intrinsic::ppc_altivec_vcmpbfp:    CompareOpc = 966; isDot = 0; break;
+    case Intrinsic::ppc_altivec_vcmpeqfp:   CompareOpc = 198; isDot = 0; break;
+    case Intrinsic::ppc_altivec_vcmpequb:   CompareOpc =   6; isDot = 0; break;
+    case Intrinsic::ppc_altivec_vcmpequh:   CompareOpc =  70; isDot = 0; break;
+    case Intrinsic::ppc_altivec_vcmpequw:   CompareOpc = 134; isDot = 0; break;
+    case Intrinsic::ppc_altivec_vcmpgefp:   CompareOpc = 454; isDot = 0; break;
+    case Intrinsic::ppc_altivec_vcmpgtfp:   CompareOpc = 710; isDot = 0; break;
+    case Intrinsic::ppc_altivec_vcmpgtsb:   CompareOpc = 774; isDot = 0; break;
+    case Intrinsic::ppc_altivec_vcmpgtsh:   CompareOpc = 838; isDot = 0; break;
+    case Intrinsic::ppc_altivec_vcmpgtsw:   CompareOpc = 902; isDot = 0; break;
+    case Intrinsic::ppc_altivec_vcmpgtub:   CompareOpc = 518; isDot = 0; break;
+    case Intrinsic::ppc_altivec_vcmpgtuh:   CompareOpc = 582; isDot = 0; break;
+    case Intrinsic::ppc_altivec_vcmpgtuw:   CompareOpc = 646; isDot = 0; break;
     }
     
     assert(CompareOpc>0 && "We only lower altivec predicate compares so far!");
 
+    // If this is a non-dot comparison, make the VCMP node.
+    if (!isDot)
+      return DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(),
+                         Op.getOperand(1), Op.getOperand(2),
+                         DAG.getConstant(CompareOpc, MVT::i32));
+    
     // Create the PPCISD altivec 'dot' comparison node.
     std::vector<SDOperand> Ops;
     std::vector<MVT::ValueType> VTs;

diff --git a/lib/Target/PowerPC/PPCISelLowering.h b/lib/Target/PowerPC/PPCISelLowering.h
index 7a7c6290ca17fc94a9b3f5482e709ddc15f0483d..bc865c6cb4b5130c99b15f80ef09f05e5d46680a 100644 (file)
--- a/lib/Target/PowerPC/PPCISelLowering.h
+++ b/lib/Target/PowerPC/PPCISelLowering.h
@@ -85,6 +85,12 @@ namespace llvm {
       /// This copies the bits corresponding to the specified CRREG into the
       /// resultant GPR.  Bits corresponding to other CR regs are undefined.
       MFCR,
+
+      /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
+      /// instructions.  For lack of better number, we use the opcode number
+      /// encoding for the OPC field to identify the compare.  For example, 838
+      /// is VCMPGTSH.
+      VCMP,
       
       /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the
       /// altivec VCMP*o instructions.  For lack of better number, we use the 

diff --git a/lib/Target/PowerPC/PPCInstrAltivec.td b/lib/Target/PowerPC/PPCInstrAltivec.td
index 948e293647037742fa0ba7d60fa68361f41090ad..18d01179a8146faa7c9676e8f441e0e18b53855e 100644 (file)
--- a/lib/Target/PowerPC/PPCInstrAltivec.td
+++ b/lib/Target/PowerPC/PPCInstrAltivec.td
@@ -453,32 +453,32 @@ def VUPKLSH : VXForm_2<718, (ops VRRC:$vD, VRRC:$vB),
 // f32 element comparisons.
 def VCMPBFP   : VXRForm_1<966, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                           "vcmpbfp $vD, $vA, $vB", VecFPCompare,
-                          [(set VRRC:$vD, 
-                                (int_ppc_altivec_vcmpbfp VRRC:$vA, VRRC:$vB))]>;
+                          [(set VRRC:$vD, (v4f32
+                                (PPCvcmp VRRC:$vA, VRRC:$vB, 966)))]>;
 def VCMPBFPo  : VXRForm_1<966, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                           "vcmpbfp. $vD, $vA, $vB", VecFPCompare,
                           [(set VRRC:$vD, (v4f32
                                 (PPCvcmp_o VRRC:$vA, VRRC:$vB, 966)))]>, isVDOT;
 def VCMPEQFP  : VXRForm_1<198, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                          "vcmpeqfp $vD, $vA, $vB", VecFPCompare,
-                         [(set VRRC:$vD, 
-                               (int_ppc_altivec_vcmpeqfp VRRC:$vA, VRRC:$vB))]>;
+                         [(set VRRC:$vD, (v4f32
+                               (PPCvcmp VRRC:$vA, VRRC:$vB, 198)))]>;
 def VCMPEQFPo : VXRForm_1<198, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                          "vcmpeqfp. $vD, $vA, $vB", VecFPCompare,
                          [(set VRRC:$vD, (v4f32
                                 (PPCvcmp_o VRRC:$vA, VRRC:$vB, 198)))]>, isVDOT;
 def VCMPGEFP  : VXRForm_1<454, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                          "vcmpgefp $vD, $vA, $vB", VecFPCompare,
-                         [(set VRRC:$vD, 
-                               (int_ppc_altivec_vcmpgefp VRRC:$vA, VRRC:$vB))]>;
+                         [(set VRRC:$vD, (v4f32
+                               (PPCvcmp VRRC:$vA, VRRC:$vB, 454)))]>;
 def VCMPGEFPo : VXRForm_1<454, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                          "vcmpgefp. $vD, $vA, $vB", VecFPCompare,
                          [(set VRRC:$vD, (v4f32
                                 (PPCvcmp_o VRRC:$vA, VRRC:$vB, 454)))]>, isVDOT;
 def VCMPGTFP  : VXRForm_1<710, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                          "vcmpgtfp $vD, $vA, $vB", VecFPCompare,
-                         [(set VRRC:$vD, 
-                               (int_ppc_altivec_vcmpgtfp VRRC:$vA, VRRC:$vB))]>;
+                         [(set VRRC:$vD, (v4f32
+                               (PPCvcmp VRRC:$vA, VRRC:$vB, 710)))]>;
 def VCMPGTFPo : VXRForm_1<710, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                          "vcmpgtfp. $vD, $vA, $vB", VecFPCompare,
                          [(set VRRC:$vD, (v4f32
@@ -487,24 +487,24 @@ def VCMPGTFPo : VXRForm_1<710, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
 // i8 element comparisons.
 def VCMPEQUB  : VXRForm_1<6, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                          "vcmpequb $vD, $vA, $vB", VecFPCompare,
-                         [(set VRRC:$vD, 
-                               (int_ppc_altivec_vcmpequb VRRC:$vA, VRRC:$vB))]>;
+                         [(set VRRC:$vD, (v16i8
+                               (PPCvcmp VRRC:$vA, VRRC:$vB, 6)))]>;
 def VCMPEQUBo : VXRForm_1<6, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                          "vcmpequb. $vD, $vA, $vB", VecFPCompare,
                          [(set VRRC:$vD, (v16i8
                                 (PPCvcmp_o VRRC:$vA, VRRC:$vB, 6)))]>, isVDOT;
 def VCMPGTSB  : VXRForm_1<774, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                          "vcmpgtsb $vD, $vA, $vB", VecFPCompare,
-                         [(set VRRC:$vD, 
-                               (int_ppc_altivec_vcmpgtsb VRRC:$vA, VRRC:$vB))]>;
+                         [(set VRRC:$vD, (v16i8
+                               (PPCvcmp VRRC:$vA, VRRC:$vB, 774)))]>;
 def VCMPGTSBo : VXRForm_1<774, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                          "vcmpgtsb. $vD, $vA, $vB", VecFPCompare,
                          [(set VRRC:$vD, (v16i8
                                 (PPCvcmp_o VRRC:$vA, VRRC:$vB, 774)))]>, isVDOT;
 def VCMPGTUB  : VXRForm_1<518, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                          "vcmpgtub $vD, $vA, $vB", VecFPCompare,
-                         [(set VRRC:$vD, 
-                               (int_ppc_altivec_vcmpgtub VRRC:$vA, VRRC:$vB))]>;
+                         [(set VRRC:$vD, (v16i8
+                               (PPCvcmp VRRC:$vA, VRRC:$vB, 518)))]>;
 def VCMPGTUBo : VXRForm_1<518, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                          "vcmpgtub. $vD, $vA, $vB", VecFPCompare,
                          [(set VRRC:$vD, (v16i8 
@@ -513,24 +513,24 @@ def VCMPGTUBo : VXRForm_1<518, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
 // i16 element comparisons.
 def VCMPEQUH  : VXRForm_1<70, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                          "vcmpequh $vD, $vA, $vB", VecFPCompare,
-                         [(set VRRC:$vD, 
-                               (int_ppc_altivec_vcmpequh VRRC:$vA, VRRC:$vB))]>;
+                         [(set VRRC:$vD, (v8i16 
+                               (PPCvcmp VRRC:$vA, VRRC:$vB, 70)))]>;
 def VCMPEQUHo : VXRForm_1<70, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                          "vcmpequh. $vD, $vA, $vB", VecFPCompare,
                          [(set VRRC:$vD, (v8i16 
                                 (PPCvcmp_o VRRC:$vA, VRRC:$vB, 70)))]>, isVDOT;
 def VCMPGTSH  : VXRForm_1<838, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                          "vcmpgtsh $vD, $vA, $vB", VecFPCompare,
-                         [(set VRRC:$vD, 
-                               (int_ppc_altivec_vcmpgtsh VRRC:$vA, VRRC:$vB))]>;
+                         [(set VRRC:$vD, (v8i16 
+                               (PPCvcmp VRRC:$vA, VRRC:$vB, 838)))]>;
 def VCMPGTSHo : VXRForm_1<838, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                          "vcmpgtsh. $vD, $vA, $vB", VecFPCompare,
                          [(set VRRC:$vD, (v8i16 
                                 (PPCvcmp_o VRRC:$vA, VRRC:$vB, 838)))]>, isVDOT;
 def VCMPGTUH  : VXRForm_1<582, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                          "vcmpgtuh $vD, $vA, $vB", VecFPCompare,
-                         [(set VRRC:$vD, 
-                               (int_ppc_altivec_vcmpgtuh VRRC:$vA, VRRC:$vB))]>;
+                         [(set VRRC:$vD, (v8i16 
+                               (PPCvcmp VRRC:$vA, VRRC:$vB, 582)))]>;
 def VCMPGTUHo : VXRForm_1<582, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                          "vcmpgtuh. $vD, $vA, $vB", VecFPCompare,
                          [(set VRRC:$vD, (v8i16 
@@ -539,24 +539,23 @@ def VCMPGTUHo : VXRForm_1<582, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
 // i32 element comparisons.
 def VCMPEQUW  : VXRForm_1<134, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                          "vcmpequw $vD, $vA, $vB", VecFPCompare,
-                         [(set VRRC:$vD, 
-                               (int_ppc_altivec_vcmpequw VRRC:$vA, VRRC:$vB))]>;
+                         [(set VRRC:$vD, (PPCvcmp VRRC:$vA, VRRC:$vB, 134))]>;
 def VCMPEQUWo : VXRForm_1<134, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                          "vcmpequw. $vD, $vA, $vB", VecFPCompare,
                          [(set VRRC:$vD, (v4i32
                                 (PPCvcmp_o VRRC:$vA, VRRC:$vB, 134)))]>, isVDOT;
 def VCMPGTSW  : VXRForm_1<902, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                          "vcmpgtsw $vD, $vA, $vB", VecFPCompare,
-                         [(set VRRC:$vD, 
-                               (int_ppc_altivec_vcmpgtsw VRRC:$vA, VRRC:$vB))]>;
+                         [(set VRRC:$vD, (v4i32
+                               (PPCvcmp VRRC:$vA, VRRC:$vB, 902)))]>;
 def VCMPGTSWo : VXRForm_1<902, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                          "vcmpgtsw. $vD, $vA, $vB", VecFPCompare,
                          [(set VRRC:$vD, (v4i32
                                 (PPCvcmp_o VRRC:$vA, VRRC:$vB, 902)))]>, isVDOT;
 def VCMPGTUW  : VXRForm_1<646, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                          "vcmpgtuw $vD, $vA, $vB", VecFPCompare,
-                         [(set VRRC:$vD, 
-                               (int_ppc_altivec_vcmpgtuw VRRC:$vA, VRRC:$vB))]>;
+                         [(set VRRC:$vD, (v4i32
+                               (PPCvcmp VRRC:$vA, VRRC:$vB, 646)))]>;
 def VCMPGTUWo : VXRForm_1<646, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                          "vcmpgtuw. $vD, $vA, $vB", VecFPCompare,
                          [(set VRRC:$vD, (v4i32

diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td
index cb0f94b12f6904f4706088f34db62f1c5c6f4c0e..125425a63db6d271c68e100b803a4d0afdf849bf 100644 (file)
--- a/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/lib/Target/PowerPC/PPCInstrInfo.td
@@ -30,7 +30,7 @@ def SDT_PPCvperm   : SDTypeProfile<1, 3, [
   SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
 ]>;
 
-def SDT_PPCvcmp_o : SDTypeProfile<1, 3, [
+def SDT_PPCvcmp : SDTypeProfile<1, 3, [
   SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
 ]>;
 
@@ -71,7 +71,8 @@ def callseq_end   : SDNode<"ISD::CALLSEQ_END",   SDT_PPCCallSeq,[SDNPHasChain]>;
 def retflag       : SDNode<"PPCISD::RET_FLAG", SDT_PPCRetFlag,
                           [SDNPHasChain, SDNPOptInFlag]>;
 
-def PPCvcmp_o     : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp_o, [SDNPOutFlag]>;
+def PPCvcmp       : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
+def PPCvcmp_o     : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutFlag]>;
 
 //===----------------------------------------------------------------------===//
 // PowerPC specific transformation functions and pattern fragments.