}
-bool HexagonInstrInfo::
-isValidOffset(const int Opcode, const int Offset) const {
+bool HexagonInstrInfo::isValidOffset(unsigned Opcode, int Offset,
+ bool Extend) const {
// This function is to check whether the "Offset" is in the correct range of
- // the given "Opcode". If "Offset" is not in the correct range, "ADD_ri" is
+ // the given "Opcode". If "Offset" is not in the correct range, "A2_addi" is
// inserted to calculate the final address. Due to this reason, the function
// assumes that the "Offset" has correct alignment.
// We used to assert if the offset was not properly aligned, however,
// problem, and we need to allow for it. The front end warns of such
// misaligns with respect to load size.
- switch(Opcode) {
+ switch (Opcode) {
+ case Hexagon::J2_loop0i:
+ case Hexagon::J2_loop1i:
+ return isUInt<10>(Offset);
+ }
+
+ if (Extend)
+ return true;
+ switch (Opcode) {
case Hexagon::L2_loadri_io:
case Hexagon::S2_storeri_io:
return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
(Offset <= Hexagon_MEMB_OFFSET_MAX);
case Hexagon::A2_addi:
- case Hexagon::TFR_FI:
return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
(Offset <= Hexagon_ADDI_OFFSET_MAX);
case Hexagon::LDriw_pred:
return true;
- case Hexagon::J2_loop0i:
- return isUInt<10>(Offset);
-
- // INLINEASM is very special.
+ case Hexagon::TFR_FI:
+ case Hexagon::TFR_FIA:
case Hexagon::INLINEASM:
return true;
}
bool isSchedulingBoundary(const MachineInstr *MI,
const MachineBasicBlock *MBB,
const MachineFunction &MF) const override;
- bool isValidOffset(const int Opcode, const int Offset) const;
+ bool isValidOffset(unsigned Opcode, int Offset, bool Extend = true) const;
bool isValidAutoIncImm(const EVT VT, const int Offset) const;
bool isMemOp(const MachineInstr *MI) const;
bool isSpillPredRegOp(const MachineInstr *MI) const;