[ARM] tegra: clock: Don't BUG on changing an enabled PLL

Change-Id: Id213fd4ad8ae1e4429e31625c8b61d6be3fe708f
Signed-off-by: Colin Cross <ccross@android.com>

diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
index ee249cd1d74b3e102a00963f4864ff412a98b6f9..5b75cb3f5146503674e6217896a77059566f3bbd 100644 (file)
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ b/arch/arm/mach-tegra/tegra2_clocks.c
@@ -645,7 +645,6 @@ static int tegra2_pll_clk_set_rate(struct clk *c, unsigned long rate)
        const struct clk_pll_table *sel;
 
        pr_debug("%s: %s %lu\n", __func__, c->name, rate);
-       BUG_ON(c->refcnt != 0);
 
        input_rate = c->parent->rate;
        for (sel = c->pll_table; sel->input_rate != 0; sel++) {