gpu: ipu-v3: smfc: Add ipu_smfc_set_watermark()
authorSteve Longerbeam <slongerbeam@gmail.com>
Thu, 26 Jun 2014 01:05:35 +0000 (18:05 -0700)
committerPhilipp Zabel <p.zabel@pengutronix.de>
Tue, 2 Sep 2014 12:55:45 +0000 (14:55 +0200)
Adds ipu_smfc_set_watermark() which programs a channel's SMFC FIFO
levels at which the watermark signal is set and cleared.

Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
drivers/gpu/ipu-v3/ipu-smfc.c
include/video/imx-ipu-v3.h

index a6429ca913c16a65b01aafce119f6770b2b9edce..6ca9b43ce25a72ad195590a4ec12cf1857237b6a 100644 (file)
@@ -80,6 +80,26 @@ int ipu_smfc_map_channel(struct ipu_smfc *smfc, int csi_id, int mipi_id)
 }
 EXPORT_SYMBOL_GPL(ipu_smfc_map_channel);
 
+int ipu_smfc_set_watermark(struct ipu_smfc *smfc, u32 set_level, u32 clr_level)
+{
+       struct ipu_smfc_priv *priv = smfc->priv;
+       unsigned long flags;
+       u32 val, shift;
+
+       spin_lock_irqsave(&priv->lock, flags);
+
+       shift = smfc->chno * 6 + (smfc->chno > 1 ? 4 : 0);
+       val = readl(priv->base + SMFC_WMC);
+       val &= ~(0x3f << shift);
+       val |= ((clr_level << 3) | set_level) << shift;
+       writel(val, priv->base + SMFC_WMC);
+
+       spin_unlock_irqrestore(&priv->lock, flags);
+
+       return 0;
+}
+EXPORT_SYMBOL_GPL(ipu_smfc_set_watermark);
+
 int ipu_smfc_enable(struct ipu_smfc *smfc)
 {
        struct ipu_smfc_priv *priv = smfc->priv;
index a695ee83e4e19155bbc4bb93cff91ce90cb84cd4..49e5954ac0333a13942f96f0b26518aa085602f5 100644 (file)
@@ -296,6 +296,7 @@ int ipu_smfc_enable(struct ipu_smfc *smfc);
 int ipu_smfc_disable(struct ipu_smfc *smfc);
 int ipu_smfc_map_channel(struct ipu_smfc *smfc, int csi_id, int mipi_id);
 int ipu_smfc_set_burstsize(struct ipu_smfc *smfc, int burstsize);
+int ipu_smfc_set_watermark(struct ipu_smfc *smfc, u32 set_level, u32 clr_level);
 
 enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc);
 enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat);