rk3028 support uart48M
authorxxx <xxx@rock-chips.com>
Fri, 17 May 2013 10:27:40 +0000 (18:27 +0800)
committerxxx <xxx@rock-chips.com>
Fri, 17 May 2013 10:27:40 +0000 (18:27 +0800)
arch/arm/mach-rk30/board-rk3028-tb.c

index edaab5262ffeecfc428475d99205a7404125cfaf..6bd24afc3b14c1d6f7fd9d8913db7e8620f3c2c3 100755 (executable)
@@ -2161,10 +2161,32 @@ static struct cpufreq_frequency_table dvfs_ddr_table[] = {
 //#define DVFS_CPU_TABLE_SIZE  (ARRAY_SIZE(dvfs_cpu_logic_table))
 //static struct cpufreq_frequency_table cpu_dvfs_table[DVFS_CPU_TABLE_SIZE];
 //static struct cpufreq_frequency_table dep_cpu2core_table[DVFS_CPU_TABLE_SIZE];
+int get_max_freq(struct cpufreq_frequency_table *table)
+{
+       int i,temp=0;
+       
+       for(i=0;table[i].frequency!= CPUFREQ_TABLE_END;i++)
+       {
+               if(temp<table[i].frequency)
+                       temp=table[i].frequency;
+       }       
+       printk("get_max_freq=%d\n",temp);
+       return temp;
+}
 
 void __init board_clock_init(void)
 {
-       rk30_clock_data_init(periph_pll_default, codec_pll_default, RK30_CLOCKS_DEFAULT_FLAGS);
+
+       u32 flags=RK30_CLOCKS_DEFAULT_FLAGS;
+#if !defined(CONFIG_ARCH_RK3188)
+       if(get_max_freq(dvfs_gpu_table)<=(400*1000))
+       {       
+               flags=RK30_CLOCKS_DEFAULT_FLAGS|CLK_GPU_GPLL;
+       }
+       else
+               flags=RK30_CLOCKS_DEFAULT_FLAGS|CLK_GPU_CPLL;
+#endif 
+       rk30_clock_data_init(periph_pll_default, codec_pll_default, flags);
        //dvfs_set_arm_logic_volt(dvfs_cpu_logic_table, cpu_dvfs_table, dep_cpu2core_table);    
        dvfs_set_freq_volt_table(clk_get(NULL, "cpu"), dvfs_arm_table);
        dvfs_set_freq_volt_table(clk_get(NULL, "gpu"), dvfs_gpu_table);