MIPS: Netlogic: Reduce size of reset code

Update thread wakeup function to use scratch registers for saving SP and
RA. Move the register restore code needed for thread 0 to the calling
function. This reduces the size of code copied to the reset vector.

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6910/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/netlogic/common/reset.S b/arch/mips/netlogic/common/reset.S
index b231fe1e7a093c0e9a0296f428a18e51e47e4f20..fda772a8595b5efc190bd2feebe720ca04717d34 100644 (file)
--- a/arch/mips/netlogic/common/reset.S
+++ b/arch/mips/netlogic/common/reset.S
@@ -197,6 +197,9 @@ FEXPORT(nlm_reset_entry)
 EXPORT(nlm_boot_siblings)
        /* core L1D flush before enable threads */
        xlp_flush_l1_dcache
+       /* save ra and sp, will be used later (only for boot cpu) */
+       dmtc0   ra, $22, 6
+       dmtc0   sp, $22, 7
        /* Enable hw threads by writing to MAP_THREADMODE of the core */
        li      t0, CKSEG1ADDR(RESET_DATA_PHYS)
        lw      t1, BOOT_THREAD_MODE(t0)        /* t1 <- thread mode */
@@ -238,14 +241,12 @@ EXPORT(nlm_boot_siblings)
        nop
 
        /*
-        * For the boot CPU, we have to restore registers and
-        * return
+        * For the boot CPU, we have to restore ra and sp and return, rest
+        * of the registers will be restored by the caller
         */
-4:     dmfc0   t0, $4, 2       /* restore SP from UserLocal */
-       li      t1, 0xfadebeef
-       dmtc0   t1, $4, 2       /* restore SP from UserLocal */
-       PTR_SUBU sp, t0, PT_SIZE
-       RESTORE_ALL
+4:
+       dmfc0   ra, $22, 6
+       dmfc0   sp, $22, 7
        jr      ra
        nop
 EXPORT(nlm_reset_entry_end)

diff --git a/arch/mips/netlogic/common/smpboot.S b/arch/mips/netlogic/common/smpboot.S
index 8597657c27fcc05d4f84e84b1616c8c412f942ee..805355b0bd05d4b6d7de3493c2cbf446c737235d 100644 (file)
--- a/arch/mips/netlogic/common/smpboot.S
+++ b/arch/mips/netlogic/common/smpboot.S
@@ -54,8 +54,9 @@
        .set    noat
        .set    arch=xlr                /* for mfcr/mtcr, XLR is sufficient */
 
-FEXPORT(xlp_boot_core0_siblings)       /* "Master" cpu starts from here */
-       dmtc0   sp, $4, 2               /* SP saved in UserLocal */
+/* Called by the boot cpu to wake up its sibling threads */
+NESTED(xlp_boot_core0_siblings, PT_SIZE, sp)
+       /* CPU register contents lost when enabling threads, save them first */
        SAVE_ALL
        sync
        /* find the location to which nlm_boot_siblings was relocated */
@@ -65,9 +66,12 @@ FEXPORT(xlp_boot_core0_siblings)     /* "Master" cpu starts from here */
        dsubu   t2, t1
        daddu   t2, t0
        /* call it */
-       jr      t2
+       jalr    t2
        nop
-       /* not reached */
+       RESTORE_ALL
+       jr      ra
+       nop
+END(xlp_boot_core0_siblings)
 
 NESTED(nlm_boot_secondary_cpus, 16, sp)
        /* Initialize CP0 Status */