Fix a comment typo.

Patch by Johnny Chen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83407 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 9571ecd37a8bd0f73a8b533d9c250f303a93e32f..da048be20caec7cb426926856062a5fbc0036ae0 100644 (file)
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -384,7 +384,7 @@ multiclass AsI1_bin_irs<bits<4> opcod, string opc, PatFrag opnode,
 }
 
 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
-/// instruction modifies the CSPR register.
+/// instruction modifies the CPSR register.
 let Defs = [CPSR] in {
 multiclass AI1_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode,
                          bit Commutable = 0> {