Targets all now request ConstantFP to be legalized into TargetConstantFP.

'fpimm' in .td files is now TargetConstantFP.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25771 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/IA64/IA64ISelDAGToDAG.cpp b/lib/Target/IA64/IA64ISelDAGToDAG.cpp
index 91fff5cea14f93a545975959548fbb9889c2e7d9..072b55b21245fb5351c1af1bb11b5b1957069966 100644 (file)
--- a/lib/Target/IA64/IA64ISelDAGToDAG.cpp
+++ b/lib/Target/IA64/IA64ISelDAGToDAG.cpp
@@ -419,7 +419,7 @@ SDOperand IA64DAGToDAGISel::Select(SDOperand Op) {
   case ISD::SREM:
   case ISD::UREM: return SelectDIV(Op);
  
-  case ISD::ConstantFP: {
+  case ISD::TargetConstantFP: {
     SDOperand Chain = CurDAG->getEntryNode(); // this is a constant, so..
 
     if (cast<ConstantFPSDNode>(N)->isExactlyValue(+0.0))

diff --git a/lib/Target/IA64/IA64ISelLowering.cpp b/lib/Target/IA64/IA64ISelLowering.cpp
index e939fb79b7a0f8aae7ff915ad93139e713c096b4..11b95c4e02e2591baf8900e7103a75f1536da4d1 100644 (file)
--- a/lib/Target/IA64/IA64ISelLowering.cpp
+++ b/lib/Target/IA64/IA64ISelLowering.cpp
@@ -104,6 +104,7 @@ IA64TargetLowering::IA64TargetLowering(TargetMachine &TM)
 
       computeRegisterProperties();
 
+      setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
       addLegalFPImmediate(+0.0);
       addLegalFPImmediate(+1.0);
 }

diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index 48249982b0112586b0ac7b9649ca416fe9610531..83297bada58851591cce111f9a4eb37f185184fb 100644 (file)
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -37,6 +37,9 @@ PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
   addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
   addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
   
+  setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
+  setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
+
   // PowerPC has no intrinsics for these particular operations
   setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
   setOperationAction(ISD::MEMSET, MVT::Other, Expand);

diff --git a/lib/Target/TargetSelectionDAG.td b/lib/Target/TargetSelectionDAG.td
index 9537819aad6727ebb7f56737294a4657f42dc8bd..7e77e839692e7e7537e76d7c1c32c0285852758f 100644 (file)
--- a/lib/Target/TargetSelectionDAG.td
+++ b/lib/Target/TargetSelectionDAG.td
@@ -194,7 +194,8 @@ def node;
 def srcvalue;
 
 def imm        : SDNode<"ISD::Constant"  , SDTIntLeaf , [], "ConstantSDNode">;
-def fpimm      : SDNode<"ISD::ConstantFP", SDTFPLeaf  , [], "ConstantFPSDNode">;
+def fpimm      : SDNode<"ISD::TargetConstantFP",
+                         SDTFPLeaf, [], "ConstantFPSDNode">;
 def vt         : SDNode<"ISD::VALUETYPE" , SDTOther   , [], "VTSDNode">;
 def bb         : SDNode<"ISD::BasicBlock", SDTOther   , [], "BasicBlockSDNode">;
 def cond       : SDNode<"ISD::CONDCODE"  , SDTOther   , [], "CondCodeSDNode">;

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index a2a788733055f25cefeaa6b50b2663a5d9890261..8a8161925b971be5dd81a7f6343c6a3a440e6723 100644 (file)
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -45,7 +45,7 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
   setSchedulingPreference(SchedulingForRegPressure);
   setShiftAmountFlavor(Mask);   // shl X, 32 == shl X, 0
   setStackPointerRegisterToSaveRestore(X86::ESP);
-
+  
   // Set up the register classes.
   addRegisterClass(MVT::i8, X86::R8RegisterClass);
   addRegisterClass(MVT::i16, X86::R16RegisterClass);
@@ -213,6 +213,10 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
     setOperationAction(ISD::FNEG , MVT::f32, Expand);
     setOperationAction(ISD::FREM , MVT::f32, Expand);
 
+    // Expand FP immediates into loads from the stack, except for the special
+    // cases we handle.
+    setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
+    setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
     addLegalFPImmediate(+0.0); // xorps / xorpd
   } else {
     // Set up the FP register classes.
@@ -228,6 +232,7 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
       setOperationAction(ISD::FCOS           , MVT::f64  , Expand);
     }
 
+    setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
     addLegalFPImmediate(+0.0); // FLD0
     addLegalFPImmediate(+1.0); // FLD1
     addLegalFPImmediate(-0.0); // FLD0/FCHS