drm/i915: Fix Ironlake M/N/P ranges to match the spec
authorZhao Yakui <yakui.zhao@intel.com>
Wed, 6 Jan 2010 14:05:57 +0000 (22:05 +0800)
committerEric Anholt <eric@anholt.net>
Thu, 7 Jan 2010 18:26:45 +0000 (10:26 -0800)
Without this fix, some modes couldn't find appropriate clocks.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Tested-by: Matthew Garrett <mjg@redhat.com>
drivers/gpu/drm/i915/intel_display.c

index 0cf44d6e9deb9524c910e028285976f4398c6de7..42e8c031c2ca14c6209e6a493da562c29efefefe 100644 (file)
@@ -241,11 +241,11 @@ struct intel_limit {
 #define IRONLAKE_VCO_MIN         1760000
 #define IRONLAKE_VCO_MAX         3510000
 #define IRONLAKE_N_MIN           1
-#define IRONLAKE_N_MAX           5
+#define IRONLAKE_N_MAX           6
 #define IRONLAKE_M_MIN           79
-#define IRONLAKE_M_MAX           118
+#define IRONLAKE_M_MAX           127
 #define IRONLAKE_M1_MIN          12
-#define IRONLAKE_M1_MAX          23
+#define IRONLAKE_M1_MAX          22
 #define IRONLAKE_M2_MIN          5
 #define IRONLAKE_M2_MAX          9
 #define IRONLAKE_P_SDVO_DAC_MIN  5