[ARM64] Add support for NV condition code (exists only for valid assembly/disassembly...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205864 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp b/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
index 46440a9bee8583f9203cce6f4bd72e426819b64f..524dd12e2809ce2d0ccb4c94ce18656dad3353c5 100644 (file)
--- a/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
+++ b/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
@@ -2188,7 +2188,7 @@ ARM64AsmParser::tryParseFPImm(OperandVector &Operands) {
 
 /// parseCondCodeString - Parse a Condition Code string.
 unsigned ARM64AsmParser::parseCondCodeString(StringRef Cond) {
-  unsigned CC = StringSwitch<unsigned>(Cond)
+  unsigned CC = StringSwitch<unsigned>(Cond.lower())
                     .Case("eq", ARM64CC::EQ)
                     .Case("ne", ARM64CC::NE)
                     .Case("cs", ARM64CC::CS)
@@ -2206,25 +2206,8 @@ unsigned ARM64AsmParser::parseCondCodeString(StringRef Cond) {
                     .Case("gt", ARM64CC::GT)
                     .Case("le", ARM64CC::LE)
                     .Case("al", ARM64CC::AL)
-                // Upper case works too. Not mixed case, though.
-                    .Case("EQ", ARM64CC::EQ)
-                    .Case("NE", ARM64CC::NE)
-                    .Case("CS", ARM64CC::CS)
-                    .Case("HS", ARM64CC::CS)
-                    .Case("CC", ARM64CC::CC)
-                    .Case("LO", ARM64CC::CC)
-                    .Case("MI", ARM64CC::MI)
-                    .Case("PL", ARM64CC::PL)
-                    .Case("VS", ARM64CC::VS)
-                    .Case("VC", ARM64CC::VC)
-                    .Case("HI", ARM64CC::HI)
-                    .Case("LS", ARM64CC::LS)
-                    .Case("GE", ARM64CC::GE)
-                    .Case("LT", ARM64CC::LT)
-                    .Case("GT", ARM64CC::GT)
-                    .Case("LE", ARM64CC::LE)
-                    .Case("AL", ARM64CC::AL)
-                    .Default(~0U);
+                    .Case("nv", ARM64CC::NV)
+                    .Default(ARM64CC::Invalid);
   return CC;
 }
 
@@ -2237,7 +2220,7 @@ bool ARM64AsmParser::parseCondCode(OperandVector &Operands,
 
   StringRef Cond = Tok.getString();
   unsigned CC = parseCondCodeString(Cond);
-  if (CC == ~0U)
+  if (CC == ARM64CC::Invalid)
     return TokError("invalid condition code");
   Parser.Lex(); // Eat identifier token.
 
@@ -3566,7 +3549,7 @@ bool ARM64AsmParser::ParseInstruction(ParseInstructionInfo &Info,
     SMLoc SuffixLoc = SMLoc::getFromPointer(NameLoc.getPointer() +
                                             (Head.data() - Name.data()));
     unsigned CC = parseCondCodeString(Head);
-    if (CC == ~0U)
+    if (CC == ARM64CC::Invalid)
       return Error(SuffixLoc, "invalid condition code");
     const MCExpr *CCExpr = MCConstantExpr::Create(CC, getContext());
     Operands.push_back(

diff --git a/lib/Target/ARM64/MCTargetDesc/ARM64BaseInfo.h b/lib/Target/ARM64/MCTargetDesc/ARM64BaseInfo.h
index d3c2cf7230fb9d82d684c4f93a8052633ec054dd..192082bf25d7d1f6804a1992dff876535f8e3cd6 100644 (file)
--- a/lib/Target/ARM64/MCTargetDesc/ARM64BaseInfo.h
+++ b/lib/Target/ARM64/MCTargetDesc/ARM64BaseInfo.h
@@ -200,14 +200,15 @@ enum CondCode {  // Meaning (integer)          Meaning (floating-point)
   LT = 0xb,      // Less than                  Less than, or unordered
   GT = 0xc,      // Greater than               Greater than
   LE = 0xd,      // Less than or equal         <, ==, or unordered
-  AL = 0xe       // Always (unconditional)     Always (unconditional)
+  AL = 0xe,      // Always (unconditional)     Always (unconditional)
+  NV = 0xf,      // Always (unconditional)     Always (unconditional)
+  // Note the NV exists purely to disassemble 0b1111. Execution is "always".
+  Invalid
 };
 
 inline static const char *getCondCodeName(CondCode Code) {
-  // cond<0> is ignored when cond<3:1> = 111, where 1110 is 0xe (aka AL).
-  if ((Code & AL) == AL)
-    Code = AL;
   switch (Code) {
+  default: llvm_unreachable("Unknown condition code");
   case EQ:  return "eq";
   case NE:  return "ne";
   case CS:  return "cs";
@@ -223,8 +224,8 @@ inline static const char *getCondCodeName(CondCode Code) {
   case GT:  return "gt";
   case LE:  return "le";
   case AL:  return "al";
+  case NV:  return "nv";
   }
-  llvm_unreachable("Unknown condition code");
 }
 
 inline static CondCode getInvertedCondCode(CondCode Code) {

diff --git a/test/MC/ARM64/nv-cond.s b/test/MC/ARM64/nv-cond.s
new file mode 100644 (file)
index 0000000..ded5ec6
--- /dev/null
+++ b/test/MC/ARM64/nv-cond.s
@@ -0,0 +1,11 @@
+// RUN: llvm-mc < %s -triple arm64 -show-encoding | FileCheck %s
+
+fcsel d28,d31,d31,nv
+csel x0,x0,x0,nv
+ccmp x0,x0,#0,nv
+b.nv #0
+
+// CHECK: fcsel   d28, d31, d31, nv       // encoding: [0xfc,0xff,0x7f,0x1e]
+// CHECK: csel    x0, x0, x0, nv          // encoding: [0x00,0xf0,0x80,0x9a]
+// CHECK: ccmp    x0, x0, #0, nv          // encoding: [0x00,0xf0,0x40,0xfa]
+// CHECK: b.nv #0                         // encoding: [0x0f,0x00,0x00,0x54]