; RUN: llc < %s -march=mips -relocation-model=static | FileCheck %s
+; RUN: llc < %s -march=mips -relocation-model=static -regalloc=basic | FileCheck %s
; Fix PR7473
define i32 @main() nounwind readnone {
volatile store i32 0, i32* %c, align 4
%0 = volatile load i32* %a, align 4 ; <i32> [#uses=1]
%1 = icmp eq i32 %0, 0 ; <i1> [#uses=1]
-; CHECK: addiu $4, $zero, 0
+; CHECK: addiu $[[R1:[0-9]+]], $zero, 0
%iftmp.0.0 = select i1 %1, i32 3, i32 0 ; <i32> [#uses=1]
%2 = volatile load i32* %c, align 4 ; <i32> [#uses=1]
%3 = icmp eq i32 %2, 0 ; <i1> [#uses=1]
-; CHECK: addiu $4, $zero, 3
-; CHECK: addu $2, $3, $4
+; CHECK: addiu $[[R1]], $zero, 3
+; CHECK: addu $2, ${{.}}, $[[R1]]
%iftmp.2.0 = select i1 %3, i32 0, i32 5 ; <i32> [#uses=1]
%4 = add nsw i32 %iftmp.2.0, %iftmp.0.0 ; <i32> [#uses=1]
ret i32 %4
; RUN: llc -march=mipsel -mcpu=mips2 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mcpu=mips2 < %s -regalloc=basic | FileCheck %s
; All test functions do the same thing - they return the first variable
; CHECK: va2:
; CHECK: addiu $sp, $sp, -40
-; CHECK: addiu $2, $sp, 44
+; CHECK: addiu $[[R0:[0-9]+]], $sp, 44
; CHECK: sw $5, 44($sp)
; CHECK: sw $6, 48($sp)
; CHECK: sw $7, 52($sp)
-; CHECK: addiu $3, $2, 7
-; CHECK: addiu $5, $zero, -8
-; CHECK: and $3, $3, $5
-; CHECK: ldc1 $f0, 0($3)
+; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7
+; CHECK: addiu $[[R2:[0-9]+]], $zero, -8
+; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]]
+; CHECK: ldc1 $f0, 0($[[R3]])
}
; int
; CHECK: addiu $sp, $sp, -48
; CHECK: sw $6, 56($sp)
; CHECK: sw $7, 60($sp)
-; CHECK: addiu $3, $sp, 56
-; CHECK: addiu $6, $3, 7
-; CHECK: addiu $7, $zero, -8
-; CHECK: and $2, $6, $7
-; CHECK: ldc1 $f0, 0($2)
+; CHECK: addiu $[[R0:[0-9]+]], $sp, 56
+; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7
+; CHECK: addiu $[[R2:[0-9]+]], $zero, -8
+; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]]
+; CHECK: ldc1 $f0, 0($[[R3]])
}
; int
; CHECK: va6:
; CHECK: addiu $sp, $sp, -48
; CHECK: sw $7, 60($sp)
-; CHECK: addiu $2, $sp, 60
-; CHECK: addiu $3, $2, 7
-; CHECK: addiu $4, $zero, -8
-; CHECK: and $3, $3, $4
-; CHECK: ldc1 $f0, 0($3)
+; CHECK: addiu $[[R0:[0-9]+]], $sp, 60
+; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7
+; CHECK: addiu $[[R2:[0-9]+]], $zero, -8
+; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]]
+; CHECK: ldc1 $f0, 0($[[R3]])
}
; int
; CHECK: va8:
; CHECK: addiu $sp, $sp, -48
-; CHECK: addiu $3, $sp, 64
-; CHECK: addiu $4, $3, 7
-; CHECK: addiu $5, $zero, -8
-; CHECK: and $2, $4, $5
-; CHECK: ldc1 $f0, 0($2)
+; CHECK: addiu $[[R0:[0-9]+]], $sp, 64
+; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7
+; CHECK: addiu $[[R2:[0-9]+]], $zero, -8
+; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]]
+; CHECK: ldc1 $f0, 0($[[R3]])
}
; int
; CHECK: va10:
; CHECK: addiu $sp, $sp, -56
-; CHECK: addiu $3, $sp, 76
-; CHECK: addiu $2, $3, 7
-; CHECK: addiu $4, $zero, -8
-; CHECK: and $2, $2, $4
-; CHECK: ldc1 $f0, 0($2)
+; CHECK: addiu $[[R0:[0-9]+]], $sp, 76
+; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7
+; CHECK: addiu $[[R2:[0-9]+]], $zero, -8
+; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]]
+; CHECK: ldc1 $f0, 0($[[R3]])
}
; RUN: llc < %s -march=xcore | FileCheck %s
+; RUN: llc < %s -march=xcore -regalloc=basic | FileCheck %s
define i64 @umul_lohi(i32 %a, i32 %b) {
entry:
%0 = zext i32 %a to i64
ret i64 %2
}
; CHECK: umul_lohi:
-; CHECK: ldc r2, 0
-; CHECK-NEXT: lmul r1, r0, r1, r0, r2, r2
+; CHECK: ldc [[REG:r[0-9]+]], 0
+; CHECK-NEXT: lmul r1, r0, r1, r0, [[REG]], [[REG]]
; CHECK-NEXT: retsp 0
define i64 @smul_lohi(i32 %a, i32 %b) {
ret i64 %2
}
; CHECK: smul_lohi:
-; CHECK: ldc r2, 0
-; CHECK-NEXT: mov r3, r2
-; CHECK-NEXT: maccs r2, r3, r1, r0
-; CHECK-NEXT: mov r0, r3
-; CHECK-NEXT: mov r1, r2
+; CHECK: ldc
+; CHECK-NEXT: mov
+; CHECK-NEXT: maccs
+; CHECK-NEXT: mov r0,
+; CHECK-NEXT: mov r1,
; CHECK-NEXT: retsp 0
define i64 @mul64(i64 %a, i64 %b) {
ret i64 %0
}
; CHECK: mul64:
-; CHECK: ldc r11, 0
-; CHECK-NEXT: lmul r11, r4, r0, r2, r11, r11
-; CHECK-NEXT: mul r0, r0, r3
-; CHECK-NEXT: lmul r0, r1, r1, r2, r11, r0
-; CHECK-NEXT: mov r0, r4
+; CHECK: ldc
+; CHECK-NEXT: lmul
+; CHECK-NEXT: mul
+; CHECK-NEXT: lmul
+; CHECK-NEXT: mov r0,
define i64 @mul64_2(i64 %a, i32 %b) {
entry:
ret i64 %1
}
; CHECK: mul64_2:
-; CHECK: ldc r3, 0
-; CHECK-NEXT: lmul r3, r0, r0, r2, r3, r3
-; CHECK-NEXT: mul r1, r1, r2
-; CHECK-NEXT: add r1, r3, r1
+; CHECK: ldc
+; CHECK-NEXT: lmul
+; CHECK-NEXT: mul
+; CHECK-NEXT: add r1,
; CHECK-NEXT: retsp 0