3288: i2c & adc dts update

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index b1c0cafa027f5b36d578eae4737c8a4670d145e8..218550ec313ed139470348d62ca8af41ffd25c0e 100755 (executable)
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -94,99 +94,114 @@
 
 
 
-       i2c0: i2c@2002d000 {
+       i2c0: i2c@ff650000 {
                compatible = "rockchip,rk30-i2c";
-               reg = <0x2002d000 0x1000>;
-               interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+               reg = <0xff650000 0x1000>;
+               interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
                #address-cells = <1>;
                #size-cells = <0>;
-               pinctrl-names = "default", "gpio";
-               pinctrl-0 = <&i2c0_sda &i2c0_scl>;
-               pinctrl-1 = <&i2c0_gpio>;
-               gpios = <&gpio1 GPIO_D0 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D1 GPIO_ACTIVE_LOW>;
-               clocks = <&clk_gates8 4>;
+               //pinctrl-names = "default", "gpio";
+               //pinctrl-0 = <&i2c0_sda &i2c0_scl>;
+               //pinctrl-1 = <&i2c0_gpio>;
+               //gpios = <&gpio0 GPIO_B7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_C0 GPIO_ACTIVE_LOW>;
+               //clocks = <&clk_gates8 4>;
                rockchip,check-idle = <1>;
                status = "disabled";
        };
 
-       i2c1: i2c@2002f000 {
+       i2c1: i2c@ff140000 {
                compatible = "rockchip,rk30-i2c";
-               reg = <0x2002f000 0x1000>;
-               interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+               reg = <0xff140000 0x1000>;
+               interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
                #address-cells = <1>;
                #size-cells = <0>;
-               pinctrl-names = "default", "gpio";
-               pinctrl-0 = <&i2c1_sda &i2c1_scl>;
-               pinctrl-1 = <&i2c1_gpio>;
-               gpios = <&gpio1 GPIO_D2 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D3 GPIO_ACTIVE_LOW>;
-               clocks = <&clk_gates8 5>;
-               rockchip,check-idle = <1>;
-               status = "disabled";
+               //pinctrl-names = "default", "gpio";
+               //pinctrl-0 = <&i2c1_sda &i2c1_scl>;
+               //pinctrl-1 = <&i2c1_gpio>;
+               //gpios = <&gpio8 GPIO_A4 GPIO_ACTIVE_LOW>, <&gpio8 GPIO_A5 GPIO_ACTIVE_LOW>;
+               //clocks = <&clk_gates8 5>;
+          rockchip,check-idle = <1>;   
+      status = "disabled";
+
+
        };
 
-       i2c2: i2c@20056000 {
+       i2c2: i2c@ff660000 {
                compatible = "rockchip,rk30-i2c";
-               reg = <0x20056000 0x1000>;
-               interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+               reg = <0xff660000 0x1000>;
+               interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
                #address-cells = <1>;
                #size-cells = <0>;
-               pinctrl-names = "default", "gpio";
-               pinctrl-0 = <&i2c2_sda &i2c2_scl>;
-               pinctrl-1 = <&i2c2_gpio>;
-               gpios = <&gpio1 GPIO_D4 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D5 GPIO_ACTIVE_LOW>;
-               clocks = <&clk_gates8 6>;
+               //pinctrl-names = "default", "gpio";
+               //pinctrl-0 = <&i2c2_sda &i2c2_scl>;
+               //pinctrl-1 = <&i2c2_gpio>;
+               //gpios = <&gpio6 GPIO_B1 GPIO_ACTIVE_LOW>, <&gpio6 GPIO_B2 GPIO_ACTIVE_LOW>;
+               //clocks = <&clk_gates8 6>;
                rockchip,check-idle = <1>;
                status = "disabled";
        };
 
-       i2c3: i2c@2005a000 {
+       i2c3: i2c@ff150000 {
                compatible = "rockchip,rk30-i2c";
-               reg = <0x2005a000 0x1000>;
-               interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+               reg = <0xff150000 0x1000>;
+               interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
                #address-cells = <1>;
                #size-cells = <0>;
-               pinctrl-names = "default", "gpio";
-               pinctrl-0 = <&i2c3_sda &i2c3_scl>;
-               pinctrl-1 = <&i2c3_gpio>;
-               gpios = <&gpio3 GPIO_B6 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_B7 GPIO_ACTIVE_LOW>;
-               clocks = <&clk_gates8 7>;
+               //pinctrl-names = "default", "gpio";
+               //pinctrl-0 = <&i2c2_sda &i2c2_scl>;
+               //pinctrl-1 = <&i2c2_gpio>;
+               //gpios = <&gpio2 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C0 GPIO_ACTIVE_LOW>;
+               //clocks = <&clk_gates8 6>;
                rockchip,check-idle = <1>;
                status = "disabled";
        };
 
-       i2c4: i2c@2005e000 {
+       i2c4: i2c@ff160000 {
                compatible = "rockchip,rk30-i2c";
-               reg = <0x2005e000 0x1000>;
-               interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+               reg = <0xff160000 0x1000>;
+               interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
                #address-cells = <1>;
                #size-cells = <0>;
-               pinctrl-names = "default", "gpio";
-               pinctrl-0 = <&i2c4_sda &i2c4_scl>;
-               pinctrl-1 = <&i2c4_gpio>;
-               gpios = <&gpio1 GPIO_D6 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D7 GPIO_ACTIVE_LOW>;
-               clocks = <&clk_gates8 8>;
+               //pinctrl-names = "default", "gpio";
+               //pinctrl-0 = <&i2c3_sda &i2c3_scl>;
+               //pinctrl-1 = <&i2c3_gpio>;
+               //gpios = <&gpio7 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C2 GPIO_ACTIVE_LOW>;
+               //clocks = <&clk_gates8 7>;
                rockchip,check-idle = <1>;
                status = "disabled";
        };
 
-    adc: adc@2006c000 {
-          compatible = "rockchip,saradc";
-          reg = <0x2006c000 0x100>;
-          interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
-           #io-channel-cells = <1>;
-          io-channel-ranges;
-           rockchip,adc-vref = <1800>;
-           clock-frequency = <1000000>;
-           clocks = <&clk_saradc>, <&clk_gates7 14>;
-           clock-names = "saradc", "pclk_saradc"; 
-           status = "disabled";
+   i2c5: i2c@ff170000 {
+       compatible = "rockchip,rk30-i2c";
+       reg = <0xff170000 0x1000>;
+       interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+       #address-cells = <1>;
+       #size-cells = <0>;
+               //pinctrl-names = "default", "gpio";
+               //pinctrl-0 = <&i2c4_sda &i2c4_scl>;
+               //pinctrl-1 = <&i2c4_gpio>;
+               //gpios = <&gpio7 GPIO_C3 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C4 GPIO_ACTIVE_LOW>;
+               //clocks = <&clk_gates8 8>;
+       rockchip,check-idle = <1>;
+       status = "disabled";
+    };
+
+    adc: adc@ff100000 {
+        compatible = "rockchip,saradc";
+        reg = <0xff100000 0x100>;
+        interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+        #io-channel-cells = <1>;
+        io-channel-ranges;
+        rockchip,adc-vref = <1800>;
+        clock-frequency = <1000000>;
+        clock-names = "saradc", "pclk_saradc"; 
+        status = "disabled";
     };
        
        rga@ff930000 {
                compatible = "rockchip,rga";
                reg = <0xff930000 0x1000>;
                interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&clk_gates6 10>, <&clk_gates6 11>;
     clock-names = "hclk_rga", "aclk_rga"; 
                status = "disabled";
         };