ARM: shmobile: Initial Alt board device tree
authorUlrich Hecht <ulrich.hecht+renesas@gmail.com>
Fri, 5 Sep 2014 10:23:49 +0000 (12:23 +0200)
committerSimon Horman <horms+renesas@verge.net.au>
Tue, 9 Sep 2014 02:29:27 +0000 (11:29 +0900)
Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
[uli: reduced to minimum, added cmt, enabled scif2, split off from SoC]
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
arch/arm/boot/dts/Makefile
arch/arm/boot/dts/r8a7794-alt.dts [new file with mode: 0644]

index b8c5cd3ddeb9c0f10e18cff41f8b0aaf33396765..81c1df94f2f30c65e7c2156b927ae2b1794bcee6 100644 (file)
@@ -375,7 +375,8 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb \
        r8a7791-henninger.dtb \
        r8a7791-koelsch.dtb \
        r8a7790-lager.dtb \
-       r8a7779-marzen.dtb
+       r8a7779-marzen.dtb \
+       r8a7794-alt.dtb
 dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \
        socfpga_cyclone5_socdk.dtb \
        socfpga_cyclone5_sockit.dtb \
diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts
new file mode 100644 (file)
index 0000000..79d06ef
--- /dev/null
@@ -0,0 +1,47 @@
+/*
+ * Device Tree Source for the Alt board
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/dts-v1/;
+#include "r8a7794.dtsi"
+
+/ {
+       model = "Alt";
+       compatible = "renesas,alt", "renesas,r8a7794";
+
+       aliases {
+               serial0 = &scif2;
+       };
+
+       chosen {
+               bootargs = "console=ttySC0,38400 ignore_loglevel rw root=/dev/nfs ip=dhcp";
+       };
+
+       memory@40000000 {
+               device_type = "memory";
+               reg = <0 0x40000000 0 0x40000000>;
+       };
+
+       lbsc {
+               #address-cells = <1>;
+               #size-cells = <1>;
+       };
+};
+
+&extal_clk {
+       clock-frequency = <20000000>;
+};
+
+&cmt0 {
+       status = "ok";
+};
+
+&scif2 {
+       status = "ok";
+};