Revert "[ARM] Add more pattern matching for f16 <-> f64 conversions"

This change is incorrect since it converts double rounding into single rounding,
which can produce different results. Instead this optimization will be done by
modifying Clang's codegen to not produce double rounding in the first place.

This reverts commit r232954.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232962 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMInstrVFP.td b/lib/Target/ARM/ARMInstrVFP.td
index dba95f9e56d2b4f62ce7b610bb5006d72a89df15..afff01692a2df0304e6d447fd167536f436c8b8a 100644 (file)
--- a/lib/Target/ARM/ARMInstrVFP.td
+++ b/lib/Target/ARM/ARMInstrVFP.td
@@ -621,14 +621,6 @@ def : Pat<(f16_to_fp GPR:$a),
 def : Pat<(f64 (f16_to_fp GPR:$a)),
           (VCVTBHD (COPY_TO_REGCLASS GPR:$a, SPR))>;
 
-def : Pat<(f64 (fextend (f16_to_fp GPR:$a))),
-          (VCVTBHD (COPY_TO_REGCLASS GPR:$a, SPR))>,
-          Requires<[HasFPARMv8, HasDPVFP]>;
-
-def : Pat<(fp_to_f16 (fround (f64 DPR:$a))),
-          (i32 (COPY_TO_REGCLASS (VCVTBDH DPR:$a), GPR))>,
-          Requires<[HasFPARMv8, HasDPVFP]>;
-
 multiclass vcvt_inst<string opc, bits<2> rm,
                      SDPatternOperator node = null_frag> {
   let PostEncoderMethod = "", DecoderNamespace = "VFPV8" in {

diff --git a/test/CodeGen/ARM/fp16-64.ll b/test/CodeGen/ARM/fp16-64.ll
deleted file mode 100644 (file)
index 854ba9a..0000000
--- a/test/CodeGen/ARM/fp16-64.ll
+++ /dev/null
@@ -1,31 +0,0 @@
-; RUN: llc -mtriple=arm -mattr=+fp-armv8 < %s | \
-; RUN:   FileCheck --check-prefix=CHECK --check-prefix=V8 %s
-; RUN: llc -mtriple=arm -mattr=+vfp3,+d16 < %s | \
-; RUN:   FileCheck --check-prefix=CHECK --check-prefix=NOV8 %s
-
-declare float @llvm.convert.from.fp16.f32(i16) nounwind readnone
-declare i16 @llvm.convert.to.fp16.f32(float) nounwind readnone
-
-define void @vcvt_f64_f16(i16* %x, double* %y) nounwind {
-entry:
-; CHECK-LABEL: vcvt_f64_f16
-  %0 = load i16, i16* %x, align 2
-  %1 = tail call float @llvm.convert.from.fp16.f32(i16 %0)
-  %conv = fpext float %1 to double
-; CHECK-V8: vcvtb.f64.f16
-; CHECK-NOV8-NOT: vcvtb.f64.f16
-  store double %conv, double* %y, align 8
-  ret void
-}
-
-define void @vcvt_f16_f64(i16* %x, double* %y) nounwind {
-entry:
-; CHECK-LABEL: vcvt_f16_f64
-  %0 = load double, double* %y, align 8
-  %conv = fptrunc double %0 to float
-; CHECK-V8: vcvtb.f16.f64
-; CHECK-NOV8-NOT: vcvtb.f16.f64
-  %1 = tail call i16 @llvm.convert.to.fp16.f32(float %conv)
-  store i16 %1, i16* %x, align 2
-  ret void
-}