soc: rockchip: support rk3288 pm config

Change-Id: Icbd23af68bdf7a4fcad59a5d227988a13b2873af
Signed-off-by: shengfei Xu <xsf@rock-chips.com>

diff --git a/Documentation/devicetree/bindings/soc/rockchip/rockchip-pm-config.txt b/Documentation/devicetree/bindings/soc/rockchip/rockchip-pm-config.txt
index 4dc1d02a15db0c15aaefdf35ee2a2d7a879251c1..9d3a9f548f33313b05cae5390bd280a754e3d213 100644 (file)
--- a/Documentation/devicetree/bindings/soc/rockchip/rockchip-pm-config.txt
+++ b/Documentation/devicetree/bindings/soc/rockchip/rockchip-pm-config.txt
@@ -2,6 +2,7 @@
 
 Required properties:
 - compatible: Should be one of the following.
+- "rockchip,pm-rk3288" - for RK3288 SOCs.
 - "rockchip,pm-rk3368" - for RK3368 SoCs.
 - "rockchip,pm-rk3399" - for RK3399 SoCs.
 
@@ -14,6 +15,29 @@ Required properties:
 - rockchip,pwm-regulator-config: the pwm regulator name.
 
 Example:
+       rockchip_suspend: rockchip-suspend {
+               compatible = "rockchip,pm-rk3288";
+               status = "disabled";
+               rockchip,sleep-mode-config = <
+                       (0
+                       |RKPM_CTR_PWR_DMNS
+                       |RKPM_CTR_GTCLKS
+                       |RKPM_CTR_PLLS
+                       |RKPM_CTR_ARMOFF_LPMD
+                       )
+               >;
+               rockchip,wakeup-config = <
+                       (0
+                       | RKPM_GPIO_WKUP_EN
+                       )
+               >;
+               rockchip,pwm-regulator-config = <
+                       (0
+                       | PWM2_REGULATOR_EN
+                       )
+               >;
+       };
+
        rockchip_suspend: rockchip-suspend {
                compatible = "rockchip,pm-rk3368";
                status = "disabled";
@@ -53,4 +77,4 @@ Example:
                        PWM2_REGULATOR_EN
                        )
                >;
-       };
\ No newline at end of file
+       };

diff --git a/drivers/soc/rockchip/rockchip_pm_config.c b/drivers/soc/rockchip/rockchip_pm_config.c
index 038695ff97e4ace1deb9b081558aee45b39d4896..a2338d94407eb13dc3e84c7993fe34ae80c7ae75 100644 (file)
--- a/drivers/soc/rockchip/rockchip_pm_config.c
+++ b/drivers/soc/rockchip/rockchip_pm_config.c
@@ -21,6 +21,7 @@
 #define PM_INVALID_GPIO        0xffff
 
 static const struct of_device_id pm_match_table[] = {
+       { .compatible = "rockchip,pm-rk3288",},
        { .compatible = "rockchip,pm-rk3368",},
        { .compatible = "rockchip,pm-rk3399",},
        { },

diff --git a/include/dt-bindings/suspend/rockchip-rk3288.h b/include/dt-bindings/suspend/rockchip-rk3288.h
new file mode 100644 (file)
index 0000000..d07cced
--- /dev/null
+++ b/include/dt-bindings/suspend/rockchip-rk3288.h
@@ -0,0 +1,59 @@
+/*
+ * Header providing constants for Rockchip suspend bindings.
+ *
+ * Copyright (C) 2017, Fuzhou Rockchip Electronics Co., Ltd
+ * Author: Power.xu
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __DT_BINDINGS_SUSPEND_ROCKCHIP_RK3288_H__
+#define __DT_BINDINGS_SUSPEND_ROCKCHIP_RK3288_H__
+
+/* the suspend mode */
+#define        RKPM_CTR_PWR_DMNS               (1 << 0)
+#define RKPM_CTR_GTCLKS                        (1 << 1)
+#define RKPM_CTR_PLLS                  (1 << 2)
+#define RKPM_CTR_VOLTS                 (1 << 3)
+#define RKPM_CTR_GPIOS                 (1 << 4)
+#define RKPM_CTR_DDR                   (1 << 5)
+#define RKPM_CTR_PMIC                  (1 << 6)
+/* system clk is 24M,and div to min */
+#define RKPM_CTR_SYSCLK_DIV            (1 << 7)
+/* switch sysclk to 32k, need hardwart support, and div to min */
+#define RKPM_CTR_SYSCLK_32K            (1 << 8)
+/* switch sysclk to 32k,disable 24M OSC,
+ * need hardwart susport. and div to min
+ */
+#define RKPM_CTR_SYSCLK_OSC_DIS                (1 << 9)
+#define RKPM_CTR_BUS_IDLE              (1 << 14)
+#define RKPM_CTR_SRAM                  (1 << 15)
+/*Low Power Function Selection*/
+#define RKPM_CTR_IDLESRAM_MD           (1 << 16)
+#define RKPM_CTR_IDLEAUTO_MD           (1 << 17)
+#define RKPM_CTR_ARMDP_LPMD            (1 << 18)
+#define RKPM_CTR_ARMOFF_LPMD           (1 << 19)
+#define RKPM_CTR_ARMLOGDP_LPMD         (1 << 20)
+#define RKPM_CTR_ARMOFF_LOGDP_LPMD     (1 << 21)
+#define RKPM_CTR_ARMLOGOFF_DLPMD       (1 << 22)
+
+/* the wake up source */
+#define RKPM_ARMINT_WKUP_EN            (1 << 0)
+#define RKPM_SDMMC_WKUP_EN             (1 << 2)
+#define RKPM_GPIO_WKUP_EN              (1 << 3)
+
+/* the pwm regulator */
+#define PWM0_REGULATOR_EN              (1 << 0)
+#define PWM1_REGULATOR_EN              (1 << 1)
+#define PWM2_REGULATOR_EN              (1 << 2)
+#define PWM3_REGULATOR_EN              (1 << 3)
+
+#endif