Fix a latent bug exposed by my truncstore patch. We compiled stfiwx-2.ll to:

_test:
	fctiwz f0, f1
	stfiwx f0, 0, r4
	blr

instead of:

_test:
	fctiwz f0, f1
	stfd f0, -8(r1)
	nop
	nop
	lwz r2, -4(r1)
	stb r2, 0(r4)
	blr

The former is not correct (stores 4 bytes, not 1).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46161 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index 6a35bafaf4a4fe6c76977f75154a83f4086d0af1..32feb05ae8d5c5420710070f39d41b74bcfc0f8d 100644 (file)
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -3184,6 +3184,7 @@ SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N,
   case ISD::STORE:
     // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
     if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
+        !cast<StoreSDNode>(N)->isTruncatingStore() &&
         N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
         N->getOperand(1).getValueType() == MVT::i32 &&
         N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {

diff --git a/test/CodeGen/PowerPC/stfiwx-2.ll b/test/CodeGen/PowerPC/stfiwx-2.ll
new file mode 100644 (file)
index 0000000..5c4a834
--- /dev/null
+++ b/test/CodeGen/PowerPC/stfiwx-2.ll
@@ -0,0 +1,11 @@
+; This cannot be a stfiwx
+; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | grep stb
+; RUN: llvm-as < %s | llc -march=ppc32 -mcpu=g5 | not grep stfiwx
+
+define void @test(float %F, i8* %P) {
+       %I = fptosi float %F to i32
+       %X = trunc i32 %I to i8
+       store i8 %X, i8* %P
+       ret void
+}
+