static inline void rk_timer_disable(void __iomem *base)
{
writel_relaxed(TIMER_DISABLE, base + TIMER_CONTROL_REG);
- dsb();
+ dsb(sy);
}
static inline void rk_timer_enable(void __iomem *base, u32 flags)
{
writel_relaxed(TIMER_ENABLE | flags, base + TIMER_CONTROL_REG);
- dsb();
+ dsb(sy);
}
static inline u32 rk_timer_read_current_value(void __iomem *base)
rk_timer_disable(base);
writel_relaxed(cycles, base + TIMER_LOAD_COUNT0);
writel_relaxed(0, base + TIMER_LOAD_COUNT1);
- dsb();
+ dsb(sy);
rk_timer_enable(base, TIMER_MODE_USER_DEFINED_COUNT | TIMER_INT_UNMASK);
return 0;
}
case CLOCK_EVT_MODE_PERIODIC:
rk_timer_disable(base);
writel_relaxed(24000000 / HZ - 1, base + TIMER_LOAD_COUNT0);
- dsb();
+ dsb(sy);
rk_timer_enable(base, TIMER_MODE_FREE_RUNNING | TIMER_INT_UNMASK);
case CLOCK_EVT_MODE_RESUME:
case CLOCK_EVT_MODE_ONESHOT:
if (ce->mode == CLOCK_EVT_MODE_ONESHOT) {
writel_relaxed(TIMER_DISABLE, base + TIMER_CONTROL_REG);
}
- dsb();
+ dsb(sy);
ce->event_handler(ce);
rk_timer_disable(base);
writel_relaxed(0xFFFFFFFF, base + TIMER_LOAD_COUNT0);
writel_relaxed(0xFFFFFFFF, base + TIMER_LOAD_COUNT1);
- dsb();
+ dsb(sy);
rk_timer_enable(base, TIMER_MODE_FREE_RUNNING | TIMER_INT_MASK);
clocksource_register_hz(cs, 24000000);
}