<&clk_l2ram>, <&aclk_core_m0>,
<&aclk_core_mp>, <&atclk_core>,
- <&pclk_dbg_src>, <&clk_gates12 8>,
- <&clk_gates12 8>, <&clk_gates12 8>,
+ <&pclk_dbg_src>, <&pclk_dbg_src>,
+ <&pclk_dbg_src>, <&pclk_dbg_src>,
<&dummy>, <&dummy>,
<&dummy>, <&dummy>;
"clk_l2ram", "aclk_core_m0",
"aclk_core_mp", "atclk_core",
- "pclk_dbg_src", "reserved", /*"g_dbg_core_clk",*/
- "reserved", "reserved", /*"g_cs_dbg_clk", "g_pclk_core_niu",*/
+ "pclk_dbg_src", "g_dbg_core_clk",
+ "g_cs_dbg_clk", "g_pclk_core_niu",
"reserved", "reserved",
"reserved", "reserved";
<&clk_core3>, <&clk_l2ram>,
<&aclk_core_m0>, <&aclk_core_mp>,
<&atclk_core>, <&pclk_dbg_src>,
+ <&clk_gates12 9>, <&clk_gates12 10>,
+ <&clk_gates12 11>,
/*PD_BUS*/
<&aclk_bus>, <&clk_gates0 3>,
#endif
}
+bool rockchip_jtag_enabled = false;
+static int __init rockchip_jtag_enable(char *__unused)
+{
+ rockchip_jtag_enabled = true;
+ printk("rockchip jtag enabled\n");
+ return 1;
+}
+__setup("rockchip_jtag", rockchip_jtag_enable);
{
int ret;
- rk3288_cpuidle_driver.states[0].enter = rk3288_cpuidle_enter;
+ if (!rockchip_jtag_enabled)
+ rk3288_cpuidle_driver.states[0].enter = rk3288_cpuidle_enter;
ret = cpuidle_register(&rk3288_cpuidle_driver, NULL);
if (ret)
pr_err("%s: failed to register cpuidle driver: %d\n", __func__, ret);
#ifdef CONFIG_CPU_IDLE
rk3288_init_cpuidle();
#endif
+ if (rockchip_jtag_enabled)
+ clk_prepare_enable(clk_get_sys(NULL, "clk_jtag"));
}
DT_MACHINE_START(RK3288_DT, "Rockchip RK3288 (Flattened Device Tree)")
.type = MT_DEVICE, \
}
+extern bool rockchip_jtag_enabled;
extern unsigned long rockchip_boot_fn;
extern struct smp_operations rockchip_smp_ops;