}\r
\r
\r
-\r
-\r
-u32\r
-RGA_dst_act_addr_temp(const struct rga_req *msg)\r
-{\r
- uint32_t pw;\r
- uint32_t x_off, y_off;\r
- uint32_t stride;\r
- uint32_t p;\r
- \r
- pw = RGA_pixel_width_init(msg->dst.format);\r
- stride = (msg->dst.vir_w * pw + 3) & (~3); \r
- \r
- x_off = msg->dst.x_offset;\r
- y_off = msg->dst.y_offset;\r
-\r
- p = (u32)((stride * y_off) + (x_off * pw));\r
-\r
- return p;\r
-}\r
-\r
-void\r
-RGA_set_cmd_info(uint8_t cmd_mode, uint32_t cmd_addr)\r
-{\r
- uint32_t reg = 0;\r
- \r
- reg |= ((cmd_mode & 1) << 1);\r
- rRGA_SYS_CTRL = reg; \r
- rRGA_CMD_ADDR = cmd_addr;\r
-}\r
-\r
-void\r
-RGA_start(void) \r
-{\r
- uint32_t reg = 0;\r
- uint8_t cmd_mode;\r
- \r
- reg = rRGA_SYS_CTRL;\r
- cmd_mode = (reg >> 2) & 1;\r
- \r
- if (cmd_mode == 0)\r
- {\r
- /* passive */\r
- reg |= (1<<1);\r
- rRGA_SYS_CTRL = reg; \r
- }\r
- else\r
- {\r
- /* master */\r
- reg = rRGA_CMD_CTRL;\r
- reg |= 1;\r
- rRGA_CMD_CTRL = reg; \r
- } \r
-}\r
-\r
-\r
-void\r
-RGA_soft_reset(void)\r
-{\r
- uint32_t reg = 0;\r
-\r
- reg = rRGA_SYS_CTRL;\r
- reg |= 1;\r
- rRGA_SYS_CTRL = reg; \r
-}\r
-\r
-\r
-#if 0\r
-/*****************************************/\r
-//hxx add,2011.6.24\r
-void rga_one_op_st_master(RGA_INFO *p_rga_info)\r
-{\r
- rRGA_SYS_CTRL = 0x4;\r
- \r
- rRGA_INT = s_RGA_INT_ALL_CMD_DONE_INT_EN(p_rga_info->int_info.all_cmd_done_int_en)|\r
- s_RGA_INT_MMU_INT_EN(p_rga_info->int_info.mmu_int_en)|\r
- s_RGA_INT_ERROR_INT_EN(p_rga_info->int_info.error_int_en);\r
- \r
- rRGA_CMD_ADDR = (u32) p_rga_info->sys_info.p_cmd_mst;\r
- \r
- rRGA_CMD_CTRL = 0x3;\r
-}\r
-\r
-\r
-void rga_set_int_info(MSG *p_msg,RGA_INFO *p_rga_info)\r
-{\r
- p_msg->CMD_fin_int_enable = p_rga_info->int_info.cur_cmd_done_int_en;\r
-}\r
-\r
-\r
-void rga_check_int_all_cmd_finish(RGA_INFO *p_rga_info)\r
-{\r
- u8 int_flag;\r
- \r
- int_flag = 0;\r
- while(!int_flag)\r
- {\r
- int_flag = rRGA_INT & m_RGA_INT_ALL_CMD_DONE_INT_FLAG;\r
- }\r
- rRGA_INT = rRGA_INT | s_RGA_INT_ALL_CMD_DONE_INT_CLEAR(0x1);\r
- \r
- //if(p_rga_info->sys_info.p_cmd_mst != NULL)\r
- // free(p_rga_info->sys_info.p_cmd_mst);\r
-}\r
-#endif\r
-\r
-void rga_start_cmd_AXI(uint8_t *base, uint32_t num)\r
-{\r
- rRGA_SYS_CTRL = 0x4;\r
- rRGA_INT = s_RGA_INT_ALL_CMD_DONE_INT_EN(ENABLE)| s_RGA_INT_MMU_INT_EN(ENABLE)| s_RGA_INT_ERROR_INT_EN(ENABLE);\r
- rRGA_CMD_ADDR = (u32)base; \r
- rRGA_CMD_CTRL |= (num<<3); \r
- rRGA_CMD_CTRL |= 0x3;\r
-}\r
-\r
-void rga_check_cmd_finish(void)\r
-{\r
- uint8_t int_flag;\r
- uint8_t error_flag;\r
- \r
- int_flag = 0;\r
- error_flag = 0;\r
- \r
- while(!int_flag)\r
- {\r
- int_flag = rRGA_INT & m_RGA_INT_ALL_CMD_DONE_INT_FLAG;\r
- error_flag = rRGA_INT & (m_RGA_INT_ERROR_INT_FLAG);\r
-\r
- if(error_flag)\r
- { \r
- printk("~~~~~ ERROR INTTUR OCCUR ~~~~~\n");\r
- }\r
- error_flag = rRGA_INT & m_RGA_INT_MMU_INT_FLAG;\r
- if(error_flag)\r
- { \r
- printk("~~~~~ MMU ERROR INTTUR OCCUR ~~~~~\n");\r
- }\r
- }\r
- rRGA_INT = rRGA_INT | s_RGA_INT_ALL_CMD_DONE_INT_CLEAR(0x1); \r
-}\r
-\r
-\r
-\r
-void rga_start_cmd_AHB(uint8_t *base)\r
-{\r
- uint32_t *base_p32;\r
- \r
- base_p32 = (u32 *)base;\r
- *base_p32 = (*base_p32 | (1<<29));\r
-\r
- memcpy((u8 *)(RGA_BASE + 0x100), base, 28*4);\r
- \r
- rRGA_SYS_CTRL = 0x2;\r
-}\r
-\r
-\r
-void rga_check_cmd_AHB_finish(void)\r
-{\r
- uint8_t int_flag;\r
- \r
- int_flag = 0;\r
- while(!int_flag)\r
- {\r
- int_flag = rRGA_INT & m_RGA_INT_NOW_CMD_DONE_INT_FLAG;\r
- }\r
- rRGA_INT = rRGA_INT | s_RGA_INT_NOW_CMD_DONE_INT_CLEAR(0x1);\r
-}\r
-\r
-\r
-\r
uint32_t RGA_gen_two_pro(struct rga_req *msg, struct rga_req *msg1)\r
{\r
\r
w_ratio = (msg->src.act_w << 16) / msg->dst.act_w;\r
h_ratio = (msg->src.act_h << 16) / msg->dst.act_h;\r
\r
- memcpy(&mp->src, &msg->src, sizeof(rga_img_info_t));\r
+ memcpy(&msg1, &msg, sizeof(struct rga_req));\r
\r
- mp->dst.format = msg->src.format;\r
+ msg->dst.format = msg->src.format;\r
\r
/*pre_scale_w cal*/\r
if ((w_ratio >= (2<<16)) && (w_ratio < (4<<16))) { \r
daw = (msg->src.act_w + 1) >> 1;\r
- if((IS_YUV_420(mp->dst.format)) && (daw & 1)) {\r
- mp->src.act_w = (daw - 1) << 1; \r
+ if((IS_YUV_420(msg->dst.format)) && (daw & 1)) {\r
+ msg->src.act_w = (daw - 1) << 1; \r
} \r
}\r
else if ((w_ratio >= (4<<16)) && (w_ratio < (8<<16))) {\r
daw = (msg->src.act_w + 3) >> 2; \r
- if((IS_YUV_420(mp->dst.format)) && (daw & 1)) {\r
- mp->src.act_w = (daw - 1) << 2; \r
+ if((IS_YUV_420(msg->dst.format)) && (daw & 1)) {\r
+ msg->src.act_w = (daw - 1) << 2; \r
}\r
}\r
else if ((w_ratio >= (8<<16)) && (w_ratio < (16<<16))) {\r
daw = (msg->src.act_w + 7) >> 3;\r
- if((IS_YUV_420(mp->dst.format)) && (daw & 1)) {\r
- mp->src.act_w = (daw - 1) << 3; \r
+ if((IS_YUV_420(msg->dst.format)) && (daw & 1)) {\r
+ msg->src.act_w = (daw - 1) << 3; \r
}\r
}\r
\r
pl = (RGA_pixel_width_init(msg->src.format));\r
stride = (pl * daw + 3) & (~3);\r
- mp->dst.act_w = daw;\r
- mp->dst.vir_w = stride / pl;\r
+ msg->dst.act_w = daw;\r
+ msg->dst.vir_w = stride / pl;\r
\r
/*pre_scale_h cal*/ \r
if ((h_ratio >= (2<<16)) && (h_ratio < (4<<16))) { \r
dah = (msg->src.act_h + 1) >> 1; \r
- if((IS_YUV(mp->dst.format)) && (dah & 1)) {\r
- mp->src.act_h = (dah - 1) << 1; \r
+ if((IS_YUV(msg->dst.format)) && (dah & 1)) {\r
+ msg->src.act_h = (dah - 1) << 1; \r
} \r
}\r
else if ((h_ratio >= (4<<16)) && (h_ratio < (8<<16))) {\r
dah = (msg->src.act_h + 3) >> 2; \r
- if((IS_YUV(mp->dst.format)) && (dah & 1)) {\r
- mp->src.act_h = (dah - 1) << 2; \r
+ if((IS_YUV(msg->dst.format)) && (dah & 1)) {\r
+ msg->src.act_h = (dah - 1) << 2; \r
}\r
}\r
else if ((h_ratio >= (8<<16)) && (h_ratio < (16<<16))) {\r
dah = (msg->src.act_h + 7) >> 3;\r
- if((IS_YUV(mp->dst.format)) && (dah & 1)) {\r
- mp->src.act_h = (dah - 1) << 3; \r
+ if((IS_YUV(msg->dst.format)) && (dah & 1)) {\r
+ msg->src.act_h = (dah - 1) << 3; \r
}\r
}\r
- mp->dst.act_h = dah;\r
- mp->dst.vir_h = dah;\r
+ msg->dst.act_h = dah;\r
+ msg->dst.vir_h = dah;\r
\r
- mp->dst.yrgb_addr = (u32)rga_service.pre_scale_buf;\r
- mp->dst.uv_addr = mp->dst.yrgb_addr + stride * dah;\r
- mp->dst.v_addr = mp->dst.uv_addr + ((stride * dah) >> 1);\r
+ msg->dst.yrgb_addr = (u32)rga_service.pre_scale_buf;\r
+ msg->dst.uv_addr = msg->dst.yrgb_addr + stride * dah;\r
+ msg->dst.v_addr = msg->dst.uv_addr + ((stride * dah) >> 1);\r
\r
- mp->render_mode = pre_scaling_mode;\r
+ msg->render_mode = pre_scaling_mode;\r
\r
- memcpy(&msg->src, &mp->dst, sizeof(rga_img_info_t));\r
+ memcpy(&msg1->src, &msg->dst, sizeof(rga_img_info_t));\r
\r
return 0;\r
}\r
#define ENABLE 1\r
#define DISABLE 0\r
\r
-#if 0\r
-int\r
-RGA_set_src_act_info(\r
- msg_t *msg,\r
- unsigned int width, /* act width */\r
- unsigned int height, /* act height */\r
- unsigned int x_off, /* x_off */\r
- unsigned int y_off /* y_off */\r
- );\r
-\r
-int\r
-RGA_set_src_vir_info(\r
- msg_t *msg,\r
- unsigned int yrgb_addr, /* yrgb_addr */\r
- unsigned int uv_addr, /* uv_addr */\r
- unsigned int v_addr, /* v_addr */\r
- unsigned int vir_w, /* vir width */\r
- unsigned int vir_h, /* vir height */\r
- unsigned char format, /* format */\r
- unsigned char a_swap_en\r
- );\r
-\r
-int\r
-RGA_set_dst_act_info(\r
- msg_t *msg,\r
- unsigned int width, /* act width */\r
- unsigned int height, /* act height */\r
- unsigned int x_off, /* x_off */\r
- unsigned int y_off /* y_off */\r
- );\r
-\r
-int\r
-RGA_set_dst_vir_info(\r
- msg_t *msg,\r
- unsigned int yrgb_addr, /* yrgb_addr */\r
- unsigned int uv_addr, /* uv_addr */\r
- unsigned int v_addr, /* v_addr */\r
- unsigned int vir_w, /* vir width */\r
- unsigned int vir_h, /* vir height */\r
- RECT clip, /* clip window*/\r
- unsigned char format, /* format */\r
- unsigned char a_swap_en );\r
-\r
-\r
-\r
-int\r
-RGA_set_rop_mask_info(\r
- msg_t *msg, \r
- u32 rop_mask_addr, \r
- u32 rop_mask_endian_mode);\r
-\r
-int \r
-RGA_set_pat_info(\r
- msg_t *msg,\r
- u32 width,\r
- u32 height,\r
- u32 x_off,\r
- u32 y_off,\r
- u32 pat_format); \r
-\r
-int\r
-RGA_set_alpha_en_info(\r
- msg_t *msg,\r
- unsigned int alpha_cal_mode,\r
- unsigned int alpha_mode,\r
- unsigned int global_a_value,\r
- unsigned int PD_en,\r
- unsigned int PD_mode\r
- );\r
-\r
-int\r
-RGA_set_rop_en_info(\r
- msg_t *msg,\r
- unsigned int ROP_mode,\r
- unsigned int ROP_code,\r
- unsigned int color_mode,\r
- unsigned int solid_color);\r
-\r
-/*\r
-int\r
-RGA_set_MMU_info(\r
- MSG *msg,\r
- unsigned int base_addr,\r
- unsigned int src_flush,\r
- unsigned int dst_flush,\r
- unsigned int cmd_flush,\r
- unsigned int page_size\r
- );\r
-*/\r
-\r
-int\r
-RGA_set_MMU_info(\r
- msg_t *msg,\r
- u8 mmu_en,\r
- u8 src_flush,\r
- u8 dst_flush,\r
- u8 cmd_flush,\r
- u32 base_addr,\r
- u8 page_size);\r
-\r
-\r
-int\r
-RGA_set_bitblt_mode(\r
- msg_t *msg,\r
- unsigned char scale_mode, // 0/near 1/bilnear 2/bicubic \r
- unsigned char rotate_mode, // 0/copy 1/rotate_scale 2/x_mirror 3/y_mirror \r
- unsigned int angle, // rotate angle (0~359) \r
- unsigned int dither_en, // dither en flag \r
- unsigned int AA_en, // AA flag \r
- unsigned int yuv2rgb_mode\r
- );\r
-\r
-\r
-int\r
-RGA_set_color_palette_mode(\r
- msg_t *msg,\r
- u8 palette_mode, /* 1bpp/2bpp/4bpp/8bpp */\r
- u8 endian_mode, /* src endian mode sel */\r
- u32 bpp1_0_color, /* BPP1 = 0 */\r
- u32 bpp1_1_color /* BPP1 = 1 */\r
- );\r
-\r
-\r
-\r
-int\r
-RGA_set_color_fill_mode(\r
- msg_t *msg,\r
- CF_GR_COLOR gr_color, /* gradient color part*/\r
- u8 gr_satur_mode, /* saturation mode */\r
- u8 cf_mode, /* patten fill or solid fill */\r
- u32 color, /* solid color */\r
- u16 pat_width, /* pat_width */\r
- u16 pat_height, /* pat_height */\r
- u8 pat_x_off, /* patten x offset */\r
- u8 pat_y_off, /* patten y offset */\r
- u8 aa_en /* alpha en */\r
- );\r
-\r
-\r
-int\r
-RGA_set_line_point_drawing_mode(\r
- msg_t *msg,\r
- POINT sp, /* start point */\r
- POINT ep, /* end point */\r
- unsigned int color, /* line point drawing color */\r
- unsigned int line_width, /* line width */\r
- unsigned char AA_en, /* AA en */\r
- unsigned char last_point_en /* last point en */\r
- );\r
-\r
-\r
-\r
-int\r
-RGA_set_blur_sharp_filter_mode(\r
- msg_t *msg,\r
- unsigned char filter_mode, /* blur/sharpness */\r
- unsigned char filter_type, /* filter intensity */\r
- unsigned char dither_en /* dither_en flag */\r
- );\r
-\r
-int\r
-RGA_set_pre_scaling_mode(\r
- msg_t *msg,\r
- unsigned char dither_en\r
- );\r
-\r
-\r
-int\r
-RGA_update_palette_table_mode(\r
- msg_t *msg,\r
- unsigned int LUT_addr, /* LUT table addr */\r
- unsigned int palette_mode /* 1bpp/2bpp/4bpp/8bpp */\r
- );\r
-\r
-\r
-int\r
-RGA_set_update_patten_buff_mode(\r
- msg_t *msg,\r
- unsigned int pat_addr, /* patten addr */\r
- unsigned int w, /* patten width */\r
- unsigned int h, /* patten height */\r
- unsigned int format /* patten format */\r
- );\r
-/*\r
-int\r
-RGA_set_MMU_info(\r
- MSG *msg,\r
- unsigned int base_addr,\r
- unsigned int src_flush,\r
- unsigned int dst_flush,\r
- unsigned int cmd_flush,\r
- unsigned int page_size\r
- );\r
-*/\r
-\r
-int\r
-RGA_set_mmu_info(\r
- msg_t *msg,\r
- u8 mmu_en,\r
- u8 src_flush,\r
- u8 dst_flush,\r
- u8 cmd_flush,\r
- u32 base_addr,\r
- u8 page_size);\r
-\r
-msg_t * RGA_init_msg(void);\r
-int RGA_free_msg(msg_t *msg);\r
-void matrix_cal(msg_t *msg, TILE_INFO *tile);\r
-unsigned char * RGA_set_reg_info(msg_t *msg, u8 *base);\r
-void RGA_set_cmd_info(u8 cmd_mode, u32 cmd_addr);\r
-void RGA_start(void);\r
-void RGA_soft_reset(void);\r
-#endif\r
-\r
uint32_t RGA_gen_two_pro(struct rga_req *msg, struct rga_req *msg1);\r
\r
\r
/* ([4] zero mode en) */\r
/* ([5] dst alpha mode) */\r
\r
- uint8_t src_trans_mode;\r
-\r
- uint8_t CMD_fin_int_enable; \r
-\r
- /* completion is reported through a callback */\r
- void (*complete)(int retval);\r
+ uint8_t src_trans_mode; \r
};\r
\r
\r
#include <linux/fb.h>\r
\r
\r
-\r
#include "rga.h"\r
#include "rga_reg_info.h"\r
#include "rga_mmu_info.h"\r
#include "RGA_API.h"\r
\r
+extern struct fb_info * rk_get_fb(int fb_id);\r
+extern void rk_direct_fb_show(struct fb_info * fbi);\r
+\r
\r
-#define RGA_TEST 1\r
+#define RGA_TEST 0\r
\r
#define PRE_SCALE_BUF_SIZE 2048*1024*4\r
\r
#define RGA_POWER_OFF_DELAY 4*HZ /* 4s */\r
#define RGA_TIMEOUT_DELAY 2*HZ /* 2s */\r
\r
+uint32_t dst_buf[800*480*4];\r
+uint32_t src_buf[1024*768*2];\r
+\r
struct rga_drvdata {\r
struct miscdevice miscdev;\r
struct device dev;\r
\r
if (!num)\r
{\r
+ #ifdef RGA_TEST \r
printk("rga try set reg cmd num is 0\n");\r
+ #endif\r
+ \r
return;\r
}\r
\r
rga_reg_from_wait_to_run(reg);\r
\r
rga_write(0x1<<10, RGA_INT);\r
+\r
+ #ifdef RGA_TEST\r
+ {\r
+ uint32_t i;\r
+ printk("CMD_REG\n");\r
+ for(i=0; i<28; i++) \r
+ printk("%.8x\n", rga_service.cmd_buff[i + 28*atomic_read(&rga_service.cmd_num)]); \r
+ }\r
+ #endif\r
\r
atomic_set(®->session->done, 0);\r
\r
\r
/* \r
* if cmd buf must use mmu\r
- * it should be writed before cmd start \r
+ * it should be configured before cmd start \r
*/\r
rga_write((2<<4)|0x1, RGA_MMU_CTRL);\r
rga_write(virt_to_phys(reg->MMU_base)>>2, RGA_MMU_TBL);\r
/* master mode */\r
rga_write(0x1<<2, RGA_SYS_CTRL);\r
\r
+ #ifdef RGA_TEST\r
+ {\r
+ uint32_t i;\r
+ printk("CMD_REG\n");\r
+ for (i=0; i<28; i++) \r
+ printk("%.8x\n", rga_service.cmd_buff[i]); \r
+ \r
+ }\r
+ #endif\r
+\r
/* All CMD finish int */\r
rga_write(0x1<<10, RGA_INT);\r
\r
atomic_set(®->session->done, 0);\r
rga_write(0x1, RGA_CMD_CTRL);\r
\r
+ #ifdef RGA_TEST\r
+ {\r
+ uint32_t i;\r
+ printk("CMD_READ_BACK_REG\n");\r
+ for (i=0; i<28; i++) \r
+ printk("%.8x\n", rga_read(0x100 + i*4)); \r
+ }\r
+ #endif\r
+\r
}\r
num--;\r
}\r
struct rga_req *req2;\r
\r
uint32_t saw, sah, daw, dah;\r
+\r
+ req2 = NULL;\r
\r
saw = req->src.act_w;\r
sah = req->src.act_h;\r
daw = req->dst.act_w;\r
dah = req->dst.act_h;\r
\r
- if((req->render_mode == bitblt_mode) && (((saw>>1) >= daw) || ((sah>>1) >= dah))) \r
+ do\r
{\r
- /* generate 2 cmd for pre scale */\r
- \r
- req2 = kmalloc(sizeof(struct rga_req), GFP_KERNEL);\r
- if(NULL == req2) {\r
- return -EINVAL; \r
- }\r
-\r
- RGA_gen_two_pro(req, req2);\r
-\r
- reg = rga_reg_init_2(session, req2, req);\r
- if(reg == NULL) {\r
- return -EFAULT;\r
- }\r
- \r
- atomic_set(®->int_enable, 1);\r
+ if((req->render_mode == bitblt_mode) && (((saw>>1) >= daw) || ((sah>>1) >= dah))) \r
+ { \r
+ /* generate 2 cmd for pre scale */ \r
+ req2 = kmalloc(sizeof(struct rga_req), GFP_KERNEL);\r
+ if(NULL == req2) {\r
+ return -EINVAL; \r
+ }\r
+ \r
+ RGA_gen_two_pro(req, req2);\r
\r
- rga_try_set_reg(2);\r
+ reg = rga_reg_init_2(session, req, req2);\r
+ if(reg == NULL) {\r
+ break;\r
+ }\r
+ \r
+ atomic_set(®->int_enable, 1);\r
\r
- if(req2 != NULL)\r
- {\r
- kfree(req2);\r
+ rga_try_set_reg(2);\r
+ \r
}\r
-\r
+ else {\r
+ /* check value if legal */\r
+ ret = rga_check_param(req);\r
+ if(ret == -EINVAL) {\r
+ return -EINVAL;\r
+ }\r
+ \r
+ reg = rga_reg_init(session, req);\r
+ if(reg == NULL) {\r
+ return -EFAULT;\r
+ }\r
+ \r
+ rga_try_set_reg(1); \r
+ } \r
}\r
- else {\r
- /* check value if legal */\r
- ret = rga_check_param(req);\r
- if(ret == -EINVAL) {\r
- return -EINVAL;\r
- }\r
- \r
- reg = rga_reg_init(session, req);\r
- if(reg == NULL) {\r
- return -EFAULT;\r
- }\r
- \r
- rga_try_set_reg(1); \r
+ while(0);\r
+\r
+ if(NULL != req2)\r
+ {\r
+ kfree(req2);\r
}\r
\r
//printk("rga_blit_async done******************\n");\r
static int rga_blit_sync(rga_session *session, struct rga_req *req)\r
{\r
int ret = 0;\r
+ int ret_timeout = 0;\r
struct rga_reg *reg;\r
struct rga_req *req2;\r
\r
/* generate 2 cmd for pre scale */\r
\r
req2 = kmalloc(sizeof(struct rga_req), GFP_KERNEL);\r
- if(NULL == req2) {\r
+ if (NULL == req2) \r
+ {\r
return -EINVAL; \r
}\r
-\r
+ \r
RGA_gen_two_pro(req, req2);\r
\r
reg = rga_reg_init_2(session, req2, req);\r
- if(reg == NULL) {\r
+ if (NULL == reg) \r
+ {\r
return -EFAULT;\r
}\r
- \r
+ \r
atomic_set(®->int_enable, 1);\r
\r
rga_try_set_reg(2); \r
\r
}\r
- else {\r
+ else \r
+ {\r
/* check value if legal */ \r
ret = rga_check_param(req);\r
- if(ret == -EINVAL) {\r
+ if(ret == -EINVAL) \r
+ {\r
return -EFAULT;\r
}\r
\r
reg = rga_reg_init(session, req);\r
- if(reg == NULL) {\r
+ if(reg == NULL) \r
+ { \r
return -EFAULT;\r
}\r
-\r
- atomic_set(®->int_enable, 1);\r
\r
+ atomic_set(®->int_enable, 1); \r
rga_try_set_reg(1);\r
} \r
\r
- ret = wait_event_interruptible_timeout(session->wait, atomic_read(&session->done), RGA_TIMEOUT_DELAY);\r
- if (unlikely(ret < 0)) \r
+ ret_timeout = wait_event_interruptible_timeout(session->wait, atomic_read(&session->done), RGA_TIMEOUT_DELAY);\r
+ if (unlikely(ret_timeout< 0)) \r
{\r
- pr_err("pid %d wait task ret %d\n", session->pid, ret);\r
+ pr_err("pid %d wait task ret %d\n", session->pid, ret_timeout);\r
} \r
- else if (0 == ret) \r
+ else if (0 == ret_timeout) \r
{\r
pr_err("pid %d wait %d task done timeout\n", session->pid, atomic_read(&session->task_running));\r
ret = -ETIMEDOUT;\r
//printk("rga_blit_sync done******************\n");\r
}\r
\r
+\r
static long rga_ioctl(struct file *file, uint32_t cmd, unsigned long arg)\r
{\r
struct rga_req *req;\r
ret = -EINVAL;\r
}\r
\r
- if (unlikely(copy_from_user(&req, (struct rga_req*)arg, sizeof(struct rga_req)))) \r
+ if (unlikely(copy_from_user(req, (struct rga_req*)arg, sizeof(struct rga_req)))) \r
{\r
ERR("copy_from_user failed\n");\r
ret = -EFAULT;\r
\r
if(req != NULL) {\r
kfree(req);\r
- }\r
- \r
+ } \r
return ret;\r
}\r
\r
{\r
reg = list_entry(rga_service.running.next, struct rga_reg, status_link);\r
\r
- #if 0\r
if(reg->MMU_base != NULL)\r
{\r
kfree(reg->MMU_base);\r
}\r
- #endif\r
\r
atomic_sub(1, ®->session->task_running);\r
atomic_sub(1, &rga_service.total_running);\r
reg = list_entry(next->next, struct rga_reg, status_link);\r
int_enable = atomic_read(®->int_enable); \r
next = next->next;\r
- }\r
+ } \r
\r
rga_try_set_reg(num);\r
\r
},\r
};\r
\r
+extern void rga_test_0();\r
+\r
static int __init rga_init(void)\r
{\r
int ret;\r
platform_driver_unregister(&rga_driver); \r
}\r
\r
-\r
module_init(rga_init);\r
module_exit(rga_exit);\r
\r
-\r
/* Module information */\r
MODULE_AUTHOR("zsq@rock-chips.com");\r
MODULE_DESCRIPTION("Driver for rga device");\r
uint32_t i;\r
uint32_t status;\r
\r
+ status = 0;\r
+\r
do\r
{ \r
down_read(¤t->mm->mmap_sem);\r
MMU_Base = NULL;\r
\r
do\r
- {\r
+ { \r
/* cal src buf mmu info */ \r
SrcMemSize = rga_buf_size_cal(req->src.yrgb_addr, req->src.uv_addr, req->src.v_addr,\r
req->src.format, req->src.vir_w, req->src.vir_h,\r
if(SrcMemSize == 0) {\r
return -EINVAL; \r
}\r
+ \r
\r
/* cal dst buf mmu info */ \r
DstMemSize = rga_buf_size_cal(req->dst.yrgb_addr, req->dst.uv_addr, req->dst.v_addr,\r
return -EINVAL; \r
}\r
\r
+ \r
+ /* Cal out the needed mem size */\r
AllSize = SrcMemSize + DstMemSize + CMDMemSize;\r
\r
pages = (struct page **)kmalloc(AllSize * sizeof(struct page *), GFP_KERNEL);\r
{\r
MMU_p = MMU_Base + CMDMemSize;\r
\r
- for(i=0; i<SrcMemSize; i++)\r
+ if(req->src.yrgb_addr == (uint32_t)rga_service.pre_scale_buf)\r
{\r
- MMU_p[i] = (uint32_t)virt_to_phys((uint32_t *)((SrcStart + i) << PAGE_SHIFT));\r
+ /* Down scale ratio over 2, Last prc */\r
+ /* MMU table copy from pre scale table */\r
+ \r
+ for(i=0; i<SrcMemSize; i++)\r
+ {\r
+ MMU_p[i] = rga_service.pre_scale_buf[i];\r
+ } \r
}\r
+ else\r
+ { \r
+ for(i=0; i<SrcMemSize; i++)\r
+ {\r
+ MMU_p[i] = (uint32_t)virt_to_phys((uint32_t *)((SrcStart + i) << PAGE_SHIFT));\r
+ }\r
+ } \r
}\r
\r
if (req->dst.yrgb_addr < KERNEL_SPACE_VALID)\r
}\r
\r
/* zsq \r
- * change the buf address in req struct\r
- * for the reason of lie to MMU \r
+ * change the buf address in req struct \r
*/\r
\r
req->mmu_info.base_addr = (virt_to_phys(MMU_Base)>>2); \r
\r
\r
/* zsq \r
- * change the buf address in req struct\r
- * for the reason of lie to MMU \r
+ * change the buf address in req struct \r
*/\r
+ \r
req->mmu_info.base_addr = virt_to_phys(MMU_Base); \r
req->dst.yrgb_addr = (req->dst.yrgb_addr & (~PAGE_MASK)) | ((CMDMemSize) << PAGE_SHIFT);\r
- \r
- \r
+ \r
/*record the malloc buf for the cmd end to release*/\r
reg->MMU_base = MMU_Base;\r
\r
{ \r
/* kernel space */\r
MMU_p = MMU_Base + CMDMemSize + SrcMemSize;\r
- for(i=0; i<DstMemSize; i++) \r
+\r
+ if(req->dst.yrgb_addr == (uint32_t)rga_service.pre_scale_buf)\r
{\r
- MMU_p[i] = virt_to_phys((uint32_t *)((DstStart + i)<< PAGE_SHIFT)); \r
+ for(i=0; i<DstMemSize; i++)\r
+ {\r
+ MMU_p[i] = rga_service.pre_scale_buf[i];\r
+ }\r
}\r
+ else\r
+ {\r
+ for(i=0; i<DstMemSize; i++) \r
+ {\r
+ MMU_p[i] = virt_to_phys((uint32_t *)((DstStart + i)<< PAGE_SHIFT)); \r
+ } \r
+ } \r
}\r
else \r
{\r
*/\r
req->mmu_info.base_addr = virt_to_phys(MMU_Base)>>2;\r
\r
- #if 0\r
req->src.yrgb_addr = (req->src.yrgb_addr & (~PAGE_MASK)) | (CMDMemSize << PAGE_SHIFT);\r
req->src.uv_addr = (req->src.uv_addr & (~PAGE_MASK)) | (CMDMemSize << PAGE_SHIFT);\r
req->src.v_addr = (req->src.v_addr & (~PAGE_MASK)) | (CMDMemSize << PAGE_SHIFT);\r
\r
req->dst.yrgb_addr = (req->dst.yrgb_addr & (~PAGE_MASK)) | ((CMDMemSize + SrcMemSize) << PAGE_SHIFT);\r
- #else\r
-\r
- req->src.yrgb_addr &= 0xffffff;\r
- req->src.uv_addr &= 0xfffffff;\r
- req->src.v_addr &= 0xfffffff;\r
-\r
- req->dst.yrgb_addr &= 0xfffffff;\r
- \r
- #endif\r
\r
/*record the malloc buf for the cmd end to release*/\r
reg->MMU_base = MMU_Base;\r
\r
ymax = MIN(MAX(MAX(MAX(pos[1], pos[3]), pos[5]), pos[7]), msg->clip.ymax);\r
ymin = MAX(MIN(MIN(MIN(pos[1], pos[3]), pos[5]), pos[7]), msg->clip.ymin);\r
-\r
- printk("xmax = %d, xmin = %d, ymin = %d, ymax = %d\n", xmax, xmin, ymin, ymax);\r
+ \r
+ //printk("xmax = %d, xmin = %d, ymin = %d, ymax = %d\n", xmax, xmin, ymin, ymax);\r
}\r
else if(msg->rotate_mode == 1)\r
{\r
\r
ymax = MIN(ymax, msg->clip.ymax);\r
ymin = MAX(ymin, msg->clip.ymin);\r
+\r
+ //printk("xmin = %d, xmax = %d, ymin = %d, ymax = %d\n", xmin, xmax, ymin, ymax);\r
}\r
} \r
\r
if ((xmin >= msg->dst.vir_w)||(xmax < 0)||(ymin >= msg->dst.vir_h)||(ymax < 0)) { \r
xmin = xmax = ymin = ymax = 0;\r
}\r
+\r
+ //printk("xmin = %d, xmax = %d, ymin = %d, ymax = %d\n", xmin, xmax, ymin, ymax);\r
\r
tile->dst_ctrl.w = (xmax - xmin);\r
tile->dst_ctrl.h = (ymax - ymin);\r
tile->dst_ctrl.x_off = xmin;\r
tile->dst_ctrl.y_off = ymin;\r
\r
- printk("tile->dst_ctrl.w = %x, tile->dst_ctrl.h = %x\n", tile->dst_ctrl.w, tile->dst_ctrl.h);\r
+ //printk("tile->dst_ctrl.w = %x, tile->dst_ctrl.h = %x\n", tile->dst_ctrl.w, tile->dst_ctrl.h);\r
\r
tile->tile_x_num = (xmax - xmin + 1 + 7)>>3;\r
tile->tile_y_num = (ymax - ymin + 1 + 7)>>3;\r
reg = ((reg & (~m_RGA_MODE_CTRL_DST_RGB_PACK)) | (s_RGA_MODE_CTRL_DST_RGB_PACK(dst_rgb_pack)));\r
reg = ((reg & (~m_RGA_MODE_CTRL_DST_RB_SWAP)) | (s_RGA_MODE_CTRL_DST_RB_SWAP(dst_rb_swp)));\r
reg = ((reg & (~m_RGA_MODE_CTRL_DST_ALPHA_SWAP)) | (s_RGA_MODE_CTRL_DST_ALPHA_SWAP(dst_a_swp)));\r
- reg = ((reg & (~m_RGA_MODE_CTRL_LUT_ENDIAN_MODE)) | (s_RGA_MODE_CTRL_LUT_ENDIAN_MODE(msg->endian_mode & 1))); \r
- reg = ((reg & (~m_RGA_MODE_CTRL_CMD_INT_ENABLE)) | (s_RGA_MODE_CTRL_CMD_INT_ENABLE(msg->CMD_fin_int_enable))); \r
+ reg = ((reg & (~m_RGA_MODE_CTRL_LUT_ENDIAN_MODE)) | (s_RGA_MODE_CTRL_LUT_ENDIAN_MODE(msg->endian_mode & 1))); \r
reg = ((reg & (~m_RGA_MODE_CTRL_SRC_TRANS_MODE)) | (s_RGA_MODE_CTRL_SRC_TRANS_MODE(msg->src_trans_mode)));\r
reg = ((reg & (~m_RGA_MODE_CTRL_ZERO_MODE_ENABLE)) | (s_RGA_MODE_CTRL_ZERO_MODE_ENABLE(msg->alpha_rop_mode >> 4)));\r
reg = ((reg & (~m_RGA_MODE_CTRL_DST_ALPHA_ENABLE)) | (s_RGA_MODE_CTRL_DST_ALPHA_ENABLE(msg->alpha_rop_mode >> 5)));\r
\r
if (!((xmax < 0)||(xmin > msg->src.act_w - 1)||(ymax < 0)||(ymin > msg->src.act_h - 1)))\r
{\r
- xp = CLIP(xp, 0, msg->src.vir_w - 1);\r
- yp = CLIP(yp, 0, msg->src.vir_h - 1);\r
+ xp = CLIP(xp, msg->src.x_offset, msg->src.x_offset + msg->src.act_w - 1);\r
+ yp = CLIP(yp, msg->src.y_offset, msg->src.y_offset + msg->src.act_h - 1);\r
}\r
\r
switch(msg->src.format)\r
reg = ((reg & (~m_RGA_MMU_CTRL_DST_FLUSH)) | s_RGA_MMU_CTRL_DST_FLUSH(dst_flag));\r
reg = ((reg & (~m_RGA_MMU_CTRL_CMD_CHAN_FLUSH)) | s_RGA_MMU_CTRL_CMD_CHAN_FLUSH(CMD_flag));\r
*RGA_MMU_CTRL_ADDR = reg;\r
- \r
+\r
return 0;\r
}\r
\r
RGA_set_dst(base, msg); \r
RGA_set_color(base, msg);\r
RGA_set_fading(base, msg);\r
- RGA_set_pat(base, msg);\r
+ RGA_set_pat(base, msg); \r
matrix_cal(msg, &tile);\r
dst_ctrl_cal(msg, &tile);\r
src_tile_info_cal(msg, &tile);\r
unsigned int RGA_gen_reg_info(const struct rga_req *msg, unsigned char *base);\r
uint8_t RGA_pixel_width_init(uint32_t format);\r
\r
-\r
-\r
-/*\r
-u8 RGA_pixel_width_init(u32 format);\r
-void dst_ctrl_cal(msg_t *msg, TILE_INFO *tile);\r
-void src_tile_info_cal(msg_t *msg, TILE_INFO *tile);\r
-void RGA_set_mode_ctrl(u8 *base, msg_t *msg);\r
-void RGA_set_src(u8 *base, msg_t *msg, TILE_INFO *tile);\r
-s32 RGA_set_dst(u8 *base, msg_t *msg);\r
-void RGA_set_alpha_rop(u8 *base, msg_t *msg);\r
-void RGA_set_color(u8 *base, msg_t *msg);\r
-s32 RGA_set_fading(u8 *base, msg_t *msg);\r
-s32 RGA_set_pat(u8 *base, msg_t *msg);\r
-void RGA_set_bitblt_reg_info(u8 *base, msg_t * msg, TILE_INFO *tile);\r
-void RGA_set_color_palette_reg_info(u8 *base, msg_t *msg);\r
-void RGA_set_color_fill_reg_info(u8 *base, msg_t *msg);\r
-s32 RGA_set_line_drawing_reg_info(u8 *base, msg_t *msg);\r
-s32 RGA_set_filter_reg_info(u8 *base, msg_t *msg);\r
-s32 RGA_set_pre_scale_reg_info(u8 *base, msg_t *msg);\r
-s32 RGA_set_update_palette_table_reg_info(u8 *base, msg_t *msg);\r
-s32 RGA_set_update_patten_buff_reg_info(u8 *base, msg_t *msg);\r
-s32 RGA_set_mmu_ctrl_reg_info(u8 *base, msg_t *msg);\r
-*/\r
projects / firefly-linux-kernel-4.4.55.git / commitdiff