Fix UnitTests/2005-05-13-SDivTwo.c

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21985 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86ISelPattern.cpp b/lib/Target/X86/X86ISelPattern.cpp
index 3345afcc4852ee429e74823447b509aceee82663..fcea635d47b8c3d250e7df069b6bccb450dc4970 100644 (file)
--- a/lib/Target/X86/X86ISelPattern.cpp
+++ b/lib/Target/X86/X86ISelPattern.cpp
@@ -2675,7 +2675,6 @@ unsigned ISel::SelectExpr(SDOperand N) {
         }
         if (RHS && (RHS & (RHS-1)) == 0) {   // Signed division by power of 2?
           unsigned Log = log2(RHS);
-          unsigned TmpReg = MakeReg(N.getValueType());
           unsigned SAROpc, SHROpc, ADDOpc, NEGOpc;
           switch (N.getValueType()) {
           default: assert("Unknown type to signed divide!");
@@ -2698,10 +2697,12 @@ unsigned ISel::SelectExpr(SDOperand N) {
             NEGOpc = X86::NEG32r;
             break;
           }
+          unsigned RegSize = MVT::getSizeInBits(N.getValueType());
           Tmp1 = SelectExpr(N.getOperand(0));
+          unsigned TmpReg = MakeReg(N.getValueType());
           BuildMI(BB, SAROpc, 2, TmpReg).addReg(Tmp1).addImm(Log-1);
           unsigned TmpReg2 = MakeReg(N.getValueType());
-          BuildMI(BB, SHROpc, 2, TmpReg2).addReg(TmpReg).addImm(32-Log);
+          BuildMI(BB, SHROpc, 2, TmpReg2).addReg(TmpReg).addImm(RegSize-Log);
           unsigned TmpReg3 = MakeReg(N.getValueType());
           BuildMI(BB, ADDOpc, 2, TmpReg3).addReg(Tmp1).addReg(TmpReg2);
 

diff --git a/lib/Target/X86/X86ISelSimple.cpp b/lib/Target/X86/X86ISelSimple.cpp
index ea5520fbf88c34a4fcb345098b658b09ae5671c5..e5898a801b1604b1ef45493e3313676985f07063 100644 (file)
--- a/lib/Target/X86/X86ISelSimple.cpp
+++ b/lib/Target/X86/X86ISelSimple.cpp
@@ -2924,7 +2924,7 @@ void X86ISel::emitDivRemOperation(MachineBasicBlock *BB,
           .addReg(Op0Reg).addImm(Log-1);
         unsigned TmpReg2 = makeAnotherReg(Op0->getType());
         BuildMI(*BB, IP, SHROpcode[Class], 2, TmpReg2)
-          .addReg(TmpReg).addImm(32-Log);
+          .addReg(TmpReg).addImm(CI->getType()->getPrimitiveSizeInBits()-Log);
         unsigned TmpReg3 = makeAnotherReg(Op0->getType());
         BuildMI(*BB, IP, ADDOpcode[Class], 2, TmpReg3)
           .addReg(Op0Reg).addReg(TmpReg2);