arm64: dts: rk3368 add pwm nodes

Rockchip 3368 SoC has the same pwm IP as 3288 SoC.
The pwm node for 3368 need to compatible with old
"rockchip-rk3288,pwm".

Change-Id: Id6741553b9e7c1a4643699647d67870f04bd0170
Signed-off-by: Jianqun xu <jay.xu@rock-chips.com>

diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index cc093a482aa461f9bd62914e28fc94b1d693d8b6..521026de1f6404199ecaf14a433d70bb680dc352 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -471,6 +471,48 @@
                status = "disabled";
        };
 
+       pwm0: pwm@ff680000 {
+               compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
+               reg = <0x0 0xff680000 0x0 0x10>;
+               #pwm-cells = <3>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pwm0_pin>;
+               clocks = <&cru PCLK_PWM1>;
+               clock-names = "pwm";
+               status = "disabled";
+       };
+
+       pwm1: pwm@ff680010 {
+               compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
+               reg = <0x0 0xff680010 0x0 0x10>;
+               #pwm-cells = <3>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pwm1_pin>;
+               clocks = <&cru PCLK_PWM1>;
+               clock-names = "pwm";
+               status = "disabled";
+       };
+
+       pwm2: pwm@ff680020 {
+               compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
+               reg = <0x0 0xff680020 0x0 0x10>;
+               #pwm-cells = <3>;
+               clocks = <&cru PCLK_PWM1>;
+               clock-names = "pwm";
+               status = "disabled";
+       };
+
+       pwm3: pwm@ff680030 {
+               compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
+               reg = <0x0 0xff680030 0x0 0x10>;
+               #pwm-cells = <3>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pwm3_pin>;
+               clocks = <&cru PCLK_PWM1>;
+               clock-names = "pwm";
+               status = "disabled";
+       };
+
        uart2: serial@ff690000 {
                compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
                reg = <0x0 0xff690000 0x0 0x100>;
@@ -896,5 +938,27 @@
                                rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
                        };
                };
+
+               pwm0 {
+                       pwm0_pin: pwm0-pin {
+                               rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
+                       };
+
+                       vop_pwm_pin: vop-pwm {
+                               rockchip,pins = <3 8 RK_FUNC_3 &pcfg_pull_none>;
+                       };
+               };
+
+               pwm1 {
+                       pwm1_pin: pwm1-pin {
+                               rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
+                       };
+               };
+
+               pwm3 {
+                       pwm3_pin: pwm3-pin {
+                               rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
+                       };
+               };
        };
 };