Fix a bug in x86's PreprocessForRMW logic that was exposed

by aggressive chain operand optimization. UpdateNodeOperands
does not modify the node in place if it would result in
a node identical to an existing node.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78297 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp
index e1344da588f0ae907d9c865168586b9efa7210b3..7340d7fb64b547547c9148f87e867f11bc4d4d2f 100644 (file)
--- a/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -342,9 +342,11 @@ static void MoveBelowTokenFactor(SelectionDAG *CurDAG, SDValue Load,
       Ops.push_back(Load.getOperand(0));
     else
       Ops.push_back(TF.getOperand(i));
-  CurDAG->UpdateNodeOperands(TF, &Ops[0], Ops.size());
-  CurDAG->UpdateNodeOperands(Load, TF, Load.getOperand(1), Load.getOperand(2));
-  CurDAG->UpdateNodeOperands(Store, Load.getValue(1), Store.getOperand(1),
+  SDValue NewTF = CurDAG->UpdateNodeOperands(TF, &Ops[0], Ops.size());
+  SDValue NewLoad = CurDAG->UpdateNodeOperands(Load, NewTF,
+                                               Load.getOperand(1),
+                                               Load.getOperand(2));
+  CurDAG->UpdateNodeOperands(Store, NewLoad.getValue(1), Store.getOperand(1),
                              Store.getOperand(2), Store.getOperand(3));
 }
 

diff --git a/test/CodeGen/X86/combiner-aa-0.ll b/test/CodeGen/X86/combiner-aa-0.ll
new file mode 100644 (file)
index 0000000..d2913ab
--- /dev/null
+++ b/test/CodeGen/X86/combiner-aa-0.ll
@@ -0,0 +1,20 @@
+; RUN: llvm-as < %s | llc -march=x86-64 -combiner-global-alias-analysis -combiner-alias-analysis
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+       %struct.Hash_Key = type { [4 x i32], i32 }
+@g_flipV_hashkey = external global %struct.Hash_Key, align 16          ; <%struct.Hash_Key*> [#uses=1]
+
+define void @foo() nounwind {
+       %t0 = load i32* undef, align 16         ; <i32> [#uses=1]
+       %t1 = load i32* null, align 4           ; <i32> [#uses=1]
+       %t2 = srem i32 %t0, 32          ; <i32> [#uses=1]
+       %t3 = shl i32 1, %t2            ; <i32> [#uses=1]
+       %t4 = xor i32 %t3, %t1          ; <i32> [#uses=1]
+       store i32 %t4, i32* null, align 4
+       %t5 = getelementptr %struct.Hash_Key* @g_flipV_hashkey, i64 0, i32 0, i64 0             ; <i32*> [#uses=2]
+       %t6 = load i32* %t5, align 4            ; <i32> [#uses=1]
+       %t7 = shl i32 1, undef          ; <i32> [#uses=1]
+       %t8 = xor i32 %t7, %t6          ; <i32> [#uses=1]
+       store i32 %t8, i32* %t5, align 4
+       unreachable
+}