<&aclk_peri_mux &clk_gpll>, <&clk_i2s_pll_mux &clk_cpll>,
<&clk_uart_pll_mux &clk_gpll>;
rockchip,clocks-init-rate =
- <&clk_core 594000000>, <&clk_gpll 768000000>,
+ <&clk_core 792000000>, <&clk_gpll 768000000>,
<&clk_cpll 594000000>, <&aclk_cpu 192000000>,
<&hclk_cpu 96000000>, <&pclk_cpu 48000000>,
<&pclk_ahb2apb 48000000>, <&aclk_peri 192000000>,
#ifndef __RK_CLK_OPS_H
#define __RK_CLK_OPS_H
#include "clkops-dtsi.h"
+#include "../../../arch/arm/mach-rockchip/iomap.h"
+#include "../../../arch/arm/mach-rockchip/grf.h"
#define MHZ (1000UL * 1000UL)
#define clk_err(fmt, args...) printk(KERN_ERR "rkclk: "fmt, ##args)
+
+#define cru_readl(offset) readl(RK_CRU_VIRT + (offset))
+#define cru_writel(v, o) do {writel(v, RK_CRU_VIRT + (o)); dsb();} \
+ while (0)
+#define grf_readl(offset) readl_relaxed(RK_GRF_VIRT + (offset))
+
#endif /* __RK_CLKOPS_H */
#include "clk-pll.h"
-//static unsigned long lpj_gpll;
-
-//fixme
-extern void __iomem *reg_start;
-#define RK30_CRU_BASE (reg_start)
-
-#define cru_readl(offset) readl(RK30_CRU_BASE + offset)
-#define cru_writel(v, offset) do {writel(v, RK30_CRU_BASE + offset); dsb();} \
- while (0)
-
-//fixme
-//#define grf_readl(offset) readl_relaxed(RK30_GRF_BASE + offset)
+//static unsigned long lpj_gpll;
#define PLLS_IN_NORM(pll_id) (((cru_readl(CRU_MODE_CON)&PLL_MODE_MSK(pll_id))\
==(PLL_MODE_NORM(pll_id)&PLL_MODE_MSK(pll_id)))\
_PLL_SET_CLKS(0, 0, 0, 0),
};
-
static void pll_wait_lock(int pll_idx)
{
-#if 1
- //fixme
- udelay(10);
-#else
u32 pll_state[4] = {1, 0, 2, 3};
u32 bit = 0x20u << pll_state[pll_idx];
int delay = 24000000;
while (delay > 0) {
- if (regfile_readl(GRF_SOC_STATUS0) & bit)
+ if (grf_readl(RK3188_GRF_SOC_STATUS0) & bit)
break;
delay--;
}
+
if (delay == 0) {
clk_err("PLL_ID=%d\npll_con0=%08x\npll_con1=%08x\n"
"pll_con2=%08x\npll_con3=%08x\n",
clk_err("wait pll bit 0x%x time out!\n", bit);
while(1);
}
-#endif
}
static DEFINE_SPINLOCK(clk_lock);
LIST_HEAD(rk_clks);
-void __iomem *reg_start = 0;
#define RKCLK_PLL_TYPE (1 << 0)
#define RKCLK_MUX_TYPE (1 << 1)
if (i % 4 == 0)
printk("\n%s: \t[0x%08x]: ",
__func__, 0x20000000 + i * 4);
- printk("%08x ", readl(reg_start + i * 4));
+ printk("%08x ", readl(RK_CRU_VIRT + i * 4));
}
printk("\n\n");
}
struct device_node *node_init;
struct rkclk *rkclk;
- reg_start = of_iomap(np, 0);
- if (reg_start == NULL) {
- clk_err("%s: can not get cru base!\n", __func__);
- return;
- } else {
- printk("%s: get cru base = 0x%x\n", __func__, (u32)reg_start);
- }
+
+ printk("%s start! cru base = 0x%08x\n", __func__, (u32)RK_CRU_VIRT);
node_init=of_find_node_by_name(NULL,"clocks-init");
if (!node_init) {
cnt_parent = of_count_phandle_with_args(np, "rockchip,clocks-init-parent", "#clock-init-cells");
- clk_debug("%s:cnt_parent =%d\n",__FUNCTION__,cnt_parent);
+ printk("%s: cnt_parent = %d\n",__FUNCTION__,cnt_parent);
for (i = 0; i < cnt_parent; i++) {
clk_parent_name=NULL;
clk_set_parent(clk_c, clk_p);
- clk_debug("%s: set %s parent = %s\n", __FUNCTION__, clk_name,
+ printk("%s: set %s parent = %s\n", __FUNCTION__, clk_name,
clk_parent_name);
}
cnt_rate = of_count_phandle_with_args(np, "rockchip,clocks-init-rate", "#clock-init-cells");
- clk_debug("%s:rate cnt=%d\n",__FUNCTION__,cnt_rate);
+ printk("%s: cnt_rate = %d\n",__FUNCTION__,cnt_rate);
for (i = 0; i < cnt_rate; i++) {
clk_name=of_clk_init_rate_get_info(np, i, &clk_rate);
clk_set_rate(clk_c, clk_rate);
- clk_debug("%s: set %s rate = %u\n", __FUNCTION__, clk_name,
+ printk("%s: set %s rate = %u\n", __FUNCTION__, clk_name,
clk_rate);
}