clk: rk: change clk_core init-rate and the way to get cru&grf base
authordkl <dkl@rock-chips.com>
Tue, 11 Feb 2014 02:16:42 +0000 (10:16 +0800)
committerdkl <dkl@rock-chips.com>
Tue, 11 Feb 2014 03:25:43 +0000 (11:25 +0800)
1. Change clk_core init-rate to 792 MHZ.
2. Use RK_CRU_VIRT & RK_GRF_VIRT to get cru&grf base.
3. Fix pll_wait_lock() func.

arch/arm/boot/dts/rk3188.dtsi
drivers/clk/rockchip/clk-ops.h
drivers/clk/rockchip/clk-pll.c
drivers/clk/rockchip/clk.c

index 3f48110748ec5acc5253cc071857a27bdda38dc2..b87da55bd2b61148f026246f6f4b89f47d691c41 100644 (file)
                        <&aclk_peri_mux &clk_gpll>,     <&clk_i2s_pll_mux &clk_cpll>,
                        <&clk_uart_pll_mux &clk_gpll>;
                rockchip,clocks-init-rate =
-                       <&clk_core 594000000>,  <&clk_gpll 768000000>,
+                       <&clk_core 792000000>,  <&clk_gpll 768000000>,
                        <&clk_cpll 594000000>,  <&aclk_cpu 192000000>,
                        <&hclk_cpu 96000000>,   <&pclk_cpu 48000000>,
                        <&pclk_ahb2apb 48000000>,       <&aclk_peri 192000000>,
index 57d0b8c91e1b949a2e6a26b51aef6f38c9baafd5..e65262a1a8d6d7d0e9719a1d42c17f41ac86c60e 100644 (file)
@@ -1,6 +1,8 @@
 #ifndef __RK_CLK_OPS_H
 #define __RK_CLK_OPS_H
 #include "clkops-dtsi.h"
+#include "../../../arch/arm/mach-rockchip/iomap.h"
+#include "../../../arch/arm/mach-rockchip/grf.h"
 
 
 #define MHZ                    (1000UL * 1000UL)
@@ -23,4 +25,10 @@ const struct clk_ops *rk_get_clkops(unsigned int idx);
 
 #define clk_err(fmt, args...) printk(KERN_ERR "rkclk: "fmt, ##args)
 
+
+#define cru_readl(offset)      readl(RK_CRU_VIRT + (offset))
+#define cru_writel(v, o)       do {writel(v, RK_CRU_VIRT + (o)); dsb();} \
+                               while (0)
+#define grf_readl(offset)      readl_relaxed(RK_GRF_VIRT + (offset))
+
 #endif /* __RK_CLKOPS_H */
index dba8f386e367998bf6f5723c90a017b052e57fbe..866e9326d2e1f677b1e1d126ea12cd1786007694 100644 (file)
@@ -5,19 +5,8 @@
 #include "clk-pll.h"
 
 
-//static unsigned long lpj_gpll;
-
-//fixme
-extern void __iomem *reg_start;
-#define RK30_CRU_BASE  (reg_start)
-
-#define cru_readl(offset)      readl(RK30_CRU_BASE + offset)
-#define cru_writel(v, offset)  do {writel(v, RK30_CRU_BASE + offset); dsb();} \
-       while (0)
-
-//fixme
-//#define grf_readl(offset)    readl_relaxed(RK30_GRF_BASE + offset)
 
+//static unsigned long lpj_gpll;
 
 #define PLLS_IN_NORM(pll_id) (((cru_readl(CRU_MODE_CON)&PLL_MODE_MSK(pll_id))\
                        ==(PLL_MODE_NORM(pll_id)&PLL_MODE_MSK(pll_id)))\
@@ -103,21 +92,17 @@ static const struct pll_clk_set pll_com_table[] = {
        _PLL_SET_CLKS(0,        0,      0,      0),
 };
 
-
 static void pll_wait_lock(int pll_idx)
 {
-#if 1
-       //fixme
-       udelay(10);
-#else
        u32 pll_state[4] = {1, 0, 2, 3};
        u32 bit = 0x20u << pll_state[pll_idx];
        int delay = 24000000;
        while (delay > 0) {
-               if (regfile_readl(GRF_SOC_STATUS0) & bit)
+               if (grf_readl(RK3188_GRF_SOC_STATUS0) & bit)
                        break;
                delay--;
        }
+       
        if (delay == 0) {
                clk_err("PLL_ID=%d\npll_con0=%08x\npll_con1=%08x\n"
                                "pll_con2=%08x\npll_con3=%08x\n",
@@ -130,7 +115,6 @@ static void pll_wait_lock(int pll_idx)
                clk_err("wait pll bit 0x%x time out!\n", bit);
                while(1);
        }
-#endif
 }
 
 
index 5f1940bf73f57fcc13d9bad23d60b63923305ee6..b1058968a54e60441b4dd8d98dee14c2af854993 100755 (executable)
@@ -110,7 +110,6 @@ struct rkclk {
 
 static DEFINE_SPINLOCK(clk_lock);
 LIST_HEAD(rk_clks);
-void __iomem *reg_start = 0;
 
 #define RKCLK_PLL_TYPE (1 << 0)
 #define RKCLK_MUX_TYPE (1 << 1)
@@ -721,7 +720,7 @@ void rk_dump_cru(void)
                if (i % 4 == 0)
                        printk("\n%s: \t[0x%08x]: ",
                                        __func__, 0x20000000 + i * 4);
-               printk("%08x ", readl(reg_start + i * 4));
+               printk("%08x ", readl(RK_CRU_VIRT + i * 4));
        }
        printk("\n\n");
 }
@@ -838,13 +837,8 @@ static void __init rk_clk_tree_init(struct device_node *np)
        struct device_node *node_init;
        struct rkclk *rkclk;
 
-       reg_start = of_iomap(np, 0);
-       if (reg_start == NULL) {
-               clk_err("%s: can not get cru base!\n", __func__);
-               return;
-       } else {
-               printk("%s: get cru base = 0x%x\n", __func__, (u32)reg_start);
-       }
+
+       printk("%s start! cru base = 0x%08x\n", __func__, (u32)RK_CRU_VIRT);
 
        node_init=of_find_node_by_name(NULL,"clocks-init");
        if (!node_init) {
@@ -1048,7 +1042,7 @@ void rkclk_init_clks(struct device_node *np)
 
        cnt_parent = of_count_phandle_with_args(np, "rockchip,clocks-init-parent", "#clock-init-cells");
 
-       clk_debug("%s:cnt_parent =%d\n",__FUNCTION__,cnt_parent);
+       printk("%s: cnt_parent = %d\n",__FUNCTION__,cnt_parent);
 
        for (i = 0; i < cnt_parent; i++) {
                clk_parent_name=NULL;
@@ -1065,13 +1059,13 @@ void rkclk_init_clks(struct device_node *np)
 
                clk_set_parent(clk_c, clk_p);
 
-               clk_debug("%s: set %s parent = %s\n", __FUNCTION__, clk_name,
+               printk("%s: set %s parent = %s\n", __FUNCTION__, clk_name,
                                clk_parent_name);
        }
 
        cnt_rate = of_count_phandle_with_args(np, "rockchip,clocks-init-rate", "#clock-init-cells");
 
-       clk_debug("%s:rate cnt=%d\n",__FUNCTION__,cnt_rate);
+       printk("%s: cnt_rate = %d\n",__FUNCTION__,cnt_rate);
 
        for (i = 0; i < cnt_rate; i++) {
                clk_name=of_clk_init_rate_get_info(np, i, &clk_rate);
@@ -1089,7 +1083,7 @@ void rkclk_init_clks(struct device_node *np)
 
                clk_set_rate(clk_c, clk_rate);
 
-               clk_debug("%s: set %s rate = %u\n", __FUNCTION__, clk_name,
+               printk("%s: set %s rate = %u\n", __FUNCTION__, clk_name,
                                clk_rate);
        }