[mips] [IAS] Add partial support for the ULW pseudo-instruction.

Summary:
This only adds support for ULW of an immediate address with/without a source register.
It does not include support for ULW of the address of a symbol.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9663

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240782 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
index 62c183289de5b9cff20b590bc006e9291e9e6017..a1106235a459856c0add2d55ac9ee6318be7dc6f 100644 (file)
--- a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -218,6 +218,9 @@ class MipsAsmParser : public MCTargetAsmParser {
   bool expandUlhu(MCInst &Inst, SMLoc IDLoc,
                   SmallVectorImpl<MCInst> &Instructions);
 
+  bool expandUlw(MCInst &Inst, SMLoc IDLoc,
+                 SmallVectorImpl<MCInst> &Instructions);
+
   void createNop(bool hasShortDelaySlot, SMLoc IDLoc,
                  SmallVectorImpl<MCInst> &Instructions);
 
@@ -1649,6 +1652,7 @@ bool MipsAsmParser::needsExpansion(MCInst &Inst) {
   case Mips::BGEU:
   case Mips::BGTU:
   case Mips::Ulhu:
+  case Mips::Ulw:
     return true;
   default:
     return false;
@@ -1689,6 +1693,8 @@ bool MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
     return expandCondBranches(Inst, IDLoc, Instructions);
   case Mips::Ulhu:
     return expandUlhu(Inst, IDLoc, Instructions);
+  case Mips::Ulw:
+    return expandUlw(Inst, IDLoc, Instructions);
   }
 }
 
@@ -2582,6 +2588,79 @@ bool MipsAsmParser::expandUlhu(MCInst &Inst, SMLoc IDLoc,
   return false;
 }
 
+bool MipsAsmParser::expandUlw(MCInst &Inst, SMLoc IDLoc,
+                              SmallVectorImpl<MCInst> &Instructions) {
+  if (hasMips32r6() || hasMips64r6()) {
+    Error(IDLoc, "instruction not supported on mips32r6 or mips64r6");
+    return false;
+  }
+
+  const MCOperand &DstRegOp = Inst.getOperand(0);
+  assert(DstRegOp.isReg() && "expected register operand kind");
+
+  const MCOperand &SrcRegOp = Inst.getOperand(1);
+  assert(SrcRegOp.isReg() && "expected register operand kind");
+
+  const MCOperand &OffsetImmOp = Inst.getOperand(2);
+  assert(OffsetImmOp.isImm() && "expected immediate operand kind");
+
+  unsigned SrcReg = SrcRegOp.getReg();
+  int64_t OffsetValue = OffsetImmOp.getImm();
+  unsigned ATReg = 0;
+
+  // When the value of offset+3 does not fit in 16 bits, we have to load the
+  // offset in AT, (D)ADDu the original source register (if there was one), and
+  // then use AT as the source register for the generated LWL and LWR.
+  bool LoadedOffsetInAT = false;
+  if (!isInt<16>(OffsetValue + 3) || !isInt<16>(OffsetValue)) {
+    ATReg = getATReg(IDLoc);
+    if (!ATReg)
+      return true;
+    LoadedOffsetInAT = true;
+
+    warnIfNoMacro(IDLoc);
+
+    if (loadImmediate(OffsetValue, ATReg, Mips::NoRegister, !ABI.ArePtrs64bit(),
+                      IDLoc, Instructions))
+      return true;
+
+    // NOTE: We do this (D)ADDu here instead of doing it in loadImmediate()
+    // because it will make our output more similar to GAS'. For example,
+    // generating an "ori $1, $zero, 32768" followed by an "addu $1, $1, $9",
+    // instead of just an "ori $1, $9, 32768".
+    // NOTE: If there is no source register specified in the ULW, the parser
+    // will interpret it as $0.
+    if (SrcReg != Mips::ZERO && SrcReg != Mips::ZERO_64)
+      createAddu(ATReg, ATReg, SrcReg, ABI.ArePtrs64bit(), Instructions);
+  }
+
+  unsigned FinalSrcReg = LoadedOffsetInAT ? ATReg : SrcReg;
+  int64_t LeftLoadOffset = 0, RightLoadOffset  = 0;
+  if (isLittle()) {
+    LeftLoadOffset = LoadedOffsetInAT ? 3 : (OffsetValue + 3);
+    RightLoadOffset  = LoadedOffsetInAT ? 0 : OffsetValue;
+  } else {
+    LeftLoadOffset = LoadedOffsetInAT ? 0 : OffsetValue;
+    RightLoadOffset  = LoadedOffsetInAT ? 3 : (OffsetValue + 3);
+  }
+
+  MCInst LeftLoadInst;
+  LeftLoadInst.setOpcode(Mips::LWL);
+  LeftLoadInst.addOperand(DstRegOp);
+  LeftLoadInst.addOperand(MCOperand::createReg(FinalSrcReg));
+  LeftLoadInst.addOperand(MCOperand::createImm(LeftLoadOffset));
+  Instructions.push_back(LeftLoadInst);
+
+  MCInst RightLoadInst;
+  RightLoadInst.setOpcode(Mips::LWR);
+  RightLoadInst.addOperand(DstRegOp);
+  RightLoadInst.addOperand(MCOperand::createReg(FinalSrcReg));
+  RightLoadInst.addOperand(MCOperand::createImm(RightLoadOffset ));
+  Instructions.push_back(RightLoadInst);
+
+  return false;
+}
+
 void MipsAsmParser::createNop(bool hasShortDelaySlot, SMLoc IDLoc,
                               SmallVectorImpl<MCInst> &Instructions) {
   MCInst NopInst;

diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td
index 17f9f290d642e1c159bc30e5e0aaa640679dc6fc..1f9543e810a418f6544fb0658b9f080c291528af 100644 (file)
--- a/lib/Target/Mips/MipsInstrInfo.td
+++ b/lib/Target/Mips/MipsInstrInfo.td
@@ -1716,6 +1716,9 @@ def BGTU : CondBranchPseudo<"bgtu">;
 def Ulhu : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr),
                              "ulhu\t$rt, $addr">, ISA_MIPS1_NOT_32R6_64R6;
 
+def Ulw : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr),
+                            "ulw\t$rt, $addr">, ISA_MIPS1_NOT_32R6_64R6;
+
 //===----------------------------------------------------------------------===//
 //  Arbitrary patterns that map to one or more instructions
 //===----------------------------------------------------------------------===//

diff --git a/test/MC/Mips/mips-expansions-bad.s b/test/MC/Mips/mips-expansions-bad.s
index 774ef931aace6fd8a127f8096f31924f67ecc0c4..416cb5f3ba69aa3cebf79f0e5ba8f193bbdf1849 100644 (file)
--- a/test/MC/Mips/mips-expansions-bad.s
+++ b/test/MC/Mips/mips-expansions-bad.s
@@ -36,3 +36,16 @@
   ulhu $5, 2
   # 32-BIT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6
   # 64-BIT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6
+
+  .set mips32r6
+  ulw $5, 0
+  # 32-BIT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6
+  # 64-BIT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6
+  .set mips32
+  ulw $5, 1
+  # 32-BIT-NOT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6
+  # 64-BIT-NOT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6
+  .set mips64r6
+  ulw $5, 2
+  # 32-BIT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6
+  # 64-BIT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6

diff --git a/test/MC/Mips/mips-expansions.s b/test/MC/Mips/mips-expansions.s
index b0d85e7fb0ce2fbb66559287e9a2769f3e5d41bc..55de6d046349eca500edd4f9476d6ec26d27709c 100644 (file)
--- a/test/MC/Mips/mips-expansions.s
+++ b/test/MC/Mips/mips-expansions.s
@@ -382,5 +382,141 @@
 # CHECK-LE: sll  $8, $8, 8         # encoding: [0x00,0x42,0x08,0x00]
 # CHECK-LE: or   $8, $8, $1        # encoding: [0x25,0x40,0x01,0x01]
 
+# Test ULW with immediate operand.
+  ulw $8, 0
+# CHECK-BE: lwl  $8, 0($zero)      # encoding: [0x88,0x08,0x00,0x00]
+# CHECK-BE: lwr  $8, 3($zero)      # encoding: [0x98,0x08,0x00,0x03]
+# CHECK-LE: lwl $8, 3($zero)       # encoding: [0x03,0x00,0x08,0x88]
+# CHECK-LE: lwr $8, 0($zero)       # encoding: [0x00,0x00,0x08,0x98]
+
+  ulw $8, 2
+# CHECK-BE: lwl  $8, 2($zero)      # encoding: [0x88,0x08,0x00,0x02]
+# CHECK-BE: lwr  $8, 5($zero)      # encoding: [0x98,0x08,0x00,0x05]
+# CHECK-LE: lwl $8, 5($zero)       # encoding: [0x05,0x00,0x08,0x88]
+# CHECK-LE: lwr $8, 2($zero)       # encoding: [0x02,0x00,0x08,0x98]
+
+  ulw $8, 0x8000
+# CHECK-BE: ori  $1, $zero, 32768  # encoding: [0x34,0x01,0x80,0x00]
+# CHECK-BE: lwl  $8, 0($1)         # encoding: [0x88,0x28,0x00,0x00]
+# CHECK-BE: lwr  $8, 3($1)         # encoding: [0x98,0x28,0x00,0x03]
+# CHECK-LE: ori $1, $zero, 32768   # encoding: [0x00,0x80,0x01,0x34]
+# CHECK-LE: lwl $8, 3($1)          # encoding: [0x03,0x00,0x28,0x88]
+# CHECK-LE: lwr $8, 0($1)          # encoding: [0x00,0x00,0x28,0x98]
+
+  ulw $8, -0x8000
+# CHECK-BE: lwl  $8, -32768($zero) # encoding: [0x88,0x08,0x80,0x00]
+# CHECK-BE: lwr  $8, -32765($zero) # encoding: [0x98,0x08,0x80,0x03]
+# CHECK-LE: lwl $8, -32765($zero)  # encoding: [0x03,0x80,0x08,0x88]
+# CHECK-LE: lwr $8, -32768($zero)  # encoding: [0x00,0x80,0x08,0x98]
+
+  ulw $8, 0x10000
+# CHECK-BE: lui  $1, 1             # encoding: [0x3c,0x01,0x00,0x01]
+# CHECK-BE: lwl  $8, 0($1)         # encoding: [0x88,0x28,0x00,0x00]
+# CHECK-BE: lwr  $8, 3($1)         # encoding: [0x98,0x28,0x00,0x03]
+# CHECK-LE: lui $1, 1              # encoding: [0x01,0x00,0x01,0x3c]
+# CHECK-LE: lwl $8, 3($1)          # encoding: [0x03,0x00,0x28,0x88]
+# CHECK-LE: lwr $8, 0($1)          # encoding: [0x00,0x00,0x28,0x98]
+
+  ulw $8, 0x18888
+# CHECK-BE: lui  $1, 1             # encoding: [0x3c,0x01,0x00,0x01]
+# CHECK-BE: ori  $1, $1, 34952     # encoding: [0x34,0x21,0x88,0x88]
+# CHECK-BE: lwl  $8, 0($1)         # encoding: [0x88,0x28,0x00,0x00]
+# CHECK-BE: lwr  $8, 3($1)         # encoding: [0x98,0x28,0x00,0x03]
+# CHECK-LE: lui $1, 1              # encoding: [0x01,0x00,0x01,0x3c]
+# CHECK-LE: ori $1, $1, 34952      # encoding: [0x88,0x88,0x21,0x34]
+# CHECK-LE: lwl $8, 3($1)          # encoding: [0x03,0x00,0x28,0x88]
+# CHECK-LE: lwr $8, 0($1)          # encoding: [0x00,0x00,0x28,0x98]
+
+  ulw $8, -32771
+# CHECK-BE: lui  $1, 65535         # encoding: [0x3c,0x01,0xff,0xff]
+# CHECK-BE: ori  $1, $1, 32765     # encoding: [0x34,0x21,0x7f,0xfd]
+# CHECK-BE: lwl  $8, 0($1)         # encoding: [0x88,0x28,0x00,0x00]
+# CHECK-BE: lwr  $8, 3($1)         # encoding: [0x98,0x28,0x00,0x03]
+# CHECK-LE: lui $1, 65535          # encoding: [0xff,0xff,0x01,0x3c]
+# CHECK-LE: ori $1, $1, 32765      # encoding: [0xfd,0x7f,0x21,0x34]
+# CHECK-LE: lwl $8, 3($1)          # encoding: [0x03,0x00,0x28,0x88]
+# CHECK-LE: lwr $8, 0($1)          # encoding: [0x00,0x00,0x28,0x98]
+
+  ulw $8, 32765
+# CHECK-BE: ori  $1, $zero, 32765  # encoding: [0x34,0x01,0x7f,0xfd]
+# CHECK-BE: lwl  $8, 0($1)         # encoding: [0x88,0x28,0x00,0x00]
+# CHECK-BE: lwr  $8, 3($1)         # encoding: [0x98,0x28,0x00,0x03]
+# CHECK-LE: ori $1, $zero, 32765   # encoding: [0xfd,0x7f,0x01,0x34]
+# CHECK-LE: lwl $8, 3($1)          # encoding: [0x03,0x00,0x28,0x88]
+# CHECK-LE: lwr $8, 0($1)          # encoding: [0x00,0x00,0x28,0x98]
+
+# Test ULW with immediate offset and a source register operand.
+  ulw $8, 0($9)
+# CHECK-BE: lwl  $8, 0($9)         # encoding: [0x89,0x28,0x00,0x00]
+# CHECK-BE: lwr  $8, 3($9)         # encoding: [0x99,0x28,0x00,0x03]
+# CHECK-LE: lwl  $8, 3($9)         # encoding: [0x03,0x00,0x28,0x89]
+# CHECK-LE: lwr  $8, 0($9)         # encoding: [0x00,0x00,0x28,0x99]
+
+  ulw $8, 2($9)
+# CHECK-BE: lwl  $8, 2($9)         # encoding: [0x89,0x28,0x00,0x02]
+# CHECK-BE: lwr  $8, 5($9)         # encoding: [0x99,0x28,0x00,0x05]
+# CHECK-LE: lwl  $8, 5($9)         # encoding: [0x05,0x00,0x28,0x89]
+# CHECK-LE: lwr  $8, 2($9)         # encoding: [0x02,0x00,0x28,0x99]
+
+  ulw $8, 0x8000($9)
+# CHECK-BE: ori  $1, $zero, 32768  # encoding: [0x34,0x01,0x80,0x00]
+# CHECK-BE: addu $1, $1, $9        # encoding: [0x00,0x29,0x08,0x21]
+# CHECK-BE: lwl  $8, 0($1)         # encoding: [0x88,0x28,0x00,0x00]
+# CHECK-BE: lwr  $8, 3($1)         # encoding: [0x98,0x28,0x00,0x03]
+# CHECK-LE: ori  $1, $zero, 32768  # encoding: [0x00,0x80,0x01,0x34]
+# CHECK-LE: addu $1, $1, $9        # encoding: [0x21,0x08,0x29,0x00]
+# CHECK-LE: lwl  $8, 3($1)         # encoding: [0x03,0x00,0x28,0x88]
+# CHECK-LE: lwr  $8, 0($1)         # encoding: [0x00,0x00,0x28,0x98]
+
+  ulw $8, -0x8000($9)
+# CHECK-BE: lwl  $8, -32768($9)    # encoding: [0x89,0x28,0x80,0x00]
+# CHECK-BE: lwr  $8, -32765($9)    # encoding: [0x99,0x28,0x80,0x03]
+# CHECK-LE: lwl  $8, -32765($9)    # encoding: [0x03,0x80,0x28,0x89]
+# CHECK-LE: lwr  $8, -32768($9)    # encoding: [0x00,0x80,0x28,0x99]
+
+  ulw $8, 0x10000($9)
+# CHECK-BE: lui  $1, 1             # encoding: [0x3c,0x01,0x00,0x01]
+# CHECK-BE: addu $1, $1, $9        # encoding: [0x00,0x29,0x08,0x21]
+# CHECK-BE: lwl  $8, 0($1)         # encoding: [0x88,0x28,0x00,0x00]
+# CHECK-BE: lwr  $8, 3($1)         # encoding: [0x98,0x28,0x00,0x03]
+# CHECK-LE: lui  $1, 1             # encoding: [0x01,0x00,0x01,0x3c]
+# CHECK-LE: addu $1, $1, $9        # encoding: [0x21,0x08,0x29,0x00]
+# CHECK-LE: lwl  $8, 3($1)         # encoding: [0x03,0x00,0x28,0x88]
+# CHECK-LE: lwr  $8, 0($1)         # encoding: [0x00,0x00,0x28,0x98]
+
+  ulw $8, 0x18888($9)
+# CHECK-BE: lui  $1, 1             # encoding: [0x3c,0x01,0x00,0x01]
+# CHECK-BE: ori  $1, $1, 34952     # encoding: [0x34,0x21,0x88,0x88]
+# CHECK-BE: addu $1, $1, $9        # encoding: [0x00,0x29,0x08,0x21]
+# CHECK-BE: lwl  $8, 0($1)         # encoding: [0x88,0x28,0x00,0x00]
+# CHECK-BE: lwr  $8, 3($1)         # encoding: [0x98,0x28,0x00,0x03]
+# CHECK-LE: lui  $1, 1             # encoding: [0x01,0x00,0x01,0x3c]
+# CHECK-LE: ori  $1, $1, 34952     # encoding: [0x88,0x88,0x21,0x34]
+# CHECK-LE: addu $1, $1, $9        # encoding: [0x21,0x08,0x29,0x00]
+# CHECK-LE: lwl  $8, 3($1)         # encoding: [0x03,0x00,0x28,0x88]
+# CHECK-LE: lwr  $8, 0($1)         # encoding: [0x00,0x00,0x28,0x98]
+
+  ulw $8, -32771($9)
+# CHECK-BE: lui  $1, 65535         # encoding: [0x3c,0x01,0xff,0xff]
+# CHECK-BE: ori  $1, $1, 32765     # encoding: [0x34,0x21,0x7f,0xfd]
+# CHECK-BE: addu $1, $1, $9        # encoding: [0x00,0x29,0x08,0x21]
+# CHECK-BE: lwl  $8, 0($1)         # encoding: [0x88,0x28,0x00,0x00]
+# CHECK-BE: lwr  $8, 3($1)         # encoding: [0x98,0x28,0x00,0x03]
+# CHECK-LE: lui  $1, 65535         # encoding: [0xff,0xff,0x01,0x3c]
+# CHECK-LE: ori  $1, $1, 32765     # encoding: [0xfd,0x7f,0x21,0x34]
+# CHECK-LE: addu $1, $1, $9        # encoding: [0x21,0x08,0x29,0x00]
+# CHECK-LE: lwl  $8, 3($1)         # encoding: [0x03,0x00,0x28,0x88]
+# CHECK-LE: lwr  $8, 0($1)         # encoding: [0x00,0x00,0x28,0x98]
+
+  ulw $8, 32765($9)
+# CHECK-BE: ori  $1, $zero, 32765  # encoding: [0x34,0x01,0x7f,0xfd]
+# CHECK-BE: addu $1, $1, $9        # encoding: [0x00,0x29,0x08,0x21]
+# CHECK-BE: lwl  $8, 0($1)         # encoding: [0x88,0x28,0x00,0x00]
+# CHECK-BE: lwr  $8, 3($1)         # encoding: [0x98,0x28,0x00,0x03]
+# CHECK-LE: ori  $1, $zero, 32765  # encoding: [0xfd,0x7f,0x01,0x34]
+# CHECK-LE: addu $1, $1, $9        # encoding: [0x21,0x08,0x29,0x00]
+# CHECK-LE: lwl  $8, 3($1)         # encoding: [0x03,0x00,0x28,0x88]
+# CHECK-LE: lwr  $8, 0($1)         # encoding: [0x00,0x00,0x28,0x98]
+
 1:
   add $4, $4, $4

diff --git a/test/MC/Mips/mips64-expansions.s b/test/MC/Mips/mips64-expansions.s
index 1256bfba4cfe46f62947dd95baa54a1ed6eecb9b..a66a520a211702c3487fa1d05916b88ae45b09d1 100644 (file)
--- a/test/MC/Mips/mips64-expansions.s
+++ b/test/MC/Mips/mips64-expansions.s
@@ -369,3 +369,85 @@
 # CHECK: lbu   $1, 0($1)       # encoding: [0x00,0x00,0x21,0x90]
 # CHECK: sll   $8, $8, 8       # encoding: [0x00,0x42,0x08,0x00]
 # CHECK: or    $8, $8, $1      # encoding: [0x25,0x40,0x01,0x01]
+
+# Test ulw with 64-bit immediate addresses.
+  ulw $8, 0x100010001
+# CHECK: lui  $1, 1           # encoding: [0x01,0x00,0x01,0x3c]
+# CHECK: ori  $1, $1, 1       # encoding: [0x01,0x00,0x21,0x34]
+# CHECK: dsll $1, $1, 16      # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori  $1, $1, 1       # encoding: [0x01,0x00,0x21,0x34]
+# CHECK: lwl  $8, 3($1)       # encoding: [0x03,0x00,0x28,0x88]
+# CHECK: lwr  $8, 0($1)       # encoding: [0x00,0x00,0x28,0x98]
+
+  ulw $8, 0x1000100010001
+# CHECK: lui  $1, 1           # encoding: [0x01,0x00,0x01,0x3c]
+# CHECK: ori  $1, $1, 1       # encoding: [0x01,0x00,0x21,0x34]
+# CHECK: dsll $1, $1, 16      # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori  $1, $1, 1       # encoding: [0x01,0x00,0x21,0x34]
+# CHECK: dsll $1, $1, 16      # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori  $1, $1, 1       # encoding: [0x01,0x00,0x21,0x34]
+# CHECK: lwl  $8, 3($1)       # encoding: [0x03,0x00,0x28,0x88]
+# CHECK: lwr  $8, 0($1)       # encoding: [0x00,0x00,0x28,0x98]
+
+  ulw $8, -0x100010001
+# CHECK: lui  $1, 65535       # encoding: [0xff,0xff,0x01,0x3c]
+# CHECK: ori  $1, $1, 65534   # encoding: [0xfe,0xff,0x21,0x34]
+# CHECK: dsll $1, $1, 16      # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori  $1, $1, 65534   # encoding: [0xfe,0xff,0x21,0x34]
+# CHECK: dsll $1, $1, 16      # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori  $1, $1, 65535   # encoding: [0xff,0xff,0x21,0x34]
+# CHECK: lwl  $8, 3($1)       # encoding: [0x03,0x00,0x28,0x88]
+# CHECK: lwr  $8, 0($1)       # encoding: [0x00,0x00,0x28,0x98]
+
+  ulw $8, -0x1000100010001
+# CHECK: lui  $1, 65534       # encoding: [0xfe,0xff,0x01,0x3c]
+# CHECK: ori  $1, $1, 65534   # encoding: [0xfe,0xff,0x21,0x34]
+# CHECK: dsll $1, $1, 16      # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori  $1, $1, 65534   # encoding: [0xfe,0xff,0x21,0x34]
+# CHECK: dsll $1, $1, 16      # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori  $1, $1, 65535   # encoding: [0xff,0xff,0x21,0x34]
+# CHECK: lwl  $8, 3($1)       # encoding: [0x03,0x00,0x28,0x88]
+# CHECK: lwr  $8, 0($1)       # encoding: [0x00,0x00,0x28,0x98]
+
+# Test ulw with source register and 64-bit immediate offset.
+  ulw $8, 0x100010001($9)
+# CHECK: lui   $1, 1          # encoding: [0x01,0x00,0x01,0x3c]
+# CHECK: ori   $1, $1, 1      # encoding: [0x01,0x00,0x21,0x34]
+# CHECK: dsll  $1, $1, 16     # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori   $1, $1, 1      # encoding: [0x01,0x00,0x21,0x34]
+# CHECK: daddu $1, $1, $9     # encoding: [0x2d,0x08,0x29,0x00]
+# CHECK: lwl   $8, 3($1)      # encoding: [0x03,0x00,0x28,0x88]
+# CHECK: lwr   $8, 0($1)      # encoding: [0x00,0x00,0x28,0x98]
+
+  ulw $8, 0x1000100010001($9)
+# CHECK: lui   $1, 1          # encoding: [0x01,0x00,0x01,0x3c]
+# CHECK: ori   $1, $1, 1      # encoding: [0x01,0x00,0x21,0x34]
+# CHECK: dsll  $1, $1, 16     # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori   $1, $1, 1      # encoding: [0x01,0x00,0x21,0x34]
+# CHECK: dsll  $1, $1, 16     # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori   $1, $1, 1      # encoding: [0x01,0x00,0x21,0x34]
+# CHECK: daddu $1, $1, $9     # encoding: [0x2d,0x08,0x29,0x00]
+# CHECK: lwl   $8, 3($1)      # encoding: [0x03,0x00,0x28,0x88]
+# CHECK: lwr   $8, 0($1)      # encoding: [0x00,0x00,0x28,0x98]
+
+  ulw $8, -0x100010001($9)
+# CHECK: lui   $1, 65535      # encoding: [0xff,0xff,0x01,0x3c]
+# CHECK: ori   $1, $1, 65534  # encoding: [0xfe,0xff,0x21,0x34]
+# CHECK: dsll  $1, $1, 16     # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori   $1, $1, 65534  # encoding: [0xfe,0xff,0x21,0x34]
+# CHECK: dsll  $1, $1, 16     # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori   $1, $1, 65535  # encoding: [0xff,0xff,0x21,0x34]
+# CHECK: daddu $1, $1, $9     # encoding: [0x2d,0x08,0x29,0x00]
+# CHECK: lwl   $8, 3($1)      # encoding: [0x03,0x00,0x28,0x88]
+# CHECK: lwr   $8, 0($1)      # encoding: [0x00,0x00,0x28,0x98]
+
+  ulw $8, -0x1000100010001($9)
+# CHECK: lui   $1, 65534      # encoding: [0xfe,0xff,0x01,0x3c]
+# CHECK: ori   $1, $1, 65534  # encoding: [0xfe,0xff,0x21,0x34]
+# CHECK: dsll  $1, $1, 16     # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori   $1, $1, 65534  # encoding: [0xfe,0xff,0x21,0x34]
+# CHECK: dsll  $1, $1, 16     # encoding: [0x38,0x0c,0x01,0x00]
+# CHECK: ori   $1, $1, 65535  # encoding: [0xff,0xff,0x21,0x34]
+# CHECK: daddu $1, $1, $9     # encoding: [0x2d,0x08,0x29,0x00]
+# CHECK: lwl   $8, 3($1)      # encoding: [0x03,0x00,0x28,0x88]
+# CHECK: lwr   $8, 0($1)      # encoding: [0x00,0x00,0x28,0x98]

diff --git a/test/MC/Mips/set-nomacro.s b/test/MC/Mips/set-nomacro.s
index 3936bccb45a512790005d15f6f48beaae2247bc0..3f82f81613158162845326d2677901bad75db0dd 100644 (file)
--- a/test/MC/Mips/set-nomacro.s
+++ b/test/MC/Mips/set-nomacro.s
@@ -62,6 +62,11 @@
 
   ulhu $5, 0
 
+  ulw $8, 2
+  ulw $8, 0x8000
+  ulw $8, 2($9)
+  ulw $8, 0x8000($9)
+
   add $4, $5, $6
 
   .set noreorder
@@ -173,5 +178,14 @@
   ulhu $5, 0
 # CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
 
+  ulw $8, 2
+# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+  ulw $8, 0x8000
+# CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+  ulw $8, 2($9)
+# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+  ulw $8, 0x8000($9)
+# CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
+
   add $4, $5, $6
 # CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions