#include <mach/imx-uart.h>
#include <mach/iomux-mx3.h>
+#include "devices.h"
+
/*!
* @file mx31ads.c
*
.virtual = AIPS1_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(AIPS1_BASE_ADDR),
.length = AIPS1_SIZE,
- .type = MT_DEVICE
+ .type = MT_DEVICE_NONSHARED
}, {
.virtual = AIPS2_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(AIPS2_BASE_ADDR),
.length = AIPS2_SIZE,
- .type = MT_DEVICE
+ .type = MT_DEVICE_NONSHARED
},
};
struct mxc_gpio_port *port =
container_of(chip, struct mxc_gpio_port, chip);
- return (__raw_readl(port->base + GPIO_DR) >> offset) & 1;
+ return (__raw_readl(port->base + GPIO_PSR) >> offset) & 1;
}
static int mxc_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
/* Allow IO space to be anywhere in the memory */
#define IO_SPACE_LIMIT 0xffffffff
+#ifdef CONFIG_ARCH_MX3
+#define __arch_ioremap __mx3_ioremap
+#define __arch_iounmap __iounmap
+
+static inline void __iomem *
+__mx3_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
+{
+ if (mtype == MT_DEVICE) {
+ /* Access all peripherals below 0x80000000 as nonshared device
+ * but leave l2cc alone.
+ */
+ if ((phys_addr < 0x80000000) && ((phys_addr < L2CC_BASE_ADDR) ||
+ (phys_addr >= L2CC_BASE_ADDR + L2CC_SIZE)))
+ mtype = MT_DEVICE_NONSHARED;
+ }
+
+ return __arm_ioremap(phys_addr, size, mtype);
+}
+#endif
+
/* io address mapping macro */
#define __io(a) ((void __iomem *)(a))
say Y or M. Otherwise, say N.
config SERIAL_NETX
- bool "NetX serial port support"
+ tristate "NetX serial port support"
depends on ARM && ARCH_NETX
select SERIAL_CORE
help
config SERIAL_NETX_CONSOLE
bool "Console on NetX serial port"
- depends on SERIAL_NETX
+ depends on SERIAL_NETX=y
select SERIAL_CORE_CONSOLE
help
If you have enabled the serial port on the Hilscher NetX SoC
#define SERIAL_NX_MAJOR 204
#define MINOR_START 170
-#ifdef CONFIG_SERIAL_NETX_CONSOLE
-
enum uart_regs {
UART_DR = 0x00,
UART_SR = 0x04,
}
};
+#ifdef CONFIG_SERIAL_NETX_CONSOLE
+
static void netx_console_putchar(struct uart_port *port, int ch)
{
while (readl(port->membase + UART_FR) & FR_BUSY);