ARM64: dts: rockchip: rk3366: modify the initial rate of wifi pll

There is a div2 behind wifi pll, so the initial rate should be 960MHz.

Change-Id: Ib90457a0b17907c3056adf58edd623ae462b06a3
Signed-off-by: Feng Xiao <xf@rock-chips.com>

diff --git a/arch/arm64/boot/dts/rockchip/rk3366.dtsi b/arch/arm64/boot/dts/rockchip/rk3366.dtsi
index 5e95e4187db41242de8e1c4075ba5352eb92ce8a..b86c33f97dc4a1c930b82ee0a67d872018fd03e0 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3366.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3366.dtsi
@@ -624,7 +624,7 @@
                assigned-clock-rates =
                        <750000000>, <576000000>,
                        <594000000>, <594000000>,
-                       <480000000>, <520000000>,
+                       <960000000>, <520000000>,
                        <375000000>, <288000000>,
                        <100000000>, <100000000>;
        };