[ARM] tegra: Set bit 22 in the PL310 AuxCtrl

Duplicate Catalin Marinas' <catalin.marinas@arm.com> ARM change
6395/1 for VExpress to tegra

Clearing bit 22 in the PL310 Auxiliary Control register (shared
attribute override enable) has the side effect of transforming Normal
Shared Non-cacheable reads into Cacheable no-allocate reads.

Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption.

Change-Id: I37232041c035f5153a7ad73257c6333634a5f4b8
Signed-off-by: Gary King <gking@nvidia.com>

diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index d8adca772d6bb1b633474513951ec9f2c48c65b0..99eb45eb30c3eb0d1da22a706c7442b8669ce7e0 100644 (file)
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -62,7 +62,7 @@ void __init tegra_init_cache(void)
        writel(0x331, p + L2X0_TAG_LATENCY_CTRL);
        writel(0x441, p + L2X0_DATA_LATENCY_CTRL);
 
-       l2x0_init(p, 0x6C080001, 0x8200c3fe);
+       l2x0_init(p, 0x6C480001, 0x8200c3fe);
 #endif
 
 }