(INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
def : Pat<(v2i64 (opnode (v2i64 VPR128:$src), VPR128:$Rn, VPR128:$Rm)),
(INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
- def : Pat<(v2f64 (opnode (v2i64 VPR128:$src), VPR128:$Rn, VPR128:$Rm)),
- (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
- def : Pat<(v4f32 (opnode (v4i32 VPR128:$src), VPR128:$Rn, VPR128:$Rm)),
- (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
// Allow to match BSL instruction pattern with non-constant operand
def : Pat<(v8i8 (or (and VPR64:$Rn, VPR64:$Rd),
ret <2 x double> %vbsl3.i
}
-define <2 x double> @bsl2xf64(<2 x i1> %v1, <2 x double> %v2, <2 x double> %v3) {
-;CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
- %1 = select <2 x i1> %v1, <2 x double> %v2, <2 x double> %v3
- ret <2 x double> %1
-}
-
-define <4 x float> @bsl4xf32(<4 x i1> %v1, <4 x float> %v2, <4 x float> %v3) {
-;CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
- %1 = select <4 x i1> %v1, <4 x float> %v2, <4 x float> %v3
- ret <4 x float> %1
-}