Add bogus conditional branch before stlx

diff --git a/lib/CodeGen/CodeGenPrepare.cpp b/lib/CodeGen/CodeGenPrepare.cpp
index 1837ba2bd5d4678d3f5132aaf421f6c9ac4a25bd..f4ff3787e630347a89b3737db4ebb16239df75e5 100644 (file)
--- a/lib/CodeGen/CodeGenPrepare.cpp
+++ b/lib/CodeGen/CodeGenPrepare.cpp
@@ -710,11 +710,11 @@ Instruction* findFirstStoreCondBranchInst(LoadInst* LI, Vector* ChainedBB) {
   BBI++;
   while (true) {
     for (; BBI != BE; BBI++) {
-      auto* Inst = dyn_cast<Instruction>(&*BBI);
-      if (Inst == nullptr) {
-        continue;
-      }
-      if (Inst->getOpcode() == Instruction::Store) {
+      Instruction* Inst = &*BBI;
+      IntrinsicInst* II = dyn_cast<IntrinsicInst>(&*BBI);
+      if (II && II->getIntrinsicID() == Intrinsic::aarch64_stlxr) {
+        return II;
+      } else if (Inst->getOpcode() == Instruction::Store) {
         return Inst;
       } else if (Inst->getOpcode() == Instruction::Br) {
         auto* BrInst = dyn_cast<BranchInst>(Inst);
@@ -759,35 +759,6 @@ Instruction* findLastLoadNext(Instruction* FromInst, Instruction* ToInst) {
   return LastLoad;
 }
 
-// XXX-comment: Returns whether the code has been changed.
-bool taintMonotonicLoads(const SmallVector<LoadInst*, 1>& MonotonicLoadInsts) {
-  bool Changed = false;
-  for (auto* LI : MonotonicLoadInsts) {
-    SmallVector<BasicBlock*, 2> ChainedBB;
-    auto* FirstInst = findFirstStoreCondBranchInst(LI, &ChainedBB);
-    if (FirstInst == nullptr) {
-      // We don't seem to be able to taint a following store/conditional branch
-      // instruction. Simply make it acquire.
-      DEBUG(dbgs() << "[RelaxedLoad]: Transformed to acquire load\n"
-                   << *LI << "\n");
-      LI->setOrdering(Acquire);
-      Changed = true;
-      continue;
-    }
-    // Taint 'FirstInst', which could be a store or a condition branch
-    // instruction.
-    if (FirstInst->getOpcode() == Instruction::Store) {
-      Changed |= taintStoreAddress(dyn_cast<StoreInst>(FirstInst), LI);
-    } else if (FirstInst->getOpcode() == Instruction::Br) {
-      Changed |= taintConditionalBranch(dyn_cast<BranchInst>(FirstInst), LI);
-    } else {
-      assert(false && "findFirstStoreCondBranchInst() should return a "
-                    "store/condition branch instruction");
-    }
-  }
-  return Changed;
-}
-
 // Inserts a fake conditional branch right after the instruction 'SplitInst',
 // and the branch condition is 'Condition'. 'SplitInst' will be placed in the
 // newly created block.
@@ -984,18 +955,28 @@ bool AddFakeConditionalBranchAfterMonotonicLoads(
           continue;
         }
       } else {
-        dbgs() << "FirstInst=" << *FirstInst << "\n";
-        assert(false && "findFirstStoreCondBranchInst() should return a "
-                        "store/condition branch instruction");
+        IntrinsicInst* II = dyn_cast<IntrinsicInst>(FirstInst);
+        if (!II || II->getIntrinsicID() != Intrinsic::aarch64_stlxr) {
+          dbgs() << "FirstInst=" << *FirstInst << "\n";
+          assert(false && "findFirstStoreCondBranchInst() should return a "
+                          "store/condition branch instruction");
+        }
       }
     }
 
     // We really need to process the relaxed load now.
-    StoreInst* SI = nullptr;;
-    if (FirstInst && (SI = dyn_cast<StoreInst>(FirstInst))) {
+    StoreInst* SI = nullptr;
+    IntrinsicInst* II = nullptr;
+    if (FirstInst) {
+      SI = dyn_cast<StoreInst>(FirstInst);
+      II = dyn_cast<IntrinsicInst>(FirstInst);
+    }
+    if (FirstInst &&
+        (SI || (II && II->getIntrinsicID() == Intrinsic::aarch64_stlxr))) {
       // For immediately coming stores, taint the address of the store.
-      if (SI->getParent() == LI->getParent() || DT->dominates(LI, SI)) {
-        TaintRelaxedLoads(LI, SI);
+      if (FirstInst->getParent() == LI->getParent() ||
+          DT->dominates(LI, FirstInst)) {
+        TaintRelaxedLoads(LI, FirstInst);
         Changed = true;
       } else {
         auto* Inst =
@@ -1004,7 +985,7 @@ bool AddFakeConditionalBranchAfterMonotonicLoads(
           LI->setOrdering(Acquire);
           Changed = true;
         } else {
-          TaintRelaxedLoads(Inst, SI);
+          TaintRelaxedLoads(Inst, FirstInst);
           Changed = true;
         }
       }