clk: rockchip: rk3399: fix PPLL is redefined and ID shouldn't be 0

PPLL is 8 and redefined by SCLK_I2C4_PMU, and clock IDs shouldn't be 0.

Change-Id: I50f89487034c1f1ef41d257de00b7f3ec53f7f4c
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h
index 0715e66db20a29b2df23d8fdf727a48d6db78ecd..51122c0146c177ce37533b512af8a0e2e2164f98 100644 (file)
--- a/include/dt-bindings/clock/rk3399-cru.h
+++ b/include/dt-bindings/clock/rk3399-cru.h
@@ -24,9 +24,8 @@
 #define PLL_GPLL                       5
 #define PLL_NPLL                       6
 #define PLL_VPLL                       7
-#define PLL_PPLL                       8
-#define ARMCLKL                                9
-#define ARMCLKB                                10
+#define ARMCLKL                                8
+#define ARMCLKB                                9
 
 /* sclk gates (special clocks) */
 #define SCLK_I2C1                      65
@@ -337,16 +336,19 @@
 #define CLK_NR_CLKS                    (HCLK_SDIOAUDIO_NOC + 1)
 
 /* pmu-clocks indices */
-#define SCLK_32K_SUSPEND_PMU           0
-#define SCLK_SPI3_PMU                  1
-#define SCLK_TIMER12_PMU               2
-#define SCLK_TIMER13_PMU               3
-#define SCLK_UART4_PMU                 4
-#define SCLK_PVTM_PMU                  5
-#define SCLK_WIFI_PMU                  6
-#define SCLK_I2C0_PMU                  7
-#define SCLK_I2C4_PMU                  8
-#define SCLK_I2C8_PMU                  9
+
+#define PLL_PPLL                       1
+
+#define SCLK_32K_SUSPEND_PMU           2
+#define SCLK_SPI3_PMU                  3
+#define SCLK_TIMER12_PMU               4
+#define SCLK_TIMER13_PMU               5
+#define SCLK_UART4_PMU                 6
+#define SCLK_PVTM_PMU                  7
+#define SCLK_WIFI_PMU                  8
+#define SCLK_I2C0_PMU                  9
+#define SCLK_I2C4_PMU                  10
+#define SCLK_I2C8_PMU                  11
 
 #define PCLK_SRC_PMU                   19
 #define PCLK_PMU                       20