Teach the scheduler to emit the appropriate INLINEASM MachineInstr for an

ISD::INLINEASM node.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25668 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
index 6ffa9c720d02cbe82f697bebcbc717a205277d83..4e45bd65646b1b537801a235c2afc29448848ae3 100644 (file)
--- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
@@ -283,6 +283,35 @@ void ScheduleDAG::EmitNode(NodeInfo *NI) {
       MRI->copyRegToReg(*BB, BB->end(), VRBase, SrcReg, TRC);
       break;
     }
+    case ISD::INLINEASM: {
+      unsigned NumOps = Node->getNumOperands();
+      if (Node->getOperand(NumOps-1).getValueType() == MVT::Flag)
+        --NumOps;  // Ignore the flag operand.
+      
+      // Create the inline asm machine instruction.
+      MachineInstr *MI =
+        new MachineInstr(BB, TargetInstrInfo::INLINEASM, (NumOps-2)/2+1);
+
+      // Add the asm string as an external symbol operand.
+      const char *AsmStr =
+        cast<ExternalSymbolSDNode>(Node->getOperand(1))->getSymbol();
+      MI->addExternalSymbolOperand(AsmStr, false);
+      
+      // Add all of the operand registers to the instruction.
+      for (unsigned i = 2; i != NumOps; i += 2) {
+        unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
+        unsigned Flags = cast<ConstantSDNode>(Node->getOperand(i))->getValue();
+        MachineOperand::UseType UseTy;
+        switch (Flags) {
+        default: assert(0 && "Bad flags!");
+        case 1: UseTy = MachineOperand::Use; break;
+        case 2: UseTy = MachineOperand::Def; break;
+        case 3: UseTy = MachineOperand::UseAndDef; break;
+        }
+        MI->addMachineRegOperand(Reg, UseTy);
+      }
+      break;
+    }
     }
   }