implement CodeGen/X86/inline-asm-x-scalar.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35799 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 4c54a285cd38b63f816d63ff77118567ce2fda2b..94305eef5b745fab49584a3cfe9b35483403fb91 100644 (file)
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -4640,7 +4640,6 @@ isOperandValidForConstraint(SDOperand Op, char Constraint, SelectionDAG &DAG) {
   return TargetLowering::isOperandValidForConstraint(Op, Constraint, DAG);
 }
 
-
 std::vector<unsigned> X86TargetLowering::
 getRegClassForInlineAsmConstraint(const std::string &Constraint,
                                   MVT::ValueType VT) const {
@@ -4709,6 +4708,21 @@ getRegClassForInlineAsmConstraint(const std::string &Constraint,
 std::pair<unsigned, const TargetRegisterClass*>
 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
                                                 MVT::ValueType VT) const {
+  // First, see if this is a constraint that directly corresponds to an LLVM
+  // register class.
+  if (Constraint.size() == 1) {
+    // GCC Constraint Letters
+    switch (Constraint[0]) {
+    default: break;
+    case 'x': 
+      if (VT == MVT::f32)
+        return std::make_pair(0U, X86::FR32RegisterClass);
+      if (VT == MVT::f64)
+        return std::make_pair(0U, X86::FR64RegisterClass);
+      break;
+    }
+  }
+  
   // Use the default implementation in TargetLowering to convert the register
   // constraint into a member of a register class.
   std::pair<unsigned, const TargetRegisterClass*> Res;