Move subreg lowering pass to be right after regalloc, per feedback.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40548 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/LLVMTargetMachine.cpp b/lib/CodeGen/LLVMTargetMachine.cpp
index 4620abb7211b00afeddde09165f9c40ae848b7d5..526c5255fe3a277dd96fc40cae5fba2cf4a0dced 100644 (file)
--- a/lib/CodeGen/LLVMTargetMachine.cpp
+++ b/lib/CodeGen/LLVMTargetMachine.cpp
@@ -72,6 +72,11 @@ LLVMTargetMachine::addPassesToEmitFile(FunctionPassManager &PM,
   
   if (PrintMachineCode)
     PM.add(createMachineFunctionPrinterPass(cerr));
+    
+  PM.add(createLowerSubregsPass());
+  
+  if (PrintMachineCode)  // Print the subreg lowered code
+    PM.add(createMachineFunctionPrinterPass(cerr));
 
   // Run post-ra passes.
   if (addPostRegAlloc(PM, Fast) && PrintMachineCode)
@@ -96,8 +101,6 @@ LLVMTargetMachine::addPassesToEmitFile(FunctionPassManager &PM,
 
   if (addPreEmitPass(PM, Fast) && PrintMachineCode)
     PM.add(createMachineFunctionPrinterPass(cerr));
-    
-  PM.add(createLowerSubregsPass());
 
   switch (FileType) {
   default:
@@ -178,6 +181,11 @@ bool LLVMTargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
   
   if (PrintMachineCode)
     PM.add(createMachineFunctionPrinterPass(cerr));
+    
+  PM.add(createLowerSubregsPass());
+  
+  if (PrintMachineCode)  // Print the subreg lowered code
+    PM.add(createMachineFunctionPrinterPass(cerr));
 
   // Run post-ra passes.
   if (addPostRegAlloc(PM, Fast) && PrintMachineCode)
@@ -199,8 +207,6 @@ bool LLVMTargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
   
   if (addPreEmitPass(PM, Fast) && PrintMachineCode)
     PM.add(createMachineFunctionPrinterPass(cerr));
-    
-  PM.add(createLowerSubregsPass());
 
   addCodeEmitter(PM, Fast, PrintEmittedAsm, MCE);