Add another accidentally omitted predicate operand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137370 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index b5adc4977e6568129bd0d6f4a3526866bfa4f640..240293a2e67d3602f03f15273edaea712aff2d8a 100644 (file)
--- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -2491,6 +2491,7 @@ static bool DecodeDoubleRegExclusive(llvm::MCInst &Inst, unsigned Insn,
   unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
   unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
   unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
+  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
 
   if (Inst.getOpcode() == ARM::STREXD)
     if (!DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
@@ -2501,6 +2502,7 @@ static bool DecodeDoubleRegExclusive(llvm::MCInst &Inst, unsigned Insn,
   if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false;
   if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)) return false;
   if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
+  if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false;
 
   return true;
 }